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Reel/Frame:056193/0280   Pages: 3
Recorded: 02/04/2021
Attorney Dkt #:234802-30018
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
03/23/2021
Application #:
16731484
Filing Dt:
12/31/2019
Title:
METHOD TO REDUCE FULL-CHIP TIMING VIOLATION THROUGH TIME BUDGETING IN INTEGRATED CIRCUIT DESIGN
Assignor
1
Exec Dt:
01/10/2021
Assignee
1
1601 S. MOPAC EXPY,
D300
AUSTIN, TEXAS 78746
Correspondence name and address
LOEB & LOEB LLP
321 N. CLARK STREET
SUITE 2300
CHICAGO, IL 60654

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