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Reel/Frame:056602/0990   Pages: 4
Recorded: 06/16/2021
Attorney Dkt #:CONVERSANT TO MOSAID
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 30
1
Patent #:
Issue Dt:
10/09/2007
Application #:
10996739
Filing Dt:
11/24/2004
Publication #:
Pub Dt:
01/12/2006
Title:
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
2
Patent #:
Issue Dt:
06/05/2007
Application #:
11041687
Filing Dt:
01/20/2005
Publication #:
Pub Dt:
08/25/2005
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
3
Patent #:
Issue Dt:
07/20/2010
Application #:
11322160
Filing Dt:
12/29/2005
Publication #:
Pub Dt:
07/05/2007
Title:
ASIC DESIGN USING CLOCK AND POWER GRID STANDARD CELL
4
Patent #:
Issue Dt:
03/24/2009
Application #:
11433158
Filing Dt:
05/12/2006
Publication #:
Pub Dt:
11/23/2006
Title:
INTEGRATED CIRCUIT WITH SIGNAL BUS FORMED BY CELL ABUTMENT OF LOGIC CELLS
5
Patent #:
Issue Dt:
01/29/2013
Application #:
11521734
Filing Dt:
09/15/2006
Publication #:
Pub Dt:
10/04/2007
Title:
ASYNCHRONOUS ID GENERATION
6
Patent #:
Issue Dt:
02/09/2010
Application #:
11536709
Filing Dt:
09/29/2006
Publication #:
Pub Dt:
12/06/2007
Title:
APPARATUS AND METHOD FOR INTERFACING TO A MEMORY
7
Patent #:
Issue Dt:
04/07/2009
Application #:
11583354
Filing Dt:
10/19/2006
Publication #:
Pub Dt:
07/05/2007
Title:
MEMORY WITH OUTPUT CONTROL
8
Patent #:
Issue Dt:
06/29/2010
Application #:
11643850
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/21/2007
Title:
INDEPENDENT LINK AND BANK SELECTION
9
Patent #:
Issue Dt:
09/21/2010
Application #:
11693027
Filing Dt:
03/29/2007
Publication #:
Pub Dt:
10/04/2007
Title:
FLASH MEMORY SYSTEM CONTROL SCHEME
10
Patent #:
Issue Dt:
03/25/2008
Application #:
11732181
Filing Dt:
04/02/2007
Publication #:
Pub Dt:
08/02/2007
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
11
Patent #:
Issue Dt:
06/03/2008
Application #:
11900971
Filing Dt:
09/14/2007
Publication #:
Pub Dt:
01/10/2008
Title:
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
12
Patent #:
Issue Dt:
10/19/2010
Application #:
11944535
Filing Dt:
11/23/2007
Publication #:
Pub Dt:
05/29/2008
Title:
NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE
13
Patent #:
Issue Dt:
10/28/2008
Application #:
11998725
Filing Dt:
11/30/2007
Publication #:
Pub Dt:
04/10/2008
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
14
Patent #:
Issue Dt:
01/05/2010
Application #:
11998762
Filing Dt:
11/30/2007
Publication #:
Pub Dt:
04/17/2008
Title:
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
15
Patent #:
Issue Dt:
09/22/2009
Application #:
12284311
Filing Dt:
09/19/2008
Publication #:
Pub Dt:
01/29/2009
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
16
Patent #:
Issue Dt:
09/27/2011
Application #:
12368512
Filing Dt:
02/10/2009
Publication #:
Pub Dt:
06/04/2009
Title:
INTEGRATED CIRCUIT WITH SIGNAL BUS FORMED BY CELL ABUTMENT OF LOGIC CELLS
17
Patent #:
Issue Dt:
05/10/2011
Application #:
12542352
Filing Dt:
08/17/2009
Publication #:
Pub Dt:
03/11/2010
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
18
Patent #:
Issue Dt:
07/19/2011
Application #:
12620749
Filing Dt:
11/18/2009
Publication #:
Pub Dt:
03/18/2010
Title:
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
19
Patent #:
Issue Dt:
06/26/2012
Application #:
12684026
Filing Dt:
01/07/2010
Publication #:
Pub Dt:
05/13/2010
Title:
A DOUBLE DATA RATE CONVERTER CIRCUIT INCLUDES A DELAY LOCKED LOOP FOR PROVIDING THE PLURALITY OF CLOCK PHASE SIGNALS
20
Patent #:
Issue Dt:
05/17/2011
Application #:
12757406
Filing Dt:
04/09/2010
Publication #:
Pub Dt:
08/05/2010
Title:
INDEPENDENT LINK AND BANK SELECTION
21
Patent #:
Issue Dt:
10/16/2012
Application #:
12879566
Filing Dt:
09/10/2010
Publication #:
Pub Dt:
01/20/2011
Title:
NON-VOLATILE MEMORY BANK AND PAGE BUFFER THEREFOR
22
Patent #:
Issue Dt:
08/28/2012
Application #:
13074291
Filing Dt:
03/29/2011
Publication #:
Pub Dt:
10/27/2011
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
23
Patent #:
Issue Dt:
10/07/2014
Application #:
13569613
Filing Dt:
08/08/2012
Publication #:
Pub Dt:
01/31/2013
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
24
Patent #:
Issue Dt:
05/27/2014
Application #:
13608605
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
01/03/2013
Title:
INDEPENDENT LINK AND BANK SELECTION
25
Patent #:
Issue Dt:
11/04/2014
Application #:
13618022
Filing Dt:
09/14/2012
Publication #:
Pub Dt:
02/21/2013
Title:
NON-VOLATILE MEMORY BANK AND PAGE BUFFER THEREFOR
26
Patent #:
Issue Dt:
01/26/2021
Application #:
14209455
Filing Dt:
03/13/2014
Title:
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
27
Patent #:
Issue Dt:
05/24/2016
Application #:
14480143
Filing Dt:
09/08/2014
Publication #:
Pub Dt:
12/25/2014
Title:
Low Leakage and Data Retention Circuitry
28
Patent #:
Issue Dt:
02/14/2017
Application #:
14531432
Filing Dt:
11/03/2014
Publication #:
Pub Dt:
02/19/2015
Title:
NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE
29
Patent #:
Issue Dt:
08/01/2017
Application #:
15137424
Filing Dt:
04/25/2016
Publication #:
Pub Dt:
10/27/2016
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
30
Patent #:
Issue Dt:
06/26/2018
Application #:
15400432
Filing Dt:
01/06/2017
Publication #:
Pub Dt:
06/29/2017
Title:
NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE
Assignor
1
Exec Dt:
04/01/2021
Assignee
1
515 LEGGET DRIVE
SUITE 704
OTTAWA, CANADA K2K 3G4
Correspondence name and address
CONVERSANT IP MANAGEMENT CORP.
5830 GRANITE PARKWAY #100-247
SUITE 247
PLANO, TX 75024

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