Total properties:
30
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Patent #:
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Issue Dt:
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10/09/2007
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Application #:
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10996739
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Filing Dt:
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11/24/2004
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Publication #:
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Pub Dt:
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01/12/2006
| | | | |
Title:
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SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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11041687
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Filing Dt:
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01/20/2005
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Publication #:
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Pub Dt:
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08/25/2005
| | | | |
Title:
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LOW LEAKAGE AND DATA RETENTION CIRCUITRY
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Patent #:
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Issue Dt:
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07/20/2010
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Application #:
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11322160
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Filing Dt:
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12/29/2005
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Publication #:
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Pub Dt:
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07/05/2007
| | | | |
Title:
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ASIC DESIGN USING CLOCK AND POWER GRID STANDARD CELL
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Patent #:
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Issue Dt:
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03/24/2009
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Application #:
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11433158
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Filing Dt:
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05/12/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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INTEGRATED CIRCUIT WITH SIGNAL BUS FORMED BY CELL ABUTMENT OF LOGIC CELLS
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Patent #:
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Issue Dt:
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01/29/2013
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Application #:
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11521734
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Filing Dt:
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09/15/2006
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Publication #:
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Pub Dt:
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10/04/2007
| | | | |
Title:
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ASYNCHRONOUS ID GENERATION
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Patent #:
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Issue Dt:
|
02/09/2010
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Application #:
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11536709
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Filing Dt:
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09/29/2006
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Publication #:
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Pub Dt:
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12/06/2007
| | | | |
Title:
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APPARATUS AND METHOD FOR INTERFACING TO A MEMORY
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Patent #:
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Issue Dt:
|
04/07/2009
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Application #:
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11583354
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Filing Dt:
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10/19/2006
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Publication #:
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Pub Dt:
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07/05/2007
| | | | |
Title:
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MEMORY WITH OUTPUT CONTROL
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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11643850
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Filing Dt:
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12/22/2006
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Publication #:
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Pub Dt:
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06/21/2007
| | | | |
Title:
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INDEPENDENT LINK AND BANK SELECTION
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Patent #:
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Issue Dt:
|
09/21/2010
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Application #:
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11693027
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Filing Dt:
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03/29/2007
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Publication #:
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Pub Dt:
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10/04/2007
| | | | |
Title:
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FLASH MEMORY SYSTEM CONTROL SCHEME
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Patent #:
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Issue Dt:
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03/25/2008
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Application #:
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11732181
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Filing Dt:
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04/02/2007
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Publication #:
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Pub Dt:
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08/02/2007
| | | | |
Title:
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LOW LEAKAGE AND DATA RETENTION CIRCUITRY
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Patent #:
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Issue Dt:
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06/03/2008
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Application #:
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11900971
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Filing Dt:
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09/14/2007
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Publication #:
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Pub Dt:
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01/10/2008
| | | | |
Title:
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SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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11944535
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Filing Dt:
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11/23/2007
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Publication #:
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Pub Dt:
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05/29/2008
| | | | |
Title:
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NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE
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|
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Patent #:
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|
Issue Dt:
|
10/28/2008
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Application #:
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11998725
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Filing Dt:
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11/30/2007
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Publication #:
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|
Pub Dt:
|
04/10/2008
| | | | |
Title:
|
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
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|
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Patent #:
|
|
Issue Dt:
|
01/05/2010
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Application #:
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11998762
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Filing Dt:
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11/30/2007
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Publication #:
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|
Pub Dt:
|
04/17/2008
| | | | |
Title:
|
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
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|
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Patent #:
|
|
Issue Dt:
|
09/22/2009
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Application #:
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12284311
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Filing Dt:
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09/19/2008
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Publication #:
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|
Pub Dt:
|
01/29/2009
| | | | |
Title:
|
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
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|
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Patent #:
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|
Issue Dt:
|
09/27/2011
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Application #:
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12368512
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Filing Dt:
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02/10/2009
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Publication #:
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Pub Dt:
|
06/04/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH SIGNAL BUS FORMED BY CELL ABUTMENT OF LOGIC CELLS
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|
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Patent #:
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|
Issue Dt:
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05/10/2011
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Application #:
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12542352
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Filing Dt:
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08/17/2009
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Publication #:
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Pub Dt:
|
03/11/2010
| | | | |
Title:
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LOW LEAKAGE AND DATA RETENTION CIRCUITRY
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Patent #:
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|
Issue Dt:
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07/19/2011
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Application #:
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12620749
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Filing Dt:
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11/18/2009
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Publication #:
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|
Pub Dt:
|
03/18/2010
| | | | |
Title:
|
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
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|
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Patent #:
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|
Issue Dt:
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06/26/2012
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Application #:
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12684026
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Filing Dt:
|
01/07/2010
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Publication #:
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Pub Dt:
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05/13/2010
| | | | |
Title:
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A DOUBLE DATA RATE CONVERTER CIRCUIT INCLUDES A DELAY LOCKED LOOP FOR PROVIDING THE PLURALITY OF CLOCK PHASE SIGNALS
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Patent #:
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|
Issue Dt:
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05/17/2011
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Application #:
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12757406
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Filing Dt:
|
04/09/2010
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Publication #:
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Pub Dt:
|
08/05/2010
| | | | |
Title:
|
INDEPENDENT LINK AND BANK SELECTION
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|
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Patent #:
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|
Issue Dt:
|
10/16/2012
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Application #:
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12879566
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Filing Dt:
|
09/10/2010
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Publication #:
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Pub Dt:
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01/20/2011
| | | | |
Title:
|
NON-VOLATILE MEMORY BANK AND PAGE BUFFER THEREFOR
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|
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Patent #:
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|
Issue Dt:
|
08/28/2012
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Application #:
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13074291
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Filing Dt:
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03/29/2011
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Publication #:
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|
Pub Dt:
|
10/27/2011
| | | | |
Title:
|
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
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|
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Patent #:
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|
Issue Dt:
|
10/07/2014
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Application #:
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13569613
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Filing Dt:
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08/08/2012
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Publication #:
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Pub Dt:
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01/31/2013
| | | | |
Title:
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LOW LEAKAGE AND DATA RETENTION CIRCUITRY
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|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
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Application #:
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13608605
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Filing Dt:
|
09/10/2012
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Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
INDEPENDENT LINK AND BANK SELECTION
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|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
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Application #:
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13618022
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Filing Dt:
|
09/14/2012
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Publication #:
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|
Pub Dt:
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02/21/2013
| | | | |
Title:
|
NON-VOLATILE MEMORY BANK AND PAGE BUFFER THEREFOR
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|
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Patent #:
|
|
Issue Dt:
|
01/26/2021
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Application #:
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14209455
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Filing Dt:
|
03/13/2014
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Title:
|
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
05/24/2016
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Application #:
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14480143
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Filing Dt:
|
09/08/2014
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Publication #:
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|
Pub Dt:
|
12/25/2014
| | | | |
Title:
|
Low Leakage and Data Retention Circuitry
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|
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Patent #:
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|
Issue Dt:
|
02/14/2017
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Application #:
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14531432
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Filing Dt:
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11/03/2014
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Publication #:
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Pub Dt:
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02/19/2015
| | | | |
Title:
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NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE
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|
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Patent #:
|
|
Issue Dt:
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08/01/2017
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Application #:
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15137424
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Filing Dt:
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04/25/2016
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Publication #:
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Pub Dt:
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10/27/2016
| | | | |
Title:
|
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
|
|
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Patent #:
|
|
Issue Dt:
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06/26/2018
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Application #:
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15400432
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Filing Dt:
|
01/06/2017
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Publication #:
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Pub Dt:
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06/29/2017
| | | | |
Title:
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NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE
|
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