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Reel/Frame:056675/0285   Pages: 7
Recorded: 06/24/2021
Attorney Dkt #:VARIOUS
Conveyance: MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 84
1
Patent #:
Issue Dt:
05/21/2013
Application #:
13526443
Filing Dt:
06/18/2012
Title:
THROUGH-SILICON VIA IMPEDANCE EXTRACTION
2
Patent #:
Issue Dt:
12/16/2014
Application #:
13627933
Filing Dt:
09/26/2012
Publication #:
Pub Dt:
03/27/2014
Title:
ELECTRICAL HOTSPOT DETECTION, ANALYSIS AND CORRECTION
3
Patent #:
Issue Dt:
09/09/2014
Application #:
13709499
Filing Dt:
12/10/2012
Publication #:
Pub Dt:
07/25/2013
Title:
SIMULATION OF CIRCUITS WITH REPETITIVE ELEMENTS
4
Patent #:
Issue Dt:
09/16/2014
Application #:
13755587
Filing Dt:
01/31/2013
Publication #:
Pub Dt:
08/01/2013
Title:
Placement and Area Adjustment for Hierarchical Groups in Printed Circuit Board Design
5
Patent #:
Issue Dt:
12/02/2014
Application #:
13755686
Filing Dt:
01/31/2013
Publication #:
Pub Dt:
08/01/2013
Title:
VERIFICATION TEST SET AND TEST BENCH MAP MAINTENANCE
6
Patent #:
Issue Dt:
07/14/2015
Application #:
13755737
Filing Dt:
01/31/2013
Publication #:
Pub Dt:
09/05/2013
Title:
Execution Time Profiling for Interpreted Programming Languages
7
Patent #:
Issue Dt:
08/05/2014
Application #:
13763292
Filing Dt:
02/08/2013
Publication #:
Pub Dt:
08/14/2014
Title:
OPTICAL PROXIMITY CORRECTION FOR TOPOGRAPHICALLY NON-UNIFORM SUBSTRATES
8
Patent #:
Issue Dt:
01/14/2014
Application #:
13776598
Filing Dt:
02/25/2013
Title:
Circuit Instance Variation Probability System and Method
9
Patent #:
Issue Dt:
06/18/2019
Application #:
13783183
Filing Dt:
03/01/2013
Publication #:
Pub Dt:
11/21/2013
Title:
Virtual Use Of Electronic Design Automation Tools
10
Patent #:
Issue Dt:
12/09/2014
Application #:
13844310
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
08/21/2014
Title:
LAYOUT DECOMPOSITION FOR TRIPLE PATTERNING LITHOGRAPHY
11
Patent #:
Issue Dt:
07/11/2017
Application #:
13875267
Filing Dt:
05/01/2013
Publication #:
Pub Dt:
01/30/2014
Title:
DEBUG ENVIRONMENT FOR A MULTI USER HARDWARE ASSISTED VERIFICATION SYSTEM
12
Patent #:
Issue Dt:
03/31/2015
Application #:
13914529
Filing Dt:
06/10/2013
Publication #:
Pub Dt:
12/12/2013
Title:
Test Data Volume Reduction Based On Test Cube Properties
13
Patent #:
Issue Dt:
05/24/2016
Application #:
13919984
Filing Dt:
06/17/2013
Publication #:
Pub Dt:
12/18/2014
Title:
Test Generation For Test-Per-Clock
14
Patent #:
Issue Dt:
02/28/2017
Application #:
13924156
Filing Dt:
06/21/2013
Publication #:
Pub Dt:
01/02/2014
Title:
TEST BENCH TRANSACTION SYNCHRONIZATION IN A DEBUGGING ENVIRONMENT
15
Patent #:
Issue Dt:
09/13/2016
Application #:
13973998
Filing Dt:
08/22/2013
Publication #:
Pub Dt:
02/27/2014
Title:
GENERATING ROOT CAUSE CANDIDATES FOR YIELD ANALYSIS
16
Patent #:
Issue Dt:
06/21/2016
Application #:
13974006
Filing Dt:
08/22/2013
Publication #:
Pub Dt:
02/27/2014
Title:
DEFECT INJECTION FOR TRANSISTOR-LEVEL FAULT SIMULATION
17
Patent #:
Issue Dt:
06/16/2015
Application #:
14011995
Filing Dt:
08/28/2013
Title:
FAULTY CHAINS IDENTIFICATION WITHOUT MASKING CHAIN PATTERNS
18
Patent #:
Issue Dt:
07/05/2016
Application #:
14019365
Filing Dt:
09/05/2013
Publication #:
Pub Dt:
03/06/2014
Title:
FORMAL VERIFICATION OF BOOTH MULTIPLIERS
19
Patent #:
Issue Dt:
07/12/2016
Application #:
14022214
Filing Dt:
09/09/2013
Title:
TEST ACCESS ARCHITECTURE FOR MULTI-DIE CIRCUITS
20
Patent #:
Issue Dt:
06/27/2017
Application #:
14030011
Filing Dt:
09/18/2013
Title:
Test Access Architecture For Stacked Memory And Logic Dies
21
Patent #:
Issue Dt:
09/06/2016
Application #:
14149806
Filing Dt:
01/07/2014
Publication #:
Pub Dt:
07/10/2014
Title:
Determining Worst-Case Bit Patterns Based Upon Data-Dependent Jitter
22
Patent #:
Issue Dt:
11/20/2018
Application #:
14154029
Filing Dt:
01/13/2014
Title:
MODIFYING CODE TO REDUCE REDUNDANT OR UNNECESSARY POWER USAGE
23
Patent #:
Issue Dt:
08/01/2017
Application #:
14170804
Filing Dt:
02/03/2014
Publication #:
Pub Dt:
08/07/2014
Title:
SCAN-BASED TEST ARCHITECTURE FOR INTERCONNECTS IN STACKED DESIGNS
24
Patent #:
Issue Dt:
05/10/2016
Application #:
14183305
Filing Dt:
02/18/2014
Publication #:
Pub Dt:
08/21/2014
Title:
Test Architecture for Characterizing Interconnects in Stacked Designs
25
Patent #:
Issue Dt:
02/06/2018
Application #:
14216954
Filing Dt:
03/17/2014
Publication #:
Pub Dt:
10/30/2014
Title:
CLOUD SERVICES PLATFORM
26
Patent #:
Issue Dt:
03/01/2016
Application #:
14220696
Filing Dt:
03/20/2014
Publication #:
Pub Dt:
09/25/2014
Title:
Single Event Upset Mitigation for Electronic Design Synthesis
27
Patent #:
Issue Dt:
02/14/2017
Application #:
14298663
Filing Dt:
06/06/2014
Publication #:
Pub Dt:
12/11/2014
Title:
Logic Built-In Self-Test with High Test Coverage and Low Switching Activity
28
Patent #:
Issue Dt:
03/24/2015
Application #:
14463502
Filing Dt:
08/19/2014
Publication #:
Pub Dt:
12/04/2014
Title:
Generating A Convergent Circuit Design From A Functional Description Using Entities Having Access To The Functional Description And To Physical Design Information
29
Patent #:
Issue Dt:
05/03/2016
Application #:
14507831
Filing Dt:
10/07/2014
Title:
Modeling Substrate Noise Coupling For Circuit Simulation
30
Patent #:
Issue Dt:
06/28/2016
Application #:
14537504
Filing Dt:
11/10/2014
Publication #:
Pub Dt:
05/14/2015
Title:
CANONICAL FORMS OF LAYOUT PATTERNS
31
Patent #:
Issue Dt:
01/31/2017
Application #:
14537685
Filing Dt:
11/10/2014
Publication #:
Pub Dt:
06/18/2015
Title:
COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN
32
Patent #:
NONE
Issue Dt:
Application #:
14549224
Filing Dt:
11/20/2014
Publication #:
Pub Dt:
05/28/2015
Title:
Tag Based System For Leveraging Design Data
33
Patent #:
Issue Dt:
03/13/2018
Application #:
14554898
Filing Dt:
11/26/2014
Publication #:
Pub Dt:
05/28/2015
Title:
Channel Sharing For Testing Circuits Having Non-Identical Cores
34
Patent #:
Issue Dt:
05/10/2016
Application #:
14557739
Filing Dt:
12/02/2014
Publication #:
Pub Dt:
06/04/2015
Title:
Dynamic Shift For Test Pattern Compression
35
Patent #:
Issue Dt:
08/15/2017
Application #:
14567495
Filing Dt:
12/11/2014
Publication #:
Pub Dt:
12/03/2015
Title:
SYSTEM DESIGN MANAGEMENT
36
Patent #:
Issue Dt:
08/06/2019
Application #:
14633999
Filing Dt:
02/27/2015
Publication #:
Pub Dt:
09/03/2015
Title:
Scan Cell Selection For Partial Scan Designs
37
Patent #:
Issue Dt:
05/16/2017
Application #:
14642501
Filing Dt:
03/09/2015
Publication #:
Pub Dt:
09/10/2015
Title:
Isometric Test Compression With Low Toggling Activity
38
Patent #:
Issue Dt:
10/10/2017
Application #:
14663275
Filing Dt:
03/19/2015
Publication #:
Pub Dt:
03/03/2016
Title:
Connectivity-Aware Layout Data Reduction For Design Verification
39
Patent #:
Issue Dt:
05/03/2016
Application #:
14693304
Filing Dt:
04/22/2015
Publication #:
Pub Dt:
08/13/2015
Title:
Generating Guiding Patterns For Directed Self-Assembly
40
Patent #:
Issue Dt:
11/06/2018
Application #:
14710390
Filing Dt:
05/12/2015
Publication #:
Pub Dt:
11/12/2015
Title:
Low Power Testing Based On Dynamic Grouping Of Scan
41
Patent #:
Issue Dt:
02/20/2018
Application #:
14721191
Filing Dt:
05/26/2015
Publication #:
Pub Dt:
11/26/2015
Title:
NON-INTRUSIVE SOFTWARE VERIFICATION
42
Patent #:
Issue Dt:
07/17/2018
Application #:
14730009
Filing Dt:
06/03/2015
Publication #:
Pub Dt:
12/03/2015
Title:
PRELINKED EMBEDDING
43
Patent #:
Issue Dt:
05/16/2017
Application #:
14745231
Filing Dt:
06/19/2015
Publication #:
Pub Dt:
10/06/2016
Title:
DIRECTED SELF-ASSEMBLY-AWARE LAYOUT DECOMPOSITION FOR MULTIPLE PATTERNING
44
Patent #:
Issue Dt:
08/04/2020
Application #:
14793579
Filing Dt:
07/07/2015
Publication #:
Pub Dt:
01/07/2016
Title:
STATISTICAL CHANNEL ANALYSIS WITH CORRELATED INPUT PATTERNS
45
Patent #:
Issue Dt:
03/27/2018
Application #:
14824370
Filing Dt:
08/12/2015
Publication #:
Pub Dt:
08/04/2016
Title:
ADDITIVE DESIGN OF HEAT SINKS
46
Patent #:
Issue Dt:
08/13/2019
Application #:
14851429
Filing Dt:
09/11/2015
Publication #:
Pub Dt:
03/02/2017
Title:
SECURE PROTOCOL FOR CHIP AUTHENTICATION
47
Patent #:
Issue Dt:
10/15/2019
Application #:
14884611
Filing Dt:
10/15/2015
Publication #:
Pub Dt:
04/21/2016
Title:
Test Point Insertion For Low Test Pattern Counts
48
Patent #:
Issue Dt:
08/22/2017
Application #:
14931637
Filing Dt:
11/03/2015
Publication #:
Pub Dt:
05/05/2016
Title:
Chip-Scale Electrothermal Analysis
49
Patent #:
Issue Dt:
06/05/2018
Application #:
14941481
Filing Dt:
11/13/2015
Publication #:
Pub Dt:
05/18/2017
Title:
Low Power Corruption Of Memory In Emulation
50
Patent #:
Issue Dt:
06/11/2019
Application #:
14950947
Filing Dt:
11/24/2015
Publication #:
Pub Dt:
05/26/2016
Title:
EXECUTION OF COMPLEX RECURSIVE ALGORITHMS
51
Patent #:
Issue Dt:
07/10/2018
Application #:
15006289
Filing Dt:
01/26/2016
Publication #:
Pub Dt:
08/11/2016
Title:
CLASS OBJECT HANDLE TRACKING
52
Patent #:
Issue Dt:
11/14/2017
Application #:
15007440
Filing Dt:
01/27/2016
Publication #:
Pub Dt:
06/08/2017
Title:
RECOGNIZING AND UTILIZING CIRCUIT TOPOLOGY IN AN ELECTRONIC CIRCUIT DESIGN
53
Patent #:
Issue Dt:
11/20/2018
Application #:
15011276
Filing Dt:
01/29/2016
Publication #:
Pub Dt:
12/08/2016
Title:
COVERAGE DATA INTERCHANGE
54
Patent #:
Issue Dt:
04/03/2018
Application #:
15051063
Filing Dt:
02/23/2016
Publication #:
Pub Dt:
08/25/2016
Title:
Deterministic Built-In Self-Test Based On Compressed Test Patterns Stored On Chip And Their Derivatives
55
Patent #:
Issue Dt:
06/04/2019
Application #:
15084993
Filing Dt:
03/30/2016
Publication #:
Pub Dt:
10/06/2016
Title:
Guiding Patterns Optimization For Directed Self-Assembly
56
Patent #:
Issue Dt:
12/05/2017
Application #:
15085044
Filing Dt:
03/30/2016
Publication #:
Pub Dt:
10/06/2016
Title:
Leakage Reduction Using Stress-Enhancing Filler Cells
57
Patent #:
Issue Dt:
07/03/2018
Application #:
15201294
Filing Dt:
07/01/2016
Publication #:
Pub Dt:
10/05/2017
Title:
Full-Chip Assessment Of Time-Dependent Dielectric Breakdown
58
Patent #:
Issue Dt:
05/01/2018
Application #:
15207383
Filing Dt:
07/11/2016
Publication #:
Pub Dt:
04/13/2017
Title:
Hybrid Compilation For FPGA Prototyping
59
Patent #:
Issue Dt:
10/24/2017
Application #:
15245869
Filing Dt:
08/24/2016
Publication #:
Pub Dt:
12/15/2016
Title:
PATTERN OPTICAL SIMILARITY DETERMINATION
60
Patent #:
Issue Dt:
06/11/2019
Application #:
15287537
Filing Dt:
10/06/2016
Publication #:
Pub Dt:
03/08/2018
Title:
LOW-LEVEL SENSOR FUSION
61
Patent #:
Issue Dt:
07/23/2019
Application #:
15353412
Filing Dt:
11/16/2016
Publication #:
Pub Dt:
05/18/2017
Title:
Test Point-Enhanced Hardware Security
62
Patent #:
Issue Dt:
03/17/2020
Application #:
15362510
Filing Dt:
11/28/2016
Publication #:
Pub Dt:
06/08/2017
Title:
ASSERTION STATEMENT CHECK AND DEBUG
63
Patent #:
Issue Dt:
03/05/2019
Application #:
15400904
Filing Dt:
01/06/2017
Publication #:
Pub Dt:
07/06/2017
Title:
TRANSITION TEST GENERATION FOR DETECTING CELL INTERNAL DEFECTS
64
Patent #:
Issue Dt:
03/19/2019
Application #:
15454909
Filing Dt:
03/09/2017
Title:
Circuit Defect Diagnosis Based On Sink Cell Fault Models
65
Patent #:
Issue Dt:
06/18/2019
Application #:
15454963
Filing Dt:
03/09/2017
Publication #:
Pub Dt:
10/05/2017
Title:
Automatic Axial Thrust Analysis Of Turbomachinery Designs
66
Patent #:
Issue Dt:
02/18/2020
Application #:
15458727
Filing Dt:
03/14/2017
Publication #:
Pub Dt:
09/14/2017
Title:
COMMUNICATION CIRCUITRY IN AN ELECTRONIC CONTROL UNIT
67
Patent #:
Issue Dt:
09/04/2018
Application #:
15472364
Filing Dt:
03/29/2017
Publication #:
Pub Dt:
10/05/2017
Title:
Correcting EUV Crosstalk Effects For Lithography Simulation
68
Patent #:
Issue Dt:
06/11/2019
Application #:
15592763
Filing Dt:
05/11/2017
Publication #:
Pub Dt:
11/16/2017
Title:
Wide-Range Clock Signal Generation For Speed Grading Of Logic Cores
69
Patent #:
Issue Dt:
10/12/2021
Application #:
15594382
Filing Dt:
05/12/2017
Publication #:
Pub Dt:
12/07/2017
Title:
VIRTUAL ETHERNET MUTABLE PORT GROUP TRANSACTOR
70
Patent #:
Issue Dt:
12/10/2019
Application #:
15669283
Filing Dt:
08/04/2017
Publication #:
Pub Dt:
11/23/2017
Title:
TARGET CAPTURE AND REPLAY IN EMULATION
71
Patent #:
Issue Dt:
09/10/2019
Application #:
15724262
Filing Dt:
10/03/2017
Title:
CONTENT ADDRESSABLE MEMORY MODELING IN EMULATION AND PROTOTYPING
72
Patent #:
Issue Dt:
12/03/2019
Application #:
15724264
Filing Dt:
10/03/2017
Title:
Dynamic Model Generation For Lithographic Simulation
73
Patent #:
Issue Dt:
03/10/2020
Application #:
15789719
Filing Dt:
10/20/2017
Publication #:
Pub Dt:
04/26/2018
Title:
REMOVAL OF ARTIFICIAL RESONANCES USING BOUNDARY ELEMENT METHOD
74
Patent #:
Issue Dt:
04/21/2020
Application #:
15792078
Filing Dt:
10/24/2017
Publication #:
Pub Dt:
04/26/2018
Title:
Flow Control In Networking System-On-Chip Verification
75
Patent #:
Issue Dt:
01/19/2021
Application #:
15792158
Filing Dt:
10/24/2017
Publication #:
Pub Dt:
11/01/2018
Title:
Determination Of Structure Function Feature Correlation To Thermal Model Element Layers
76
Patent #:
Issue Dt:
03/19/2019
Application #:
15796596
Filing Dt:
10/27/2017
Publication #:
Pub Dt:
05/03/2018
Title:
WORST CASE EYE FOR MULTI-LEVEL PULSE AMPLITUDE MODULATED LINKS
77
Patent #:
Issue Dt:
12/03/2019
Application #:
15873833
Filing Dt:
01/17/2018
Publication #:
Pub Dt:
10/25/2018
Title:
Context-Aware Pattern Matching For Layout Processing
78
Patent #:
Issue Dt:
06/09/2020
Application #:
15873879
Filing Dt:
01/17/2018
Publication #:
Pub Dt:
10/18/2018
Title:
GENERIC PROTOCOL ANALYZER FOR CIRCUIT DESIGN VERIFICATION
79
Patent #:
Issue Dt:
12/17/2019
Application #:
15884369
Filing Dt:
01/30/2018
Publication #:
Pub Dt:
09/06/2018
Title:
Test Application Time Reduction Using Capture-Per-Cycle Test Points
80
Patent #:
Issue Dt:
10/06/2020
Application #:
15884372
Filing Dt:
01/30/2018
Publication #:
Pub Dt:
09/06/2018
Title:
CELL-AWARE DIAGNOSTIC PATTERN GENERATION FOR LOGIC DIAGNOSIS
81
Patent #:
Issue Dt:
09/29/2020
Application #:
15925642
Filing Dt:
03/19/2018
Title:
Efficient And Flexible Network For Streaming Data In Circuits
82
Patent #:
Issue Dt:
05/26/2020
Application #:
15943423
Filing Dt:
04/02/2018
Publication #:
Pub Dt:
10/04/2018
Title:
Concurrent Testbench and Software Driven Verification
83
Patent #:
Issue Dt:
05/19/2020
Application #:
15972812
Filing Dt:
05/07/2018
Title:
Inter-Cell Bridge Defect Diagnosis
84
Patent #:
Issue Dt:
12/31/2019
Application #:
15985679
Filing Dt:
05/21/2018
Publication #:
Pub Dt:
11/22/2018
Title:
Reconfigurable Scan Network Defect Diagnosis
Assignor
1
Exec Dt:
12/30/2020
Newly Merged Entity Data
1
Exec Dt:
12/30/2020
Newly Merged Entity's New Name
1
5800 GRANITE PARKWAY, SUITE 600
PLANO, TEXAS 75024
Correspondence name and address
SIEMENS CORPORATION IP DEPT - MAIL CODE INT-244
3850 QUADRANGLE BOULEVARD
ORLANDO, FL 32817

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