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Reel/Frame:056801/0732   Pages: 4
Recorded: 07/09/2021
Attorney Dkt #:TSMP20205494US00
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
02/13/2024
Application #:
17371416
Filing Dt:
07/09/2021
Publication #:
Pub Dt:
10/06/2022
Title:
Self-Aligned Scheme for Semiconductor Device and Method of Forming the Same
Assignors
1
Exec Dt:
07/06/2021
2
Exec Dt:
07/06/2021
3
Exec Dt:
07/06/2021
4
Exec Dt:
07/06/2021
5
Exec Dt:
07/06/2021
6
Exec Dt:
07/06/2021
Assignee
1
8, LI-HSIN RD. 6
HSINCHU SCIENCE PARK
HSINCHU, TAIWAN 300-78
Correspondence name and address
SLATER MATSIL, LLP/TSMC
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252

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