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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 10 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
5978906
Issue Dt:
11/02/1999
Application #:
08957596
Filing Dt:
10/24/1997
Title:
BRANCH SELECTORS ASSOCIATED WITH BYTE RANGES WITHIN AN INSTRUCTION CACHE FOR RAPIDLY IDENTIFYING BRANCH PREDICTIONS
2
Patent #:
6014739
Issue Dt:
01/11/2000
Application #:
08957900
Filing Dt:
10/27/1997
Title:
INCREASING GENERAL REGISTERS IN X86 PROCESSORS
3
Patent #:
6043138
Issue Dt:
03/28/2000
Application #:
08959105
Filing Dt:
10/23/1997
Title:
MULTI-STEP POLYSILICON DEPOSITION PROCESS FOR BORON PENETRATION INHIBITION
4
Patent #:
5827776
Issue Dt:
10/27/1998
Application #:
08959106
Filing Dt:
10/23/1997
Title:
METHOD OF MAKING AN INTEGRATED CIRCUIT WHICH USES AN ETCH STOP FOR PRODUCING STAGGERED INTERCONNECT LINES
5
Patent #:
6194283
Issue Dt:
02/27/2001
Application #:
08959587
Filing Dt:
10/29/1997
Title:
HIGH DENSITY TRENCH FILL DUE TO NEW SPACER FILL METHOD INCLUDING ISOTROPICALLY ETCHING SILICON NITRIDE SPACERS
6
Patent #:
5913047
Issue Dt:
06/15/1999
Application #:
08960189
Filing Dt:
10/29/1997
Title:
PAIRING FLOATING POINT EXCHANGE INSTRUCTION WITH ANOTHER FLOATING POINT INSTRUCTION TO REDUCE DISPATCH LATENCY
7
Patent #:
5916010
Issue Dt:
06/29/1999
Application #:
08960952
Filing Dt:
10/30/1997
Title:
CMP PAD MAINTENANCE APPARATUS AND METHOD
8
Patent #:
6094443
Issue Dt:
07/25/2000
Application #:
08961023
Filing Dt:
10/30/1997
Title:
APPARATUS AND METHOD FOR DETECTING A PRESCRIBED PATTERN IN A DATA STREAM BY SELECTIVELY SKIPPING GROUPS OF NONRELEVANT DATA BYTES
9
Patent #:
6043166
Issue Dt:
03/28/2000
Application #:
08961131
Filing Dt:
10/30/1997
Title:
SILICON-ON-INSULATOR SUBSTRATES USING LOW DOSE IMPLANTATION
10
Patent #:
5938728
Issue Dt:
08/17/1999
Application #:
08961190
Filing Dt:
10/30/1997
Title:
APPARATUS AND METHOD FOR SELECTIVELY CONTROLLING CLOCKING AND RESETTING OF A NETWORK INTERFACE
11
Patent #:
5938771
Issue Dt:
08/17/1999
Application #:
08961432
Filing Dt:
10/30/1997
Title:
APPARATUS AND METHOD IN A NETWORK INTERFACE FOR ENABLING POWER UP OF A HOST COMPUTER USING MAGIC PACKET AND ON-NOW POWER UP MANAGEMENT SCHEMES
12
Patent #:
5866473
Issue Dt:
02/02/1999
Application #:
08961853
Filing Dt:
10/31/1997
Title:
METHOD OF MANUFACTURING A POLYSILICON GATE HAVING A DIMENSION BELOW THE PHOTOLITHOGRAPHY LIMITATION
13
Patent #:
5953627
Issue Dt:
09/14/1999
Application #:
08965541
Filing Dt:
11/06/1997
Title:
PROCESS FOR MANUFACTURE OF INTEGRATED CIRCUIT DEVICE
14
Patent #:
5966312
Issue Dt:
10/12/1999
Application #:
08966138
Filing Dt:
11/07/1997
Title:
METHOD FOR MONITORING AND ANALYZING MANUFACTURING PROCESSES USING STATISTICAL SIMULATION WITH SINGLE STEP FEEDBACK
15
Patent #:
5937315
Issue Dt:
08/10/1999
Application #:
08966288
Filing Dt:
11/07/1997
Title:
SELF-ALIGNED SILICIDE GATE TECHNOLOGY FOR ADVANCED SUBMICRON MOS DEVICES
16
Patent #:
5937325
Issue Dt:
08/10/1999
Application #:
08966306
Filing Dt:
11/07/1997
Title:
FORMATION OF LOW RESISTIVITY TITANIUM SILICIDE GATES IN SEMICONDUCTOR INTEGRATED CIRCUITS
17
Patent #:
5964881
Issue Dt:
10/12/1999
Application #:
08967418
Filing Dt:
11/11/1997
Title:
SYSTEM AND METHOD TO CONTROL MICROPROCESSOR STARTUP TO REDUCE POWER SUPPLY BULK CAPACITANCE NEEDS
18
Patent #:
6184108
Issue Dt:
02/06/2001
Application #:
08967889
Filing Dt:
11/12/1997
Title:
METHOD OF MAKING TRENCH ISOLATION STRUCTURES WITH OXIDIZED SILICON REGIONS
19
Patent #:
5857089
Issue Dt:
01/05/1999
Application #:
08967950
Filing Dt:
11/12/1997
Title:
FLOATING POINT STACK AND EXCHANGE INSTRUCTION
20
Patent #:
6103096
Issue Dt:
08/15/2000
Application #:
08968190
Filing Dt:
11/12/1997
Title:
APPARATUS AND METHOD FOR THE ELECTROCHEMICAL ETCHING OF A WAFER
21
Patent #:
5998292
Issue Dt:
12/07/1999
Application #:
08968402
Filing Dt:
11/12/1997
Title:
METHOD FOR MAKING THREE DIMENSIONAL CIRCUIT INTEGRATION
22
Patent #:
6222136
Issue Dt:
04/24/2001
Application #:
08968988
Filing Dt:
11/12/1997
Title:
PRINTED CIRCUIT BOARD WITH CONTINUOUS CONNECTIVE BUMPS
23
Patent #:
5877861
Issue Dt:
03/02/1999
Application #:
08971065
Filing Dt:
11/14/1997
Title:
NETHOD FOR OVERLAY CONTROL SYSTEM
24
Patent #:
5852616
Issue Dt:
12/22/1998
Application #:
08971357
Filing Dt:
11/17/1997
Title:
ON-CHIP OPERATING CONDITION RECORDER
25
Patent #:
6084933
Issue Dt:
07/04/2000
Application #:
08971574
Filing Dt:
11/17/1997
Title:
CHIP OPERATING CONDITIONS COMPENSATED CLOCK GENERATION
26
Patent #:
5835719
Issue Dt:
11/10/1998
Application #:
08972093
Filing Dt:
11/17/1997
Title:
APPARATUS AND METHOD FOR REMOTE WAKE-UP IN SYSTEM HAVING INTERLINKED NETWORKS
27
Patent #:
6092220
Issue Dt:
07/18/2000
Application #:
08972111
Filing Dt:
11/17/1997
Title:
METHOD AND APPARATUS FOR ORDERED RELIABLE MULTICAST WITH ASYMMETRIC SAFETY IN A MULTIPROCESSING SYSTEM
28
Patent #:
6093335
Issue Dt:
07/25/2000
Application #:
08974210
Filing Dt:
11/20/1997
Title:
METHOD OF SURFACE FINISHES FOR ELIMINATING SURFACE IRREGULARITIES AND DEFECTS
29
Patent #:
6110649
Issue Dt:
08/29/2000
Application #:
08974580
Filing Dt:
11/19/1997
Title:
PROCESS FOR MANUFACTURE OF INTEGRATED CIRCUIT DEVICE
30
Patent #:
6076160
Issue Dt:
06/13/2000
Application #:
08974970
Filing Dt:
11/20/1997
Title:
HARDWARE-BASED SYSTEM FOR ENABLING DATA TRANSFERS BETWEEN A CPU AND CHIP SET LOGIC OF A COMPUTER SYSTEM ON BOTH EDGES OF BUS CLOCK SIGNAL
31
Patent #:
6154818
Issue Dt:
11/28/2000
Application #:
08975027
Filing Dt:
11/20/1997
Title:
SYSTEM AND METHOD OF CONTROLLING ACCESS TO PRIVILEGE PARTITIONED ADDRESS SPACE FOR A MODEL SPECIFIC REGISTER FILE
32
Patent #:
6017463
Issue Dt:
01/25/2000
Application #:
08976026
Filing Dt:
11/21/1997
Title:
POINT OF USE MIXING FOR LI/PLUG TUNGSTEN POLISHING SLURRY TO IMPROVE EXISTING SLURRY
33
Patent #:
5915195
Issue Dt:
06/22/1999
Application #:
08977795
Filing Dt:
11/25/1997
Title:
ION IMPLANTATION PROCESS TO IMPROVE THE GATE OXIDE QUALITY AT THE EDGE OF A SHALLOW TRENCH ISOLATION STRUCTURE
34
Patent #:
6054374
Issue Dt:
04/25/2000
Application #:
08979599
Filing Dt:
11/26/1997
Title:
METHOD OF SCALING DIELECTRIC THICKNESS IN A SEMICONDUCTOR PROCESS WITH ION IMPLANTATION
35
Patent #:
5825066
Issue Dt:
10/20/1998
Application #:
08979876
Filing Dt:
11/26/1997
Title:
CONTROL OF JUNCTION DEPTH AND CHANNEL LENGHT USING GENERATED INTERSTITIAL GRADIENTS TO OPPOSE DOPANT DIFFUSION
36
Patent #:
5978441
Issue Dt:
11/02/1999
Application #:
08980554
Filing Dt:
12/01/1997
Title:
EXTREME ULTRAVIOLET LITHOGRAPHY MASK BLANK AND MANUFACTURING METHOD THEREFOR
37
Patent #:
5908308
Issue Dt:
06/01/1999
Application #:
08980883
Filing Dt:
11/26/1997
Title:
USE OF BOROPHOSPHOROUS TETRAETHYL ORTHOSICLICATE (BPTEOUS) TO IMPROVE ISOLATION IN A TRANSISTOR ARRAY
38
Patent #:
6066578
Issue Dt:
05/23/2000
Application #:
08980888
Filing Dt:
12/01/1997
Title:
METHOD AND SYSTEM FOR PROVIDING INORGANIC VAPOR SURFACE TREATMENT FOR PHOTORESIST ADHESION PROMOTION
39
Patent #:
5930632
Issue Dt:
07/27/1999
Application #:
08980916
Filing Dt:
12/01/1997
Title:
PROCESS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING COBALT NIOBATE GATE ELECTRODE STRUCTURE
40
Patent #:
6337215
Issue Dt:
01/08/2002
Application #:
08982019
Filing Dt:
12/01/1997
Title:
MAGNETIC PARTICLES HAVING TWO ANTIPARALLEL FERROMAGNETIC LAYERS AND ATTACHED AFFINITY RECOGNITION MOLECULES
41
Patent #:
5940698
Issue Dt:
08/17/1999
Application #:
08982198
Filing Dt:
12/01/1997
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE GATE ELECTRODE STRUCTURE
42
Patent #:
5923993
Issue Dt:
07/13/1999
Application #:
08982230
Filing Dt:
12/17/1997
Title:
METHOD FOR FABRICATING DISHING FREE SHALLOW ISOLATION TRENCHES
43
Patent #:
6151662
Issue Dt:
11/21/2000
Application #:
08982720
Filing Dt:
12/02/1997
Title:
DATA TRANSACTION TYPING FOR IMPROVED CACHING AND PREFETCHING CHARACTERISTICS
44
Patent #:
6130835
Issue Dt:
10/10/2000
Application #:
08982893
Filing Dt:
12/02/1997
Title:
VOLTAGE BIASING FOR MAGNETIC RAM WITH MAGNETIC TUNNEL MEMORY CELLS
45
Patent #:
5991193
Issue Dt:
11/23/1999
Application #:
08982995
Filing Dt:
12/02/1997
Title:
VOLTAGE BIASING FOR MAGNETIC RAM WITH MAGNETIC TUNNEL MEMORY CELLS
46
Patent #:
6001415
Issue Dt:
12/14/1999
Application #:
08984229
Filing Dt:
12/03/1997
Title:
VIA WITH BARRIER LAYER FOR IMPEDING DIFFUSION OF CONDUCTIVE MATERIAL FROM VIA INTO INSULATOR
47
Patent #:
6077780
Issue Dt:
06/20/2000
Application #:
08984352
Filing Dt:
12/03/1997
Title:
METHOD FOR FILLING HIGH ASPECT RATIO OPENINGS OF AN INTEGRATED CIRCUIT TO MINIMIZE ELECTROMIGRATION FAILURE
48
Patent #:
6124546
Issue Dt:
09/26/2000
Application #:
08984547
Filing Dt:
12/03/1997
Title:
INTEGRATED CIRCUIT CHIP PACKAGE AND METHOD OF MAKING THE SAME
49
Patent #:
6154711
Issue Dt:
11/28/2000
Application #:
08985467
Filing Dt:
12/05/1997
Title:
DISPOSITION TOOL FOR FACTORY PROCESS CONTROL
50
Patent #:
6041270
Issue Dt:
03/21/2000
Application #:
08985470
Filing Dt:
12/05/1997
Title:
AUTOMATIC RECIPE ADJUST AND DOWNLOAD BASED ON PROCESS CONTROL WINDOW
51
Patent #:
5866437
Issue Dt:
02/02/1999
Application #:
08985566
Filing Dt:
12/05/1997
Title:
DYNAMIC PROCESS WINDOW CONTROL USING SIMULATED WET DATA FROM CURRENT AND PREVIOUS LAYER DATA
52
Patent #:
6188306
Issue Dt:
02/13/2001
Application #:
08985915
Filing Dt:
12/05/1997
Title:
ON-CHIP TRANSFORMERS
53
Patent #:
6008094
Issue Dt:
12/28/1999
Application #:
08986086
Filing Dt:
12/05/1997
Title:
OPTIMIZATION OF LOGIC GATES WITH CRISS-CROSS IMPLANTS TO FORM ASYMMETIC CHANNEL REGIONS
54
Patent #:
6046507
Issue Dt:
04/04/2000
Application #:
08986087
Filing Dt:
12/05/1997
Title:
ELECTROPHORETIC COATING METHODOLOGY TO IMPROVE INTERNAL PACKAGE DELAMINATION AND WIRE BOND RELIABILITY
55
Patent #:
5930659
Issue Dt:
07/27/1999
Application #:
08986098
Filing Dt:
12/05/1997
Title:
FORMING MINIMAL SIZE SPACES IN INTEGRATED CIRCUIT CONDUCTIVE LINES
56
Patent #:
6063665
Issue Dt:
05/16/2000
Application #:
08986463
Filing Dt:
12/08/1997
Title:
METHOD FOR SILICON SURFACE CONTROL FOR SHALLOW JUNCTION FORMATION
57
Patent #:
6271542
Issue Dt:
08/07/2001
Application #:
08987066
Filing Dt:
12/08/1997
Title:
MERGED LOGIC AND MEMORY COMBINING THIN FILM AND BULK SI TRANSISTORS
58
Patent #:
5869379
Issue Dt:
02/09/1999
Application #:
08987116
Filing Dt:
12/08/1997
Title:
METHOD OF FORMING AIR GAP SPACER FOR HIGH PERFORMANCE MOSFETS
59
Patent #:
5946579
Issue Dt:
08/31/1999
Application #:
08987277
Filing Dt:
12/09/1997
Title:
STACKED MASK INTEGRATION TECHNIQUE FOR ADVANCED CMOS TRANSISTOR FORMATION
60
Patent #:
6323561
Issue Dt:
11/27/2001
Application #:
08987455
Filing Dt:
12/09/1997
Title:
SPACER FORMATION FOR PRECISE SALICIDE FORMATION
61
Patent #:
6207353
Issue Dt:
03/27/2001
Application #:
08987808
Filing Dt:
12/10/1997
Title:
RESIST FORMULATION WHICH MINIMIZES BLISTERING DURING ETCHING
62
Patent #:
5930497
Issue Dt:
07/27/1999
Application #:
08988438
Filing Dt:
12/11/1997
Title:
METHOD AND MEANS FOR GENERATION OF REALISTIC ACCESS PATTERNS IN STORAGE SUBSYSTEM BENCHMARKING AND OTHER TESTS
63
Patent #:
6093331
Issue Dt:
07/25/2000
Application #:
08988681
Filing Dt:
12/11/1997
Title:
BACKSIDE SILICON REMOVAL FOR FACE DOWN CHIP ANALYSIS
64
Patent #:
6035364
Issue Dt:
03/07/2000
Application #:
08989330
Filing Dt:
12/11/1997
Title:
INDEPENDENT USE OF BITS ON AN ON-CHIP BUS
65
Patent #:
6278166
Issue Dt:
08/21/2001
Application #:
08989741
Filing Dt:
12/12/1997
Title:
USE OF NITRIC OXIDE SURFACE ANNEAL TO PROVIDE REACTION BARRIER FOR DEPOSITION OF TANTALUM PENTOXIDE
66
Patent #:
6061775
Issue Dt:
05/09/2000
Application #:
08989793
Filing Dt:
12/12/1997
Title:
APPARATUS AND METHOD FOR PREDICTING A FIRST MICROCODE INSTRUCTION OF A CACHE LINE AND USING PREDECODE INSTRUCTION DATA TO IDENTIFY INSTRUCTION BOUNDARIES AND TYPES
67
Patent #:
5890006
Issue Dt:
03/30/1999
Application #:
08989794
Filing Dt:
12/12/1997
Title:
APPARATUS FOR EXTRACTING INSTRUCTION SPECIFIC BYTES FROM AN INSTRUCTION
68
Patent #:
6523129
Issue Dt:
02/18/2003
Application #:
08991107
Filing Dt:
12/16/1997
Title:
METHOD OF PREVENTING COMPUTER MALFUNCTION DURING A CHANGE OF POWER CONSUMPTION STATES VIA DYNAMIC ADJUSTMENT OF CORE VOLTAGE
69
Patent #:
6163052
Issue Dt:
12/19/2000
Application #:
08991464
Filing Dt:
12/16/1997
Title:
TRENCH-GATED VERTICAL COMBINATION JFET AND MOSFET DEVICES
70
Patent #:
6090694
Issue Dt:
07/18/2000
Application #:
08991742
Filing Dt:
12/16/1997
Title:
LOCAL INTERCONNECT PATTERNING AND CONTACT FORMATION
71
Patent #:
6020222
Issue Dt:
02/01/2000
Application #:
08991808
Filing Dt:
12/16/1997
Title:
SILICON OXIDE INSULATOR (SOI) SEMICONDUCTOR HAVING SELECTIVELY LINKED BODY
72
Patent #:
6016533
Issue Dt:
01/18/2000
Application #:
08991846
Filing Dt:
12/16/1997
Title:
WAY PREDICTION LOGIC FOR CACHE ARRAY
73
Patent #:
6314530
Issue Dt:
11/06/2001
Application #:
08991970
Filing Dt:
12/17/1997
Title:
OPERATING SYSTEM INCORPORATING DEBUG FEATURES TO ACCESS ON-CHIP TRACE MEMORY
74
Patent #:
6044430
Issue Dt:
03/28/2000
Application #:
08992283
Filing Dt:
12/17/1997
Title:
REAL TIME INTERRUPT HANDLING FOR SUPERSCALAR PROCESSORS
75
Patent #:
6175914
Issue Dt:
01/16/2001
Application #:
08992314
Filing Dt:
12/17/1997
Title:
COMBINED PARALLEL DEBUG AND TRACE PORT
76
Patent #:
6009270
Issue Dt:
12/28/1999
Application #:
08992315
Filing Dt:
12/17/1997
Title:
TRACE SYNCHRONIZATION IN A PROCESSOR
77
Patent #:
6051870
Issue Dt:
04/18/2000
Application #:
08992333
Filing Dt:
12/17/1997
Title:
PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING IMPROVED PHOSPHOROUS-DOPED SILICON DIOXIDE DIELECTRIC FILM
78
Patent #:
6094729
Issue Dt:
07/25/2000
Application #:
08992361
Filing Dt:
12/17/1997
Title:
DEBUG INTERFACE INCLUDING A COMPACT TRACE RECORD STORAGE
79
Patent #:
6157623
Issue Dt:
12/05/2000
Application #:
08992424
Filing Dt:
12/18/1997
Title:
APPARATUS AND METHOD FOR SELECTIVELY OUTPUTTING DATA USING A MAC LAYER INTERFACE OR A PCI BUS INTERFACE
80
Patent #:
5942801
Issue Dt:
08/24/1999
Application #:
08992430
Filing Dt:
12/18/1997
Title:
BORDERLESS VIAS WITH HSQ GAP FILLED METAL PATTERNS HAVING HIGH ETCHING RESISTANCE
81
Patent #:
5970362
Issue Dt:
10/19/1999
Application #:
08992488
Filing Dt:
12/18/1997
Title:
SIMPLIFIED SHALLOW TRENCH ISOLATION FORMATION WITH NO POLISH STOP
82
Patent #:
6124183
Issue Dt:
09/26/2000
Application #:
08992490
Filing Dt:
12/18/1997
Title:
SHALLOW TRENCH ISOLATION FORMATION WITH SIMPLIFIED REVERSE PLANARIZATION MASK
83
Patent #:
6058112
Issue Dt:
05/02/2000
Application #:
08992492
Filing Dt:
12/18/1997
Title:
INTERNAL RULES CHECKER DIAGNOSTIC MODE
84
Patent #:
6133142
Issue Dt:
10/17/2000
Application #:
08992628
Filing Dt:
12/18/1997
Title:
LOWER METAL FEATURE PROFILE WITH OVERHANGING ARC LAYER TO IMPROVE ROBUSTNESS OF BORDERLESS VIAS
85
Patent #:
5949126
Issue Dt:
09/07/1999
Application #:
08992735
Filing Dt:
12/17/1997
Title:
TRENCH ISOLATION STRUCTURE EMPLOYING PROTECTIVE SIDEWALL SPACERS UPON EXPOSED SURFACES OF THE ISOLATION TRENCH
86
Patent #:
6292483
Issue Dt:
09/18/2001
Application #:
08992795
Filing Dt:
12/18/1997
Title:
APPARATUS AND METHOD FOR GENERATING AN INDEX KEY FOR A NETWORK SWITCH ROUTING TABLE USING A PROGRAMMABLE HASH FUNCTION
87
Patent #:
5999441
Issue Dt:
12/07/1999
Application #:
08992796
Filing Dt:
12/18/1997
Title:
RANDOM ACCESS MEMORY HAVING BIT SELECTABLE MASK FOR MEMORY WRITES
88
Patent #:
6084877
Issue Dt:
07/04/2000
Application #:
08992797
Filing Dt:
12/18/1997
Title:
NETWORK SWITCH PORT CONFIGURED FOR GENERATING AN INDEX KEY FOR A NETWORK SWITCH ROUTING TABLE USING A PROGRAMMABLE HASH FUNCTION
89
Patent #:
6118761
Issue Dt:
09/12/2000
Application #:
08992841
Filing Dt:
12/18/1997
Title:
APPARATUS AND METHOD FOR GENERATING RATE CONTROL FRAMES IN A WORKGROUP SWITCH BASED ON TRAFFIC CONTRIBUTION FROM A NETWORK SWITCH PORT
90
Patent #:
6192028
Issue Dt:
02/20/2001
Application #:
08992848
Filing Dt:
12/18/1997
Title:
METHOD AND APPARATUS PROVIDING PROGRAMMABLE THRESHOLDS FOR HALF-DUPLEX FLOW CONTROL IN A NETWORK SWITCH
91
Patent #:
6094436
Issue Dt:
07/25/2000
Application #:
08992921
Filing Dt:
12/18/1997
Title:
INTEGRATED MULTIPORT SWITCH HAVING SHARED MEDIA ACCESS CONTROL CIRCUITRY
92
Patent #:
6169742
Issue Dt:
01/02/2001
Application #:
08992923
Filing Dt:
12/18/1997
Title:
MULTIPORT DATA NETWORK SWITCH HAVING DIRECT MEDIA ACCESS CONTROL LINK TO EXTERNAL MANAGEMENT
93
Patent #:
6175902
Issue Dt:
01/16/2001
Application #:
08992925
Filing Dt:
12/18/1997
Title:
METHOD AND APPARATUS FOR MAINTAINING A TIME ORDER BY PHYSICAL ORDERING IN A MEMORY
94
Patent #:
6011799
Issue Dt:
01/04/2000
Application #:
08992926
Filing Dt:
12/18/1997
Title:
METHOD AND APPARATUS FOR MANAGING EXTERNAL PHYSICAL LAYER DEVICES
95
Patent #:
6233244
Issue Dt:
05/15/2001
Application #:
08992927
Filing Dt:
12/18/1997
Title:
METHOD AND APPARATUS FOR RECLAIMING BUFFERS
96
Patent #:
6010965
Issue Dt:
01/04/2000
Application #:
08992959
Filing Dt:
12/18/1997
Title:
METHOD OF FORMING HIGH INTEGRITY VIAS
97
Patent #:
6078627
Issue Dt:
06/20/2000
Application #:
08992963
Filing Dt:
12/18/1997
Title:
CIRCUIT AND METHOD FOR MULTILEVEL SIGNAL DECODING, DESCRAMBLING, AND ERROR DETECTION
98
Patent #:
6083850
Issue Dt:
07/04/2000
Application #:
08992965
Filing Dt:
12/18/1997
Title:
HSQ DIELECTRIC INTERLAYER
99
Patent #:
5918133
Issue Dt:
06/29/1999
Application #:
08993029
Filing Dt:
12/18/1997
Title:
SEMICONDUCTOR DEVICE HAVING DUAL GATE DIELECTRIC THICKNESS ALONG THE CHANNEL AND FABRICATION THEREOF
100
Patent #:
6393548
Issue Dt:
05/21/2002
Application #:
08993046
Filing Dt:
12/18/1997
Title:
VARIABLE 16 OR 32 BIT PCI INTERFACE WHICH SUPPORTS STEERING AND SWAPPING OF DATA
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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