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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 100 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
8446667
Issue Dt:
05/21/2013
Application #:
13106930
Filing Dt:
05/13/2011
Publication #:
US20110211059
Pub Dt:
09/01/2011
Title:
CONTACT MICROSCOPE USING POINT SOURCE ILLUMINATION
2
Patent #:
8243507
Issue Dt:
08/14/2012
Application #:
13107087
Filing Dt:
05/13/2011
Publication #:
US20110217836
Pub Dt:
09/08/2011
Title:
PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL
3
Patent #:
NONE
Issue Dt:
Application #:
13107250
Filing Dt:
05/13/2011
Publication #:
US20120286397
Pub Dt:
11/15/2012
Title:
Die Seal for Integrated Circuit Device
4
Patent #:
8849643
Issue Dt:
09/30/2014
Application #:
13107355
Filing Dt:
05/13/2011
Publication #:
US20120290281
Pub Dt:
11/15/2012
Title:
TABLE-LOOKUP-BASED MODELS FOR YIELD ANALYSIS ACCELERATION
5
Patent #:
8489380
Issue Dt:
07/16/2013
Application #:
13108008
Filing Dt:
05/16/2011
Publication #:
US20110213605
Pub Dt:
09/01/2011
Title:
SATISFIABILITY (SAT) BASED BOUNDED MODEL CHECKERS
6
Patent #:
9117929
Issue Dt:
08/25/2015
Application #:
13108087
Filing Dt:
05/16/2011
Publication #:
US20110223733
Pub Dt:
09/15/2011
Title:
Method for Forming a Strained Transistor by Stress Memorization Based on a Stressed Implantation Mask
7
Patent #:
9012283
Issue Dt:
04/21/2015
Application #:
13108213
Filing Dt:
05/16/2011
Publication #:
US20120292664
Pub Dt:
11/22/2012
Title:
INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORS (FETS) AND METHOD OF MANUFACTURE
8
Patent #:
8507989
Issue Dt:
08/13/2013
Application #:
13108282
Filing Dt:
05/16/2011
Publication #:
US20120292700
Pub Dt:
11/22/2012
Title:
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) FET WITH A BACK GATE AND REDUCED PARASITIC CAPACITANCE
9
Patent #:
8598663
Issue Dt:
12/03/2013
Application #:
13108290
Filing Dt:
05/16/2011
Publication #:
US20120292705
Pub Dt:
11/22/2012
Title:
SEMICONDUCTOR STRUCTURE HAVING NFET AND PFET FORMED IN SOI SUBSTRATE WITH UNDERLAPPED EXTENSIONS
10
Patent #:
8618583
Issue Dt:
12/31/2013
Application #:
13108305
Filing Dt:
05/16/2011
Publication #:
US20120292669
Pub Dt:
11/22/2012
Title:
JUNCTION GATE FIELD EFFECT TRANSISTOR STRUCRURE HAVING N-CHANNEL
11
Patent #:
8987104
Issue Dt:
03/24/2015
Application #:
13108363
Filing Dt:
05/16/2011
Publication #:
US20120292671
Pub Dt:
11/22/2012
Title:
METHOD OF FORMING SPACERS THAT PROVIDE ENHANCED PROTECTION FOR GATE ELECTRODE STRUCTURES
12
Patent #:
NONE
Issue Dt:
Application #:
13108574
Filing Dt:
05/16/2011
Publication #:
US20120292304
Pub Dt:
11/22/2012
Title:
PORTABLE ELECTRONIC DEVICE CASE WITH ACTIVE THERMAL PROTECTION
13
Patent #:
8639992
Issue Dt:
01/28/2014
Application #:
13108721
Filing Dt:
05/16/2011
Publication #:
US20120297259
Pub Dt:
11/22/2012
Title:
SOFT ERROR RATE DETECTOR
14
Patent #:
8425236
Issue Dt:
04/23/2013
Application #:
13108955
Filing Dt:
05/16/2011
Publication #:
US20120295453
Pub Dt:
11/22/2012
Title:
TALL MEZZANINE CONNECTOR
15
Patent #:
NONE
Issue Dt:
Application #:
13109134
Filing Dt:
05/17/2011
Publication #:
US20120292637
Pub Dt:
11/22/2012
Title:
Dual Cavity Etch for Embedded Stressor Regions
16
Patent #:
8536019
Issue Dt:
09/17/2013
Application #:
13109869
Filing Dt:
05/17/2011
Publication #:
US20120292734
Pub Dt:
11/22/2012
Title:
SEMICONDUCTOR DEVICES HAVING ENCAPSULATED ISOLATION REGIONS AND RELATED FABRICATION METHODS
17
Patent #:
8627147
Issue Dt:
01/07/2014
Application #:
13109948
Filing Dt:
05/17/2011
Publication #:
US20120297251
Pub Dt:
11/22/2012
Title:
METHOD AND COMPUTER PROGRAM PRODUCT FOR SYSTEM TUNING BASED ON PERFORMANCE MEASUREMENTS AND HISTORICAL PROBLEM DATA AND SYSTEM THEREOF
18
Patent #:
8614900
Issue Dt:
12/24/2013
Application #:
13110175
Filing Dt:
05/18/2011
Publication #:
US20110292621
Pub Dt:
12/01/2011
Title:
GROUNDED LID FOR MICRO-ELECTRONIC ASSEMBLIES
19
Patent #:
9298501
Issue Dt:
03/29/2016
Application #:
13111451
Filing Dt:
05/19/2011
Publication #:
US20120297234
Pub Dt:
11/22/2012
Title:
CONCURRENT MANAGEMENT CONSOLE OPERATIONS
20
Patent #:
8455307
Issue Dt:
06/04/2013
Application #:
13111741
Filing Dt:
05/19/2011
Publication #:
US20120292672
Pub Dt:
11/22/2012
Title:
FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
21
Patent #:
8803141
Issue Dt:
08/12/2014
Application #:
13112356
Filing Dt:
05/20/2011
Publication #:
US20110240932
Pub Dt:
10/06/2011
Title:
HYDRAZINE-FREE SOLUTION DEPOSITION OF CHALCOGENIDE FILMS
22
Patent #:
8440494
Issue Dt:
05/14/2013
Application #:
13112465
Filing Dt:
05/20/2011
Publication #:
US20120295390
Pub Dt:
11/22/2012
Title:
SINGLE-CRYSTALLINE SILICON ALKALINE TEXTURING WITH GLYCEROL OR ETHYLENE GLYCOL ADDITIVES
23
Patent #:
8168045
Issue Dt:
05/01/2012
Application #:
13112477
Filing Dt:
05/20/2011
Publication #:
US20110220020
Pub Dt:
09/15/2011
Title:
APPARATUS FOR AN ENHANCED MAGNETIC PLATING METHOD
24
Patent #:
NONE
Issue Dt:
Application #:
13112687
Filing Dt:
05/20/2011
Publication #:
US20120271601
Pub Dt:
10/25/2012
Title:
SYSTEMS AND METHODS FOR FORECASTING PROCESS EVENT DATES
25
Patent #:
8306755
Issue Dt:
11/06/2012
Application #:
13113256
Filing Dt:
05/23/2011
Publication #:
US20110225148
Pub Dt:
09/15/2011
Title:
FIELD-BASED SIMILARITY SEARCH SYSTEM AND METHOD
26
Patent #:
8386977
Issue Dt:
02/26/2013
Application #:
13113421
Filing Dt:
05/23/2011
Publication #:
US20120304138
Pub Dt:
11/29/2012
Title:
CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY
27
Patent #:
8664056
Issue Dt:
03/04/2014
Application #:
13113698
Filing Dt:
05/23/2011
Publication #:
US20110294269
Pub Dt:
12/01/2011
Title:
TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN DIAMOND-SHAPED CAVITIES BASED ON A PRE-AMORPHIZATION
28
Patent #:
8597994
Issue Dt:
12/03/2013
Application #:
13113901
Filing Dt:
05/23/2011
Publication #:
US20120299106
Pub Dt:
11/29/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
29
Patent #:
8486768
Issue Dt:
07/16/2013
Application #:
13114116
Filing Dt:
05/24/2011
Publication #:
US20120001295
Pub Dt:
01/05/2012
Title:
SEMICONDUCTOR DEVICE COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND PRECISION EFUSES FORMED IN THE ACTIVE SEMICONDUCTOR MATERIAL
30
Patent #:
8552500
Issue Dt:
10/08/2013
Application #:
13114283
Filing Dt:
05/24/2011
Publication #:
US20120299080
Pub Dt:
11/29/2012
Title:
STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY
31
Patent #:
8546243
Issue Dt:
10/01/2013
Application #:
13114543
Filing Dt:
05/24/2011
Publication #:
US20120299152
Pub Dt:
11/29/2012
Title:
DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE
32
Patent #:
8609555
Issue Dt:
12/17/2013
Application #:
13115192
Filing Dt:
05/25/2011
Publication #:
US20120025392
Pub Dt:
02/02/2012
Title:
INCREASED STABILITY OF A COMPLEX MATERIAL STACK IN A SEMICONDUCTOR DEVICE BY PROVIDING FLUORINE ENRICHED INTERFACES
33
Patent #:
8722479
Issue Dt:
05/13/2014
Application #:
13115270
Filing Dt:
05/25/2011
Publication #:
US20120302037
Pub Dt:
11/29/2012
Title:
METHOD OF PROTECTING STI STRUCTURES FROM EROSION DURING PROCESSING OPERATIONS
34
Patent #:
8592270
Issue Dt:
11/26/2013
Application #:
13115314
Filing Dt:
05/25/2011
Publication #:
US20120302019
Pub Dt:
11/29/2012
Title:
NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES
35
Patent #:
8828816
Issue Dt:
09/09/2014
Application #:
13115428
Filing Dt:
05/25/2011
Publication #:
US20120302023
Pub Dt:
11/29/2012
Title:
PMOS THRESHOLD VOLTAGE CONTROL BY GERMANIUM IMPLANTATION
36
Patent #:
NONE
Issue Dt:
Application #:
13115583
Filing Dt:
05/25/2011
Publication #:
US20120301688
Pub Dt:
11/29/2012
Title:
FLEXIBLE ELECTRONICS WIRING
37
Patent #:
8514386
Issue Dt:
08/20/2013
Application #:
13115823
Filing Dt:
05/25/2011
Publication #:
US20120300220
Pub Dt:
11/29/2012
Title:
TECHNIQUE FOR VERIFYING THE MICROSTRUCTURE OF LEAD-FREE INTERCONNECTS IN SEMICONDUCTOR ASSEMBLIES
38
Patent #:
9023696
Issue Dt:
05/05/2015
Application #:
13116672
Filing Dt:
05/26/2011
Publication #:
US20120299160
Pub Dt:
11/29/2012
Title:
METHOD OF FORMING CONTACTS FOR DEVICES WITH MULTIPLE STRESS LINERS
39
Patent #:
8549369
Issue Dt:
10/01/2013
Application #:
13116961
Filing Dt:
05/26/2011
Publication #:
US20120304030
Pub Dt:
11/29/2012
Title:
SEMICONDUCTOR-BASED TEST DEVICE THAT IMPLEMENTS RANDOM LOGIC FUNCTIONS
40
Patent #:
8455314
Issue Dt:
06/04/2013
Application #:
13117249
Filing Dt:
05/27/2011
Publication #:
US20120025266
Pub Dt:
02/02/2012
Title:
TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOYS FORMED IN A LATE STAGE
41
Patent #:
NONE
Issue Dt:
Application #:
13118826
Filing Dt:
05/31/2011
Publication #:
US20120309182
Pub Dt:
12/06/2012
Title:
Method of Forming Sidewall Spacers Having Different Widths Using a Non-Conformal Deposition Process
42
Patent #:
8829585
Issue Dt:
09/09/2014
Application #:
13118881
Filing Dt:
05/31/2011
Publication #:
US20120305998
Pub Dt:
12/06/2012
Title:
HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY
43
Patent #:
8756045
Issue Dt:
06/17/2014
Application #:
13126546
Filing Dt:
06/06/2011
Publication #:
US20110276612
Pub Dt:
11/10/2011
Title:
METHOD, DEVICE, COMPUTER PROGRAM AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A REPRESENTATION OF A SIGNAL
44
Patent #:
8421186
Issue Dt:
04/16/2013
Application #:
13149108
Filing Dt:
05/31/2011
Publication #:
US20120306048
Pub Dt:
12/06/2012
Title:
ELECTRICALLY PROGRAMMABLE METAL FUSE
45
Patent #:
8624323
Issue Dt:
01/07/2014
Application #:
13149797
Filing Dt:
05/31/2011
Publication #:
US20120306018
Pub Dt:
12/06/2012
Title:
BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH
46
Patent #:
8390074
Issue Dt:
03/05/2013
Application #:
13150437
Filing Dt:
06/01/2011
Publication #:
US20110227166
Pub Dt:
09/22/2011
Title:
STRUCTURE AND METHOD FOR LATCHUP IMPROVEMENT USING THROUGH WAFER VIA LATCHUP GUARD RING
47
Patent #:
9087925
Issue Dt:
07/21/2015
Application #:
13150440
Filing Dt:
06/01/2011
Publication #:
US20110227130
Pub Dt:
09/22/2011
Title:
Si and SiGeC On A Buried Oxide Layer On A Substrate
48
Patent #:
8775988
Issue Dt:
07/08/2014
Application #:
13150445
Filing Dt:
06/01/2011
Publication #:
US20120311514
Pub Dt:
12/06/2012
Title:
Decentralized Dynamically Scheduled Parallel Static Timing Analysis
49
Patent #:
8598660
Issue Dt:
12/03/2013
Application #:
13150612
Filing Dt:
06/01/2011
Publication #:
US20120306014
Pub Dt:
12/06/2012
Title:
STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE
50
Patent #:
8897062
Issue Dt:
11/25/2014
Application #:
13150690
Filing Dt:
06/01/2011
Publication #:
US20110228600
Pub Dt:
09/22/2011
Title:
MEMORY PROGRAMMING FOR A PHASE CHANGE MEMORY CELL
51
Patent #:
8354659
Issue Dt:
01/15/2013
Application #:
13150705
Filing Dt:
06/01/2011
Publication #:
US20110227021
Pub Dt:
09/22/2011
Title:
POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL
52
Patent #:
NONE
Issue Dt:
Application #:
13151238
Filing Dt:
06/01/2011
Publication #:
US20120305940
Pub Dt:
12/06/2012
Title:
Defect Free Si:C Epitaxial Growth
53
Patent #:
8381150
Issue Dt:
02/19/2013
Application #:
13151295
Filing Dt:
06/02/2011
Publication #:
US20120311515
Pub Dt:
12/06/2012
Title:
METHOD FOR PERFORMING A PARALLEL STATIC TIMING ANALYSIS USING THREAD-SPECIFIC SUB-GRAPHS
54
Patent #:
8381147
Issue Dt:
02/19/2013
Application #:
13151313
Filing Dt:
06/02/2011
Publication #:
US20120311518
Pub Dt:
12/06/2012
Title:
METHOD, A SYSTEM AND A PROGRAM STORAGE DEVICE FOR MODELING THE RESISTANCE OF A MULTI-CONTACTED DIFFUSION REGION
55
Patent #:
8862417
Issue Dt:
10/14/2014
Application #:
13151337
Filing Dt:
06/02/2011
Publication #:
US20120310574
Pub Dt:
12/06/2012
Title:
SYSTEMS AND METHODS FOR DETERMINING ADJUSTABLE WAFER ACCEPTANCE CRITERIA BASED ON CHIP CHARACTERISTICS
56
Patent #:
8555229
Issue Dt:
10/08/2013
Application #:
13151413
Filing Dt:
06/02/2011
Publication #:
US20120311517
Pub Dt:
12/06/2012
Title:
PARALLEL SOLVING OF LAYOUT OPTIMIZATION
57
Patent #:
8901664
Issue Dt:
12/02/2014
Application #:
13151525
Filing Dt:
06/02/2011
Publication #:
US20110227165
Pub Dt:
09/22/2011
Title:
HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE
58
Patent #:
8564917
Issue Dt:
10/22/2013
Application #:
13151898
Filing Dt:
06/02/2011
Publication #:
US20120307405
Pub Dt:
12/06/2012
Title:
INTEGRATED CIRCUIT HAVING ELECTROSTATIC DISCHARGE PROTECTION
59
Patent #:
8507351
Issue Dt:
08/13/2013
Application #:
13152350
Filing Dt:
06/03/2011
Publication #:
US20110230039
Pub Dt:
09/22/2011
Title:
DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
60
Patent #:
8119466
Issue Dt:
02/21/2012
Application #:
13153051
Filing Dt:
06/03/2011
Publication #:
US20110256675
Pub Dt:
10/20/2011
Title:
SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS
61
Patent #:
NONE
Issue Dt:
Application #:
13153179
Filing Dt:
06/03/2011
Publication #:
US20120306021
Pub Dt:
12/06/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
62
Patent #:
8617915
Issue Dt:
12/31/2013
Application #:
13153381
Filing Dt:
06/03/2011
Publication #:
US20120070936
Pub Dt:
03/22/2012
Title:
ANNEALING THIN FILMS
63
Patent #:
8766410
Issue Dt:
07/01/2014
Application #:
13153806
Filing Dt:
06/06/2011
Publication #:
US20110233634
Pub Dt:
09/29/2011
Title:
EMBEDDED DRAM INTEGRATED CIRCUITS WITH EXTREMELY THIN SILICON-ON-INSULATOR PASS TRANSISTORS
64
Patent #:
8697557
Issue Dt:
04/15/2014
Application #:
13154521
Filing Dt:
06/07/2011
Publication #:
US20120313187
Pub Dt:
12/13/2012
Title:
Method of Removing Gate Cap Materials While Protecting Active Area
65
Patent #:
8941182
Issue Dt:
01/27/2015
Application #:
13154548
Filing Dt:
06/07/2011
Publication #:
US20120313176
Pub Dt:
12/13/2012
Title:
BURIED SUBLEVEL METALLIZATIONS FOR IMPROVED TRANSISTOR DENSITY
66
Patent #:
8664103
Issue Dt:
03/04/2014
Application #:
13154578
Filing Dt:
06/07/2011
Publication #:
US20120315749
Pub Dt:
12/13/2012
Title:
Metal Gate Stack Formation for Replacement Gate Technology
67
Patent #:
8835900
Issue Dt:
09/16/2014
Application #:
13154677
Filing Dt:
06/07/2011
Publication #:
US20120313143
Pub Dt:
12/13/2012
Title:
HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT
68
Patent #:
8722511
Issue Dt:
05/13/2014
Application #:
13154754
Filing Dt:
06/07/2011
Publication #:
US20120025318
Pub Dt:
02/02/2012
Title:
REDUCED TOPOGRAPHY IN ISOLATION REGIONS OF A SEMICONDUCTOR DEVICE BY APPLYING A DEPOSITION/ETCH SEQUENCE PRIOR TO FORMING THE INTERLAYER DIELECTRIC
69
Patent #:
8791009
Issue Dt:
07/29/2014
Application #:
13154905
Filing Dt:
06/07/2011
Publication #:
US20120315753
Pub Dt:
12/13/2012
Title:
METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA
70
Patent #:
NONE
Issue Dt:
Application #:
13154941
Filing Dt:
06/07/2011
Publication #:
US20120025315
Pub Dt:
02/02/2012
Title:
Transistor with Embedded Strain-Inducing Material and Dummy Gate Electrodes Positioned Adjacent to the Active Region
71
Patent #:
8536032
Issue Dt:
09/17/2013
Application #:
13155878
Filing Dt:
06/08/2011
Publication #:
US20120313168
Pub Dt:
12/13/2012
Title:
FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION
72
Patent #:
8283233
Issue Dt:
10/09/2012
Application #:
13156170
Filing Dt:
06/08/2011
Publication #:
US20110233627
Pub Dt:
09/29/2011
Title:
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Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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