|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13194644
|
Filing Dt:
|
07/29/2011
|
Publication #:
|
|
Pub Dt:
|
01/31/2013
| | | | |
Title:
|
MODELING GATE TRANSCONDUCTANCE IN A SUB-CIRCUIT TRANSISTOR MODEL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
13194695
|
Filing Dt:
|
07/29/2011
|
Publication #:
|
|
Pub Dt:
|
01/31/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT SYSTEMS INCLUDING VERTICAL INDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
13195255
|
Filing Dt:
|
08/01/2011
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13195307
|
Filing Dt:
|
08/01/2011
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
MULTI-CHIP RETICLE PHOTOMASKS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13195981
|
Filing Dt:
|
08/02/2011
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
Title:
|
Semiconductor Device Comprising a Contact Structure with Reduced Parasitic Capacitance
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13196318
|
Filing Dt:
|
08/02/2011
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
Strain Enhancement in Transistors Comprising an Embedded Strain-Inducing Semiconductor Material by Alloy Species Condensation
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
13196334
|
Filing Dt:
|
08/02/2011
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
HOLEY ELECTRODE GRIDS FOR PHOTOVOLTAIC CELLS WITH SUBWAVELENGTH AND SUPERWAVELENGTH FEATURE SIZES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13196647
|
Filing Dt:
|
08/02/2011
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
METHODS FOR RELIABILITY TESTING OF SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13197061
|
Filing Dt:
|
08/03/2011
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
ABSTRACTION FOR ARRAYS IN INTEGRATED CIRCUIT MODELS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13197239
|
Filing Dt:
|
08/03/2011
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
Title:
|
DIFFERENTIAL THRESHOLD VOLTAGE ADJUSTMENT IN PMOS TRANSISTORS BY DIFFERENTIAL FORMATION OF A CHANNEL SEMICONDUCTOR MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13197320
|
Filing Dt:
|
08/03/2011
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
EFFICIENT SLACK PROJECTION FOR TRUNCATED DISTRIBUTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13197325
|
Filing Dt:
|
08/03/2011
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13197387
|
Filing Dt:
|
08/03/2011
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
Title:
|
FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY A NITRIDE HARD MASK LAYER AND AN OXIDE MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13197414
|
Filing Dt:
|
08/03/2011
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
SELF-ALIGNED SCHOTTKY DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13197631
|
Filing Dt:
|
08/03/2011
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
SELF-ADJUSTING LATCH-UP RESISTANCE FOR CMOS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2015
|
Application #:
|
13198152
|
Filing Dt:
|
08/04/2011
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
EPITAXIAL EXTENSION CMOS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13198209
|
Filing Dt:
|
08/04/2011
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
METHOD FOR FORMING A TRANSISTOR COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES INCLUDING A POLYCRYSTALLINE SEMICONDUCTOR MATERIAL AND EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOYS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13198292
|
Filing Dt:
|
08/04/2011
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
CONTENT ADDRESSABLE MEMORIES WITH WIRELINE COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
13202228
|
Filing Dt:
|
08/18/2011
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
INSULATION MATERIAL FOR INTEGRATED CIRCUITS AND USE OF SAID INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2013
|
Application #:
|
13204271
|
Filing Dt:
|
08/05/2011
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
TRANSISTOR WITH BOOT SHAPED SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13204283
|
Filing Dt:
|
08/05/2011
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
13204440
|
Filing Dt:
|
08/05/2011
|
Publication #:
|
|
Pub Dt:
|
02/23/2012
| | | | |
Title:
|
DYNAMIC PROVISIONAL DECOMPOSITION OF LITHOGRAPHIC PATTERNS HAVING DIFFERENT INTERACTION RANGES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
13204955
|
Filing Dt:
|
08/08/2011
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
ALIGNMENT DATA BASED PROCESS CONTROL SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13205063
|
Filing Dt:
|
08/08/2011
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
ANNEALING COPPER INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13205186
|
Filing Dt:
|
08/08/2011
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
STRUCTURAL MIGRATION OF INTEGRATED CIRCUIT LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13206586
|
Filing Dt:
|
08/10/2011
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING A WETTING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13207102
|
Filing Dt:
|
08/10/2011
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
13207480
|
Filing Dt:
|
08/11/2011
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CIRCUIT DEVICE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13207609
|
Filing Dt:
|
08/11/2011
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
PICK AND PLACE TAPE RELEASE FOR THIN SEMICONDUCTOR DIES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13208046
|
Filing Dt:
|
08/11/2011
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
IIMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13208697
|
Filing Dt:
|
08/12/2011
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
SHRINKAGE OF CONTACT ELEMENTS AND VIAS IN A SEMICONDUCTOR DEVICE BY INCORPORATING ADDITIONAL TAPERING MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13208835
|
Filing Dt:
|
08/12/2011
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
Semiconductor Device Comprising Contact Elements with Silicided Sidewall Regions
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13208972
|
Filing Dt:
|
08/12/2011
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
Embedding Metal Silicide Contact Regions Reliably Into Highly Doped Drain and Source Regions by a Stop Implantation
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13209057
|
Filing Dt:
|
08/12/2011
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
SELF-ALIGNED FIN TRANSISTOR FORMED ON A BULK SUBSTRATE BY LATE FIN ETCH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13209061
|
Filing Dt:
|
08/12/2011
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13209128
|
Filing Dt:
|
08/12/2011
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
Method of Forming a Semiconductor Device Comprising eFuses of Increased Programming Window
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13209405
|
Filing Dt:
|
08/14/2011
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13209504
|
Filing Dt:
|
08/15/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
EARLY NOISE DETECTION AND NOISE AWARE ROUTING IN CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13209569
|
Filing Dt:
|
08/15/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
LOW TEMPERATURE BEOL COMPATIBLE DIODE HAVING HIGH VOLTAGE MARGINS FOR USE IN LARGE ARRAYS OF ELECTRONIC COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2015
|
Application #:
|
13210514
|
Filing Dt:
|
08/16/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
DETECTION OF SURFACE DEFECTS BY OPTICAL INLINE METROLOGY DURING Cu-CMP PROCESS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13210858
|
Filing Dt:
|
08/16/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
Methods of Forming a Non-Planar Cap Layer Above Conductive Lines on a Semiconductor Device
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13212489
|
Filing Dt:
|
08/18/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
METHOD FOR FORMING CORELESS FLIP CHIP BALL GRID ARRAY (FCBGA) SUBSTRATES AND SUCH SUBSTRATES FORMED BY THE METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13213740
|
Filing Dt:
|
08/19/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
HOMOGENEOUS MODIFICATION OF POROUS FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13214157
|
Filing Dt:
|
08/19/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
PROCESS TO FORM AN ADHESION LAYER AND MULTIPHASE ULTRA-LOW K DIELECTRIC MATERIAL USING PECVD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13214818
|
Filing Dt:
|
08/22/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
TECHNIQUES FOR RECOVERY OF WIRELESS SERVICES FOLLOWING POWER FAILURES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13215568
|
Filing Dt:
|
08/23/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
Semiconductor Device with DRAM Word Lines and Gate Electrodes in Non-Memory Regions of the Device Comprised of a Metal, and Methods of Making Same
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13215635
|
Filing Dt:
|
08/23/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13215738
|
Filing Dt:
|
08/23/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
FIXED CURVATURE FORCE LOADING OF MECHANICALLY SPALLED FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13215868
|
Filing Dt:
|
08/23/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
THERMAL COUPLING DETERMINATION AND REPRESENTATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13216708
|
Filing Dt:
|
08/24/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
PARASITIC CAPACITANCE REDUCTION IN MOSFET BY AIRGAP ILD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13216791
|
Filing Dt:
|
08/24/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH RECESSED SOURCE/DRAIN REGIONS, AND A SEMICONDUCTOR DEVICE COMPRISING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
13216862
|
Filing Dt:
|
08/24/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
IMPLANTATION OF HYDROGEN TO IMPROVE GATE INSULATION LAYER-SUBSTRATE INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13216921
|
Filing Dt:
|
08/24/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
METHODS OF FORMING STRESSED SILICON-CARBON AREAS IN AN NMOS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13217009
|
Filing Dt:
|
08/24/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
THRESHOLD VOLTAGE ADJUSTMENT IN A FIN TRANSISTOR BY CORNER IMPLANTATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13217061
|
Filing Dt:
|
08/24/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
ELECTRONIC DEVICE HAVING PLURAL FIN-FETS WITH DIFFERENT FIN HEIGHTS AND PLANAR FETS ON THE SAME SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13217335
|
Filing Dt:
|
08/25/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
SYNCHRONIZING GLOBAL CLOCKS IN 3D STACKS OF INTEGRATED CIRCUITS BY SHORTING THE CLOCK NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13217349
|
Filing Dt:
|
08/25/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13217381
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Filing Dt:
|
08/25/2011
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Publication #:
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|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
3D INTER-STRATUM CONNECTIVITY ROBUSTNESS
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|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
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Application #:
|
13217406
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Filing Dt:
|
08/25/2011
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Publication #:
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Pub Dt:
|
02/28/2013
| | | | |
Title:
|
AC SUPPLY NOISE REDUCTION IN A 3D STACK WITH VOLTAGE SENSING AND CLOCK SHIFTING
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|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13217429
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Filing Dt:
|
08/25/2011
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Publication #:
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Pub Dt:
|
02/28/2013
| | | | |
Title:
|
VERTICAL POWER BUDGETING AND SHIFTING FOR THREE-DIMENSIONAL INTEGRATION
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|
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Patent #:
|
|
Issue Dt:
|
08/27/2013
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Application #:
|
13217734
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Filing Dt:
|
08/25/2011
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Publication #:
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Pub Dt:
|
02/28/2013
| | | | |
Title:
|
PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STACK OF INTEGRATED CIRCUITS
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Patent #:
|
|
Issue Dt:
|
08/13/2013
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Application #:
|
13217792
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Filing Dt:
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08/25/2011
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Publication #:
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Pub Dt:
|
02/28/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH WORK FUNCTION ADJUSTING LAYER HAVING VARIED THICKNESS IN A GATE WIDTH DIRECTION AND METHODS OF MAKING SAME
|
|
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Patent #:
|
|
Issue Dt:
|
10/15/2013
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Application #:
|
13217975
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Filing Dt:
|
08/25/2011
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Publication #:
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Pub Dt:
|
02/28/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH DUAL METAL SILICIDE REGIONS AND METHODS OF MAKING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
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Application #:
|
13218089
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Filing Dt:
|
08/25/2011
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Publication #:
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|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
Methods of Forming Metal Silicide Regions on Semiconductor Devices Using Different Temperatures
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13218262
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Filing Dt:
|
08/25/2011
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Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
INTEGRATED CIRCUITS THAT INCLUDE DEEP TRENCH CAPACITORS AND METHODS FOR THEIR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13218589
|
Filing Dt:
|
08/26/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
METHODS OF FORMING AN ANODE AND A CATHODE OF A SUBSTRATE DIODE BY PERFORMING ANGLED ION IMPLANTATION PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
13219801
|
Filing Dt:
|
08/29/2011
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
INTERCONNECTION IN MULTI-CHIP WITH INTERPOSERS AND BRIDGES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13219813
|
Filing Dt:
|
08/29/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
EARLY DECOUPLING CAPACITOR OPTIMIZATION METHOD FOR HIERARCHICAL CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13220816
|
Filing Dt:
|
08/30/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
FORMATION OF METAL NANOSPHERES AND MICROSPHERES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13221198
|
Filing Dt:
|
08/30/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
METHOD TO ENABLE COMPRESSIVELY STRAINED PFET CHANNEL IN A FINFET STRUCTURE BY IMPLANT AND THERMAL DIFFUSION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13221248
|
Filing Dt:
|
08/30/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
REMOVAL OF ALKALINE CRYSTAL DEFECTS IN LITHOGRAPHIC PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13222306
|
Filing Dt:
|
08/31/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
ANALYZING EM PERFORMANCE DURING IC MANUFACTURING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13222469
|
Filing Dt:
|
08/31/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
SILICIDATION OF DEVICE CONTACTS USING PRE-AMORPHIZATION IMPLANT OF SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13222790
|
Filing Dt:
|
08/31/2011
|
Title:
|
ON-CHIP RADIATION DOSIMETER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13222928
|
Filing Dt:
|
08/31/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
SOFT HIERARCHY-BASED PHYSICAL SYNTHESIS FOR LARGE-SCALE, HIGH-PERFORMANCE CIRCUITS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13223016
|
Filing Dt:
|
08/31/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
MOSFET INTEGRATED CIRCUIT WITH IMPROVED SILICIDE THICKNESS UNIFORMITY AND METHODS FOR ITS MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2013
|
Application #:
|
13223706
|
Filing Dt:
|
09/01/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
MASK ASSIGNMENT FOR MULTIPLE PATTERNING LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13223844
|
Filing Dt:
|
09/01/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
Multiple Patterning Layout Decomposition for Ease of Conflict Removal
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13223998
|
Filing Dt:
|
09/01/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
METHOD AND APPARATUS FOR CHARACTERIZING DISCONTINUITIES IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
13224402
|
Filing Dt:
|
09/02/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
AUTOMATED LITHOGRAPHIC HOT SPOT DETECTION EMPLOYING UNSUPERVISED TOPOLOGICAL IMAGE CATEGORIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13224765
|
Filing Dt:
|
09/02/2011
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
Title:
|
ARRAY OF QUANTUM SYSTEMS IN A CAVITY FOR QUANTUM COMPUTING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
13224768
|
Filing Dt:
|
09/02/2011
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
Title:
|
MODULAR ARRAY OF FIXED-COUPLING QUANTUM SYSTEMS FOR QUANTUM INFORMATION PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13225320
|
Filing Dt:
|
09/02/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
LOW VISCOSITY ELECTROSTATIC DISCHARGE (ESD) DISSIPATING ADHESIVE SUBSTANTIALLY FREE OF AGGLOMERATES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13226557
|
Filing Dt:
|
09/07/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
REDUCING PHASE LOCKED LOOP PHASE LOCK TIME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13226650
|
Filing Dt:
|
09/07/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
TRANSIMPEDANCE AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13226838
|
Filing Dt:
|
09/07/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13227554
|
Filing Dt:
|
09/08/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
SRAM CELL HAVING RECESSED STORAGE NODE CONNECTIONS AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13227750
|
Filing Dt:
|
09/08/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13228023
|
Filing Dt:
|
09/08/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
INTERCONNECT STRUCTURES WITH FUNCTIONAL COMPONENTS AND ELECTRICAL CONDUCTIVE CONTACT STRUCTURES ON A SAME LEVEL, AND METHODS FOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13228491
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
EMBEDDING A NANOTUBE INSIDE A NANOPORE FOR DNA TRANSLOCATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13228767
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13228857
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
C-RICH CARBON BORON NITRIDE DIELECTRIC FILMS FOR USE IN ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13228983
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
Heat Treatment Process and Photovoltaic Device Based on Said Process
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13229154
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
METHOD FOR FABRICATING FIELD EFFECT TRANSISTOR DEVICES WITH HIGH-ASPECT RATIO MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13229440
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
DEPOSITION OF GERMANIUM FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13230083
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
01/05/2012
| | | | |
Title:
|
TRANSISTOR WITH ASYMMETRIC SILICON GERMANIUM SOURCE REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13230371
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13230442
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
03/15/2012
| | | | |
Title:
|
Reconfigurable Multi-level Sensing Scheme for Semiconductor Memories
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13230457
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
Strain-Compensating Fill Patterns for Controlling Semiconductor Chip Package Interactions
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13230474
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
SELECTIVE PRINT
|
|