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Patent #:
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|
Issue Dt:
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07/23/2013
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Application #:
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13345881
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Filing Dt:
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01/09/2012
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Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
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ISOLATED ZENER DIODE
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Patent #:
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Issue Dt:
|
07/29/2014
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Application #:
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13345889
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Filing Dt:
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01/09/2012
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Publication #:
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Pub Dt:
|
06/21/2012
| | | | |
Title:
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METHOD FOR HIGH DENSITY DATA STORAGE AND IMAGING
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Patent #:
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Issue Dt:
|
11/08/2016
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Application #:
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13345922
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Filing Dt:
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01/09/2012
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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Methods of Making Transistor Devices with Elevated Source/Drain Regions to Accommodate Consumption During Metal Silicide Formation Process
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Patent #:
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Issue Dt:
|
05/14/2013
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Application #:
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13346008
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Filing Dt:
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01/09/2012
|
Title:
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METHOD TO FORM LOW SERIES RESISTANCE TRANSISTOR DEVICES ON SILICON ON INSULATOR LAYER
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13346299
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Filing Dt:
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01/09/2012
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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NFET Device with Tensile Stressed Channel Region and Methods of Forming Same
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Patent #:
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Issue Dt:
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03/19/2013
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Application #:
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13346776
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Filing Dt:
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01/10/2012
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Publication #:
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Pub Dt:
|
05/03/2012
| | | | |
Title:
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METHODS OF FABRICATING PHOTOMASKS FOR IMPROVING DAMASCENE WIRE UNIFORMITY WITHOUT REDUCING PERFORMANCE
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Patent #:
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Issue Dt:
|
01/15/2013
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Application #:
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13347014
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Filing Dt:
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01/10/2012
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Publication #:
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Pub Dt:
|
05/03/2012
| | | | |
Title:
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THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION
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Patent #:
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Issue Dt:
|
05/06/2014
|
Application #:
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13347060
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Filing Dt:
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01/10/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
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APPARATUS AND METHOD FOR REMOVING A CMP PAD FROM A PLATEN
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13347435
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Filing Dt:
|
01/10/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
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TRANSISTOR WITH STRESS ENHANCED CHANNEL AND METHODS FOR FABRICATION
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Patent #:
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Issue Dt:
|
05/06/2014
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Application #:
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13347571
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Filing Dt:
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01/10/2012
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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INDUCTOR WITH LAMINATED YOKE
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13347687
|
Filing Dt:
|
01/10/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DIELECTRIC MATERIAL WITH HIGH MECHANICAL STRENGTH
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Patent #:
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|
Issue Dt:
|
10/28/2014
|
Application #:
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13347851
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Filing Dt:
|
01/11/2012
|
Publication #:
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|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
A TRANSISTOR STRUCTURE HAVING AN ELECTRICAL CONTACT STRUCTURE WITH MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER
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Patent #:
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Issue Dt:
|
01/14/2014
|
Application #:
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13348018
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Filing Dt:
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01/11/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES
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|
Patent #:
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Issue Dt:
|
02/03/2015
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Application #:
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13348142
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Filing Dt:
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01/11/2012
|
Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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13348184
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Filing Dt:
|
01/11/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
Methods of Forming Faceted Stress-Inducing Stressors Proximate the Gate Structure of a Transistor
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|
Patent #:
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|
Issue Dt:
|
10/15/2013
|
Application #:
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13348188
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Filing Dt:
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01/11/2012
|
Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
|
RECESSED SOURCE AND DRAIN REGIONS FOR FINFETS
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Patent #:
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|
Issue Dt:
|
10/14/2014
|
Application #:
|
13348256
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Filing Dt:
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01/11/2012
|
Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique
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|
Patent #:
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|
Issue Dt:
|
04/16/2013
|
Application #:
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13348355
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Filing Dt:
|
01/11/2012
|
Title:
|
CONTROLLING THRESHOLD VOLTAGE IN CARBON BASED FIELD EFFECT TRANSISTORS
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13348441
|
Filing Dt:
|
01/11/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING IN-LINE DIAGNOSTICS PERFORMED ON LOW-K DIELECTRIC LAYERS
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|
Patent #:
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Issue Dt:
|
10/15/2013
|
Application #:
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13348771
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Filing Dt:
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01/12/2012
|
Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
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METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER
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|
Patent #:
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|
Issue Dt:
|
05/14/2013
|
Application #:
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13349158
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Filing Dt:
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01/12/2012
|
Publication #:
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|
Pub Dt:
|
05/03/2012
| | | | |
Title:
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EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE
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|
Patent #:
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Issue Dt:
|
05/31/2016
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Application #:
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13349203
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Filing Dt:
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01/12/2012
|
Publication #:
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Pub Dt:
|
05/03/2012
| | | | |
Title:
|
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
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|
Patent #:
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|
Issue Dt:
|
07/23/2013
|
Application #:
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13349325
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Filing Dt:
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01/12/2012
|
Publication #:
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|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
TIMING ANALYSIS OF AN ARRAY CIRCUIT CROSS SECTION
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|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13349412
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Filing Dt:
|
01/12/2012
|
Title:
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METHODS FOR PATTERN MATCHING IN A DOUBLE PATTERNING TECHNOLOGY-COMPLIANT PHYSICAL DESIGN FLOW
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|
Patent #:
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Issue Dt:
|
01/27/2015
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Application #:
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13349942
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Filing Dt:
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01/13/2012
|
Publication #:
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|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
STRAIN ENGINEERING IN THREE-DIMENSIONAL TRANSISTORS BASED ON STRAINED ISOLATION MATERIAL
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|
Patent #:
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Issue Dt:
|
09/17/2013
|
Application #:
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13350174
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Filing Dt:
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01/13/2012
|
Publication #:
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Pub Dt:
|
05/10/2012
| | | | |
Title:
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PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE
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|
Patent #:
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Issue Dt:
|
12/25/2012
|
Application #:
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13350817
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Filing Dt:
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01/16/2012
|
Publication #:
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Pub Dt:
|
05/10/2012
| | | | |
Title:
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METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL
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|
Patent #:
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Issue Dt:
|
11/04/2014
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Application #:
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13350889
|
Filing Dt:
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01/16/2012
|
Publication #:
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|
Pub Dt:
|
05/10/2012
| | | | |
Title:
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LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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03/11/2014
|
Application #:
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13350891
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Filing Dt:
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01/16/2012
|
Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
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METHODS OF REDUCING GATE LEAKAGE
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|
Patent #:
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Issue Dt:
|
08/25/2015
|
Application #:
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13350908
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Filing Dt:
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01/16/2012
|
Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
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METHODS OF FORMING A DIELECTRIC CAP LAYER ON A METAL GATE STRUCTURE
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Patent #:
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Issue Dt:
|
01/21/2014
|
Application #:
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13350967
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Filing Dt:
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01/16/2012
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Publication #:
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Pub Dt:
|
05/10/2012
| | | | |
Title:
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IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER
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Patent #:
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Issue Dt:
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07/15/2014
|
Application #:
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13350981
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Filing Dt:
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01/16/2012
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
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ULTRA-COMPACT PLL WITH WIDE TUNING RANGE AND LOW NOISE
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Patent #:
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Issue Dt:
|
07/23/2013
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Application #:
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13351012
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Filing Dt:
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01/16/2012
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Publication #:
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Pub Dt:
|
05/17/2012
| | | | |
Title:
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TRENCH-GENERATED TRANSISTOR STRUCTURES, DEVICE STRUCTURES, AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13351294
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Filing Dt:
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01/17/2012
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Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
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LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES
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Patent #:
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Issue Dt:
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02/26/2013
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Application #:
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13351370
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Filing Dt:
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01/17/2012
|
Publication #:
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Pub Dt:
|
05/10/2012
| | | | |
Title:
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METHOD FOR FABRICATING AIR GAP INTERCONNECT STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
06/04/2013
|
Application #:
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13351398
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Filing Dt:
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01/17/2012
|
Publication #:
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|
Pub Dt:
|
05/10/2012
| | | | |
Title:
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GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
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|
Patent #:
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Issue Dt:
|
05/28/2013
|
Application #:
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13351402
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Filing Dt:
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01/17/2012
|
Publication #:
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|
Pub Dt:
|
05/10/2012
| | | | |
Title:
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GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
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Patent #:
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Issue Dt:
|
08/12/2014
|
Application #:
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13352131
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Filing Dt:
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01/17/2012
|
Publication #:
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Pub Dt:
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07/18/2013
| | | | |
Title:
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PREVENTION OF DATA LOSS DUE TO ADJACENT TRACK INTERFERENCE
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Patent #:
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Issue Dt:
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11/04/2014
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Application #:
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13352713
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Filing Dt:
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01/18/2012
|
Publication #:
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Pub Dt:
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07/18/2013
| | | | |
Title:
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ANALYZING A PATTERNING PROCESS USING A MODEL OF YIELD
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|
Patent #:
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Issue Dt:
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06/10/2014
|
Application #:
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13352737
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Filing Dt:
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01/18/2012
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Publication #:
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Pub Dt:
|
07/19/2012
| | | | |
Title:
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GRAPHENE DEVICES AND SEMICONDUCTOR FIELD EFFECT TRANSISTORS IN 3D HYBRID INTEGRATED CIRCUITS
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13352775
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Filing Dt:
|
01/18/2012
|
Publication #:
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|
Pub Dt:
|
07/18/2013
| | | | |
Title:
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Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer
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Patent #:
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Issue Dt:
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08/05/2014
|
Application #:
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13352851
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Filing Dt:
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01/18/2012
|
Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
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DIFFUSION BARRIER FOR OPPOSITELY DOPED PORTIONS OF GATE CONDUCTOR
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Patent #:
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Issue Dt:
|
05/27/2014
|
Application #:
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13353035
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Filing Dt:
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01/18/2012
|
Publication #:
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|
Pub Dt:
|
07/18/2013
| | | | |
Title:
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NEAR-NEIGHBOR TRIMMING OF DUMMY FILL SHAPES WITH BUILT-IN OPTICAL PROXIMITY CORRECTIONS FOR SEMICONDUCTOR APPLICATIONS
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|
Patent #:
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Issue Dt:
|
10/07/2014
|
Application #:
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13353118
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Filing Dt:
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01/18/2012
|
Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
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SILICON PHOTONIC CHIP OPTICAL COUPLING STRUCTURES
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|
Patent #:
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Issue Dt:
|
12/02/2014
|
Application #:
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13353162
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Filing Dt:
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01/18/2012
|
Publication #:
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|
Pub Dt:
|
07/18/2013
| | | | |
Title:
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SILICON PHOTONICS WAFER USING STANDARD SILICON-ON-INSULATOR PROCESSES THROUGH SUBSTRATE REMOVAL OR TRANSFER
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Patent #:
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Issue Dt:
|
07/08/2014
|
Application #:
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13353708
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Filing Dt:
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01/19/2012
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE
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|
Patent #:
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Issue Dt:
|
09/23/2014
|
Application #:
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13353879
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Filing Dt:
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01/19/2012
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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DYNAMIC GRADUATED MEMORY DEVICE PROTECTION IN REDUNDANT ARRAY OF INDEPENDENT MEMORY (RAIM) SYSTEMS
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Patent #:
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Issue Dt:
|
07/15/2014
|
Application #:
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13353925
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Filing Dt:
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01/19/2012
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM
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Patent #:
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|
Issue Dt:
|
09/29/2015
|
Application #:
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13354024
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Filing Dt:
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01/19/2012
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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FINFET SEMICONDUCTOR DEVICES WITH IMPROVED SOURCE/DRAIN RESISTANCE AND METHODS OF MAKING SAME
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Patent #:
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Issue Dt:
|
11/17/2015
|
Application #:
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13354070
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Filing Dt:
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01/19/2012
|
Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND METHODS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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05/19/2015
|
Application #:
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13354363
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Filing Dt:
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01/20/2012
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD OF FORMING THE SAME
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13354613
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Filing Dt:
|
01/20/2012
|
Publication #:
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|
Pub Dt:
|
08/02/2012
| | | | |
Title:
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High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials
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|
Patent #:
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Issue Dt:
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06/16/2015
|
Application #:
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13354705
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Filing Dt:
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01/20/2012
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
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|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13354717
|
Filing Dt:
|
01/20/2012
|
Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
ENERGY EFFICIENT AIR FLOW CONTROL
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|
Patent #:
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|
Issue Dt:
|
01/06/2015
|
Application #:
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13354739
|
Filing Dt:
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01/20/2012
|
Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHOD OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13354844
|
Filing Dt:
|
01/20/2012
|
Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
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Methods of Forming Replacement Gate Structures for Semiconductor Devices
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|
Patent #:
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|
Issue Dt:
|
10/23/2012
|
Application #:
|
13355221
|
Filing Dt:
|
01/20/2012
|
Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
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METHOD OF MANUFACTURING A TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS
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|
Patent #:
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|
Issue Dt:
|
09/09/2014
|
Application #:
|
13355691
|
Filing Dt:
|
01/23/2012
|
Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
EPITAXIAL REPLACEMENT OF A RAISED SOURCE/DRAIN
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|
Patent #:
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|
Issue Dt:
|
06/25/2013
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Application #:
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13355833
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Filing Dt:
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01/23/2012
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Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES
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Patent #:
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|
Issue Dt:
|
12/30/2014
|
Application #:
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13356013
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Filing Dt:
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01/23/2012
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Publication #:
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Pub Dt:
|
05/17/2012
| | | | |
Title:
|
ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT
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Patent #:
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|
Issue Dt:
|
06/16/2015
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Application #:
|
13356090
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Filing Dt:
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01/23/2012
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Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHOD TO FORM SILICIDE CONTACT IN TRENCHES
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13356326
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Filing Dt:
|
01/23/2012
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Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHODS FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED DAMAGE TO SHALLOW TRENCH ISOLATION (STI) REGIONS
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|
Patent #:
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|
Issue Dt:
|
01/08/2013
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Application #:
|
13356681
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Filing Dt:
|
01/24/2012
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Title:
|
ANALYTIC EXPERIMENTAL ESTIMATOR FOR IMPACT OF VOLTAGE-OVERSHOOT OF VOLTAGE WAVEFORM ON DIELECTRIC FAILURE/BREAKDOWN
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Patent #:
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|
Issue Dt:
|
01/07/2014
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Application #:
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13356778
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Filing Dt:
|
01/24/2012
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Publication #:
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|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
NEGATIVE COEFFICIENT THERMAL EXPANSION ENGINEERED PARTICLES FOR COMPOSITE FABRICATION
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13357285
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Filing Dt:
|
01/24/2012
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Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHODS OF FABRICATING INTEGRATED CIRCUITS WITH THE ELIMINATION OF VOIDS IN INTERLAYER DIELECTICS
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|
Patent #:
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|
Issue Dt:
|
01/01/2013
|
Application #:
|
13357656
|
Filing Dt:
|
01/25/2012
|
Publication #:
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|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
N-TYPE CARRIER ENHANCEMENT IN SEMICONDUCTORS
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|
Patent #:
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|
Issue Dt:
|
02/11/2014
|
Application #:
|
13357728
|
Filing Dt:
|
01/25/2012
|
Publication #:
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|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
ARRAY OF ALPHA PARTICLE SENSORS
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|
|
Patent #:
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|
Issue Dt:
|
07/01/2014
|
Application #:
|
13358101
|
Filing Dt:
|
01/25/2012
|
Publication #:
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|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
SOPHISTICATED GATE ELECTRODE STRUCTURES FORMED BY CAP LAYER REMOVAL WITH REDUCED LOSS OF EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL
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|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
13358172
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
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METHOD OF MANUFACTURING SWITCHING FILTERS AND DESIGN STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
|
13358180
|
Filing Dt:
|
01/25/2012
|
Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
04/02/2013
|
Application #:
|
13358963
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
3D OPTOELECTRONIC PACKAGING
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|
|
Patent #:
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|
Issue Dt:
|
07/09/2013
|
Application #:
|
13359100
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
3D OPTOELECTRONIC PACKAGING
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|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13359107
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
CELL ARRAY AND DENSITY FEATURES WITH DECOUPLING CAPACITORS
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|
|
Patent #:
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|
Issue Dt:
|
03/11/2014
|
Application #:
|
13359197
|
Filing Dt:
|
01/26/2012
|
Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
Methods of Forming SRAM Devices Using Sidewall Image Transfer Techniques
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13359242
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
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|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13359454
|
Filing Dt:
|
01/26/2012
|
Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS
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|
|
Patent #:
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|
Issue Dt:
|
07/16/2013
|
Application #:
|
13359634
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13359729
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
ELECTRON BEAM SCULPTING OF TUNNELING JUNCTION FOR NANOPORE DNA SEQUENCING
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|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13359818
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
METHODS FOR READING A FEATURE PATTERN FROM A PACKAGED DIE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13359858
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
Mosfet Structures Having Compressively Strained Silicon Channel
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|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13359970
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS
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|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13360055
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP
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|
|
Patent #:
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|
Issue Dt:
|
01/28/2014
|
Application #:
|
13360083
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY
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|
|
Patent #:
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|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360203
|
Filing Dt:
|
01/27/2012
|
Publication #:
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|
Pub Dt:
|
05/17/2012
| | | | |
Title:
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ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
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|
|
Patent #:
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|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360248
|
Filing Dt:
|
01/27/2012
|
Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
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|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360270
|
Filing Dt:
|
01/27/2012
|
Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
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|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360277
|
Filing Dt:
|
01/27/2012
|
Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
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ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
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|
Patent #:
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|
Issue Dt:
|
02/18/2014
|
Application #:
|
13360811
|
Filing Dt:
|
01/30/2012
|
Publication #:
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|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
BDD-BASED FUNCTIONAL COVERAGE ANALYSIS
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|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13360877
|
Filing Dt:
|
01/30/2012
|
Publication #:
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|
Pub Dt:
|
08/23/2012
| | | | |
Title:
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TRANSMISSION ELECTRON MICROSCOPY SAMPLE ETCHING FIXTURE
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|
Patent #:
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|
Issue Dt:
|
12/24/2013
|
Application #:
|
13361004
|
Filing Dt:
|
01/30/2012
|
Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SEMICONDUCTOR SUBSTRATES USING BANDGAP MATERIAL BETWEEN III-V CHANNEL MATERIAL AND INSULATOR LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13361051
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
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ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
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|
Patent #:
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|
Issue Dt:
|
08/20/2013
|
Application #:
|
13361595
|
Filing Dt:
|
01/30/2012
|
Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
METHODS FOR QUANTITATIVELY EVALUATING THE QUALITY OF DOUBLE PATTERNING TECHNOLOGY-COMPLIANT LAYOUTS
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13361644
|
Filing Dt:
|
01/30/2012
|
Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
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INTEGRATED CIRCUITS INCLUDING COPPER LOCAL INTERCONNECTS AND METHODS FOR THE MANUFACTURE THEREOF
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|
|
Patent #:
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|
Issue Dt:
|
01/08/2013
|
Application #:
|
13362019
|
Filing Dt:
|
01/31/2012
|
Publication #:
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|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR WITH CHANNEL REGION EDGE AND CENTER PORTIONS HAVING DIFFERENT BAND STRUCTURES FOR SUPPRESSED CORNER LEAKAGE
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|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13362228
|
Filing Dt:
|
01/31/2012
|
Title:
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UNIFORM SOLDER REFLOW FIXTURE
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|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13362366
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SUPERCONDUCTING QUANTUM CIRCUIT HAVING A RESONANT CAVITY THERMALIZED WITH METAL COMPONENTS
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|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13362398
|
Filing Dt:
|
01/31/2012
|
Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
METHODS OF EPITAXIAL FINFET
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|
|
Patent #:
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|
Issue Dt:
|
03/22/2016
|
Application #:
|
13362754
|
Filing Dt:
|
01/31/2012
|
Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
PROBABLISTIC SUBSURFACE MODELING FOR IMPROVED DRILL CONTROL AND REAL-TIME CORRECTION
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|
Patent #:
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|
Issue Dt:
|
07/08/2014
|
Application #:
|
13362763
|
Filing Dt:
|
01/31/2012
|
Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL
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|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13362862
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
LOW TEMPERATURE MELT-PROCESSING OF ORGANIC-INORGANIC HYBRID
|
|