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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 119 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
9040404
Issue Dt:
05/26/2015
Application #:
13676483
Filing Dt:
11/14/2012
Publication #:
US20140131808
Pub Dt:
05/15/2014
Title:
REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE
2
Patent #:
8828746
Issue Dt:
09/09/2014
Application #:
13676817
Filing Dt:
11/14/2012
Publication #:
US20140131800
Pub Dt:
05/15/2014
Title:
COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE
3
Patent #:
8772143
Issue Dt:
07/08/2014
Application #:
13676927
Filing Dt:
11/14/2012
Publication #:
US20140134826
Pub Dt:
05/15/2014
Title:
FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES
4
Patent #:
8650512
Issue Dt:
02/11/2014
Application #:
13677373
Filing Dt:
11/15/2012
Title:
ELASTIC MODULUS MAPPING OF AN INTEGRATED CIRCUIT CHIP IN A CHIP/DEVICE PACKAGE
5
Patent #:
9395408
Issue Dt:
07/19/2016
Application #:
13677542
Filing Dt:
11/15/2012
Publication #:
US20140107824
Pub Dt:
04/17/2014
Title:
System for Wafer Quality Predictive Modeling based on Multi-Source Information with Heterogeneous Relatedness
6
Patent #:
9059044
Issue Dt:
06/16/2015
Application #:
13677610
Filing Dt:
11/15/2012
Publication #:
US20140131803
Pub Dt:
05/15/2014
Title:
ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUCTOR DEVICES
7
Patent #:
8841177
Issue Dt:
09/23/2014
Application #:
13677647
Filing Dt:
11/15/2012
Publication #:
US20140134811
Pub Dt:
05/15/2014
Title:
CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
8
Patent #:
NONE
Issue Dt:
Application #:
13677651
Filing Dt:
11/15/2012
Publication #:
US20140131777
Pub Dt:
05/15/2014
Title:
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SALICIDE CONTACTS ON NON-PLANAR SOURCE/DRAIN REGIONS
9
Patent #:
8624361
Issue Dt:
01/07/2014
Application #:
13677863
Filing Dt:
11/15/2012
Title:
SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
10
Patent #:
9209024
Issue Dt:
12/08/2015
Application #:
13677908
Filing Dt:
11/15/2012
Publication #:
US20140117368
Pub Dt:
05/01/2014
Title:
BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
11
Patent #:
9048173
Issue Dt:
06/02/2015
Application #:
13677954
Filing Dt:
11/15/2012
Publication #:
US20140131722
Pub Dt:
05/15/2014
Title:
DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
12
Patent #:
9099381
Issue Dt:
08/04/2015
Application #:
13677997
Filing Dt:
11/15/2012
Publication #:
US20140134830
Pub Dt:
05/15/2014
Title:
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
13
Patent #:
8962421
Issue Dt:
02/24/2015
Application #:
13678011
Filing Dt:
11/15/2012
Publication #:
US20140134822
Pub Dt:
05/15/2014
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SEMICONDUCTIVE RESISTOR STRUCTURES IN A FINFET ARCHITECTURE
14
Patent #:
8963208
Issue Dt:
02/24/2015
Application #:
13678054
Filing Dt:
11/15/2012
Publication #:
US20140131771
Pub Dt:
05/15/2014
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION, AND METHOD FOR THE FORMATION THEREOF
15
Patent #:
8901713
Issue Dt:
12/02/2014
Application #:
13678111
Filing Dt:
11/15/2012
Publication #:
US20140103533
Pub Dt:
04/17/2014
Title:
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT
16
Patent #:
8835936
Issue Dt:
09/16/2014
Application #:
13678124
Filing Dt:
11/15/2012
Publication #:
US20140131735
Pub Dt:
05/15/2014
Title:
SOURCE AND DRAIN DOPING USING DOPED RAISED SOURCE AND DRAIN REGIONS
17
Patent #:
8584060
Issue Dt:
11/12/2013
Application #:
13679115
Filing Dt:
11/16/2012
Title:
BLOCK MASK DECOMPOSITION FOR MITIGATING CORNER ROUNDING
18
Patent #:
8653599
Issue Dt:
02/18/2014
Application #:
13679222
Filing Dt:
11/16/2012
Title:
STRAINED SIGE NANOWIRE HAVING (111)-ORIENTED SIDEWALLS
19
Patent #:
9053982
Issue Dt:
06/09/2015
Application #:
13679284
Filing Dt:
11/16/2012
Publication #:
US20140138771
Pub Dt:
05/22/2014
Title:
LOCAL TAILORING OF FINGERS IN MULTI-FINGER FIN FIELD EFFECT TRANSISTORS
20
Patent #:
8642453
Issue Dt:
02/04/2014
Application #:
13679357
Filing Dt:
11/16/2012
Publication #:
US20130072003
Pub Dt:
03/21/2013
Title:
SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE
21
Patent #:
8999831
Issue Dt:
04/07/2015
Application #:
13680257
Filing Dt:
11/19/2012
Publication #:
US20140141598
Pub Dt:
05/22/2014
Title:
METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
22
Patent #:
8685817
Issue Dt:
04/01/2014
Application #:
13680560
Filing Dt:
11/19/2012
Title:
METAL GATE STRUCTURES FOR CMOS TRANSISTOR DEVICES HAVING REDUCED PARASITIC CAPACITANCE
23
Patent #:
8775996
Issue Dt:
07/08/2014
Application #:
13680775
Filing Dt:
11/19/2012
Publication #:
US20140143746
Pub Dt:
05/22/2014
Title:
DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN
24
Patent #:
8822320
Issue Dt:
09/02/2014
Application #:
13681761
Filing Dt:
11/20/2012
Publication #:
US20140138797
Pub Dt:
05/22/2014
Title:
DENSE FINFET SRAM
25
Patent #:
8819600
Issue Dt:
08/26/2014
Application #:
13682056
Filing Dt:
11/20/2012
Publication #:
US20140143739
Pub Dt:
05/22/2014
Title:
POLYGON RECOVERY FOR VLSI MASK CORRECTION
26
Patent #:
8551848
Issue Dt:
10/08/2013
Application #:
13682108
Filing Dt:
11/20/2012
Publication #:
US20130078781
Pub Dt:
03/28/2013
Title:
FIELD EFFECT TRANSISTOR WITH ASYMMETRIC ABRUPT JUNCTION IMPLANT
27
Patent #:
8639375
Issue Dt:
01/28/2014
Application #:
13682184
Filing Dt:
11/20/2012
Publication #:
US20130103178
Pub Dt:
04/25/2013
Title:
ENHANCING INVESTIGATION OF VARIABILITY BY INCLUSION OF SIMILAR OBJECTS WITH KNOWN DIFFERENCES TO THE ORIGINAL ONES
28
Patent #:
NONE
Issue Dt:
Application #:
13682326
Filing Dt:
11/20/2012
Publication #:
US20140138837
Pub Dt:
05/22/2014
Title:
SANDWICHED DIFFUSION BARRIER AND METAL LINER FOR AN INTERCONNECT STRUCTURE
29
Patent #:
8716094
Issue Dt:
05/06/2014
Application #:
13682769
Filing Dt:
11/21/2012
Publication #:
US20140141605
Pub Dt:
05/22/2014
Title:
FINFET FORMATION USING DOUBLE PATTERNING MEMORIZATION
30
Patent #:
9325542
Issue Dt:
04/26/2016
Application #:
13683508
Filing Dt:
11/21/2012
Publication #:
US20140140439
Pub Dt:
05/22/2014
Title:
POWER-SCALABLE SKEW COMPENSATION IN SOURCE-SYNCHRONOUS PARALLEL INTERFACES
31
Patent #:
8766377
Issue Dt:
07/01/2014
Application #:
13684695
Filing Dt:
11/26/2012
Publication #:
US20140131790
Pub Dt:
05/15/2014
Title:
FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES
32
Patent #:
8987790
Issue Dt:
03/24/2015
Application #:
13684818
Filing Dt:
11/26/2012
Publication #:
US20140145247
Pub Dt:
05/29/2014
Title:
FIN ISOLATION IN MULTI-GATE FIELD EFFECT TRANSISTORS
33
Patent #:
8946792
Issue Dt:
02/03/2015
Application #:
13684842
Filing Dt:
11/26/2012
Publication #:
US20140145248
Pub Dt:
05/29/2014
Title:
DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM
34
Patent #:
8748252
Issue Dt:
06/10/2014
Application #:
13684869
Filing Dt:
11/26/2012
Publication #:
US20140148003
Pub Dt:
05/29/2014
Title:
REPLACEMENT METAL GATE TRANSISTORS USING BI-LAYER HARDMASK
35
Patent #:
NONE
Issue Dt:
Application #:
13684871
Filing Dt:
11/26/2012
Publication #:
US20140145332
Pub Dt:
05/29/2014
Title:
METHODS OF FORMING GRAPHENE LINERS AND/OR CAP LAYERS ON COPPER-BASED CONDUCTIVE STRUCTURES
36
Patent #:
8446759
Issue Dt:
05/21/2013
Application #:
13685077
Filing Dt:
11/26/2012
Publication #:
US20130083594
Pub Dt:
04/04/2013
Title:
MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY
37
Patent #:
8446760
Issue Dt:
05/21/2013
Application #:
13685113
Filing Dt:
11/26/2012
Publication #:
US20130077394
Pub Dt:
03/28/2013
Title:
MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY
38
Patent #:
9059242
Issue Dt:
06/16/2015
Application #:
13685733
Filing Dt:
11/27/2012
Publication #:
US20140145263
Pub Dt:
05/29/2014
Title:
Finfet Semiconductor Device Having Increased Gate Height Control
39
Patent #:
8697536
Issue Dt:
04/15/2014
Application #:
13685735
Filing Dt:
11/27/2012
Title:
LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE
40
Patent #:
8914688
Issue Dt:
12/16/2014
Application #:
13685779
Filing Dt:
11/27/2012
Publication #:
US20140149810
Pub Dt:
05/29/2014
Title:
SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRCUITRY
41
Patent #:
8775980
Issue Dt:
07/08/2014
Application #:
13686203
Filing Dt:
11/27/2012
Publication #:
US20140149952
Pub Dt:
05/29/2014
Title:
TRENCH SILICIDE MASK GENERATION USING DESIGNATED TRENCH TRANSFER AND TRENCH BLOCK REGIONS
42
Patent #:
8857022
Issue Dt:
10/14/2014
Application #:
13686263
Filing Dt:
11/27/2012
Publication #:
US20130081240
Pub Dt:
04/04/2013
Title:
METHOD OF MANUFACTURING COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS
43
Patent #:
8917210
Issue Dt:
12/23/2014
Application #:
13686377
Filing Dt:
11/27/2012
Publication #:
US20140145884
Pub Dt:
05/29/2014
Title:
PACKAGE STRUCTURES TO IMPROVE ON-CHIP ANTENNA PERFORMANCE
44
Patent #:
8683398
Issue Dt:
03/25/2014
Application #:
13686624
Filing Dt:
11/27/2012
Title:
AUTOMATED SYNTHESIS OF HIGH-PERFORMANCE TWO OPERAND BINARY PARALLEL PREFIX ADDER
45
Patent #:
9054020
Issue Dt:
06/09/2015
Application #:
13686969
Filing Dt:
11/28/2012
Publication #:
US20140145295
Pub Dt:
05/29/2014
Title:
DOUBLE DENSITY SEMICONDUCTOR FINS AND METHOD OF FABRICATION
46
Patent #:
8623719
Issue Dt:
01/07/2014
Application #:
13687240
Filing Dt:
11/28/2012
Publication #:
US20130122668
Pub Dt:
05/16/2013
Title:
METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET
47
Patent #:
8975635
Issue Dt:
03/10/2015
Application #:
13687314
Filing Dt:
11/28/2012
Publication #:
US20140131770
Pub Dt:
05/15/2014
Title:
CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
48
Patent #:
8803254
Issue Dt:
08/12/2014
Application #:
13687355
Filing Dt:
11/28/2012
Publication #:
US20140145274
Pub Dt:
05/29/2014
Title:
METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR NFET SEMICONDUCTOR DEVICES AND DEVICES HAVING SUCH GATE STRUCTURES
49
Patent #:
8828887
Issue Dt:
09/09/2014
Application #:
13687877
Filing Dt:
11/28/2012
Publication #:
US20130084703
Pub Dt:
04/04/2013
Title:
RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE
50
Patent #:
NONE
Issue Dt:
Application #:
13688258
Filing Dt:
11/29/2012
Publication #:
US20140148011
Pub Dt:
05/29/2014
Title:
METHOD OF FORMING SEMICONDUCTOR FINS
51
Patent #:
8890262
Issue Dt:
11/18/2014
Application #:
13688259
Filing Dt:
11/29/2012
Publication #:
US20140145257
Pub Dt:
05/29/2014
Title:
SEMICONDUCTOR DEVICE HAVING A METAL GATE RECESS
52
Patent #:
8591749
Issue Dt:
11/26/2013
Application #:
13688879
Filing Dt:
11/29/2012
Publication #:
US20130089815
Pub Dt:
04/11/2013
Title:
CHROMELESS PHASE-SHIFTING PHOTOMASK WITH UNDERCUT RIM-SHIFTING ELEMENT
53
Patent #:
8743596
Issue Dt:
06/03/2014
Application #:
13689052
Filing Dt:
11/29/2012
Publication #:
US20140127830
Pub Dt:
05/08/2014
Title:
MAGNETORESISTIVE RANDOM ACCESS MEMORY
54
Patent #:
9437670
Issue Dt:
09/06/2016
Application #:
13689090
Filing Dt:
11/29/2012
Publication #:
US20140145747
Pub Dt:
05/29/2014
Title:
LIGHT ACTIVATED TEST CONNECTIONS
55
Patent #:
8954912
Issue Dt:
02/10/2015
Application #:
13689437
Filing Dt:
11/29/2012
Publication #:
US20140149957
Pub Dt:
05/29/2014
Title:
STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS
56
Patent #:
8816401
Issue Dt:
08/26/2014
Application #:
13689838
Filing Dt:
11/30/2012
Publication #:
US20140151750
Pub Dt:
06/05/2014
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR
57
Patent #:
8691689
Issue Dt:
04/08/2014
Application #:
13689839
Filing Dt:
11/30/2012
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING LOW RESISTANCE DEVICE CONTACTS
58
Patent #:
8778789
Issue Dt:
07/15/2014
Application #:
13689844
Filing Dt:
11/30/2012
Publication #:
US20140154877
Pub Dt:
06/05/2014
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING LOW RESISTANCE METAL GATE STRUCTURES
59
Patent #:
8928057
Issue Dt:
01/06/2015
Application #:
13689924
Filing Dt:
11/30/2012
Publication #:
US20140151772
Pub Dt:
06/05/2014
Title:
UNIFORM FINFET GATE HEIGHT
60
Patent #:
NONE
Issue Dt:
Application #:
13689936
Filing Dt:
11/30/2012
Publication #:
US20140151818
Pub Dt:
06/05/2014
Title:
SEMICONDUCTOR DEVICE WITH A SILICON DIOXIDE GATE INSULATION LAYER IMPLANTED WITH A RARE EARTH ELEMENT AND METHODS OF MAKING SUCH A DEVICE
61
Patent #:
8829617
Issue Dt:
09/09/2014
Application #:
13689948
Filing Dt:
11/30/2012
Publication #:
US20140151801
Pub Dt:
06/05/2014
Title:
UNIFORM FINFET GATE HEIGHT
62
Patent #:
8956928
Issue Dt:
02/17/2015
Application #:
13689979
Filing Dt:
11/30/2012
Publication #:
US20140151816
Pub Dt:
06/05/2014
Title:
NOVEL CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
63
Patent #:
8949761
Issue Dt:
02/03/2015
Application #:
13690209
Filing Dt:
11/30/2012
Publication #:
US20140157221
Pub Dt:
06/05/2014
Title:
TECHNIQUES FOR ROUTING SIGNAL WIRES IN AN INTEGRATED CIRCUIT DESIGN
64
Patent #:
8946063
Issue Dt:
02/03/2015
Application #:
13690240
Filing Dt:
11/30/2012
Publication #:
US20140151802
Pub Dt:
06/05/2014
Title:
Semiconductor Device Having SSOI Substrate with Relaxed Tensile Stress
65
Patent #:
9029208
Issue Dt:
05/12/2015
Application #:
13690867
Filing Dt:
11/30/2012
Publication #:
US20140154846
Pub Dt:
06/05/2014
Title:
SEMICONDUCTOR DEVICE WITH REPLACEMENT METAL GATE AND METHOD FOR SELECTIVE DEPOSITION OF MATERIAL FOR REPLACEMENT METAL GATE
66
Patent #:
NONE
Issue Dt:
Application #:
13690871
Filing Dt:
11/30/2012
Publication #:
US20140156232
Pub Dt:
06/05/2014
Title:
METHODS, SYSTEMS AND COMPUTER PROGRAM STORAGE DEVICES FOR GENERATING A FLOODING FORECAST
67
Patent #:
9111761
Issue Dt:
08/18/2015
Application #:
13691129
Filing Dt:
11/30/2012
Publication #:
US20130087923
Pub Dt:
04/11/2013
Title:
MULTI COMPONENT DIELECTRIC LAYER
68
Patent #:
8815694
Issue Dt:
08/26/2014
Application #:
13692069
Filing Dt:
12/03/2012
Publication #:
US20140151803
Pub Dt:
06/05/2014
Title:
INDUCING CHANNEL STRESS IN SEMICONDUCTOR-ON-INSULATOR DEVICES BY BASE SUBSTRATE OXIDATION
69
Patent #:
NONE
Issue Dt:
Application #:
13692144
Filing Dt:
12/03/2012
Publication #:
US20140151756
Pub Dt:
06/05/2014
Title:
FIN FIELD EFFECT TRANSISTORS INCLUDING COMPLIMENTARILY STRESSED CHANNELS
70
Patent #:
NONE
Issue Dt:
Application #:
13692162
Filing Dt:
12/03/2012
Publication #:
US20140151757
Pub Dt:
06/05/2014
Title:
SUBSTRATE-TEMPLATED EPITAXIAL SOURCE/DRAIN CONTACT STRUCTURES
71
Patent #:
NONE
Issue Dt:
Application #:
13692182
Filing Dt:
12/03/2012
Publication #:
US20140151638
Pub Dt:
06/05/2014
Title:
HYBRID NANOMESH STRUCTURES
72
Patent #:
8772116
Issue Dt:
07/08/2014
Application #:
13692603
Filing Dt:
12/03/2012
Publication #:
US20140138781
Pub Dt:
05/22/2014
Title:
DIELECTRIC EQUIVALENT THICKNESS AND CAPACITANCE SCALING FOR SEMICONDUCTOR DEVICES
73
Patent #:
8697501
Issue Dt:
04/15/2014
Application #:
13693094
Filing Dt:
12/04/2012
Title:
SEMICONDUCTOR DEVICE HAVING A GATE FORMED ON A UNIFORM SURFACE AND METHOD FOR FORMING THE SAME
74
Patent #:
8607175
Issue Dt:
12/10/2013
Application #:
13693127
Filing Dt:
12/04/2012
Title:
IDENTIFYING LOGIC BLOCKS IN A SYNTHESIZED LOGIC DESIGN THAT HAVE SPECIFIED INPUTS
75
Patent #:
8735947
Issue Dt:
05/27/2014
Application #:
13693285
Filing Dt:
12/04/2012
Publication #:
US20140151786
Pub Dt:
06/05/2014
Title:
NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH
76
Patent #:
8956808
Issue Dt:
02/17/2015
Application #:
13693627
Filing Dt:
12/04/2012
Publication #:
US20140154630
Pub Dt:
06/05/2014
Title:
ASYMMETRIC TEMPLATES FOR FORMING NON-PERIODIC PATTERNS USING DIRECTES SELF-ASSEMBLY MATERIALS
77
Patent #:
8932956
Issue Dt:
01/13/2015
Application #:
13693749
Filing Dt:
12/04/2012
Publication #:
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Pub Dt:
06/05/2014
Title:
FAR BACK END OF THE LINE STACK ENCAPSULATION
78
Patent #:
8796099
Issue Dt:
08/05/2014
Application #:
13705242
Filing Dt:
12/05/2012
Publication #:
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Pub Dt:
06/05/2014
Title:
Inducing Channel Strain via Encapsulated Silicide Formation
79
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8772117
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07/08/2014
Application #:
13705261
Filing Dt:
12/05/2012
Publication #:
US20140151807
Pub Dt:
06/05/2014
Title:
COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE
80
Patent #:
9052722
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06/09/2015
Application #:
13705300
Filing Dt:
12/05/2012
Publication #:
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Pub Dt:
05/30/2013
Title:
DYNAMICALLY LIMITING ENERGY CONSUMED BY COOLING APPARATUS
81
Patent #:
8673729
Issue Dt:
03/18/2014
Application #:
13705477
Filing Dt:
12/05/2012
Title:
Finfet eDram Strap Connection Structure
82
Patent #:
9093491
Issue Dt:
07/28/2015
Application #:
13705717
Filing Dt:
12/05/2012
Publication #:
US20140151852
Pub Dt:
06/05/2014
Title:
BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
83
Patent #:
NONE
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Application #:
13705738
Filing Dt:
12/05/2012
Publication #:
US20140156235
Pub Dt:
06/05/2014
Title:
MODELING MULTIPLE INTERACTIONS BETWEEN MULTIPLE LOCI
84
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8609481
Issue Dt:
12/17/2013
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13705920
Filing Dt:
12/05/2012
Title:
GATE-ALL-AROUND CARBON NANOTUBE TRANSISTOR WITH SELECTIVELY DOPED SPACERS
85
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8643122
Issue Dt:
02/04/2014
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13707058
Filing Dt:
12/06/2012
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Pub Dt:
05/16/2013
Title:
SILICIDE CONTACTS HAVING DIFFERENT SHAPES ON REGIONS OF A SEMICONDUCTOR DEVICE
86
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8815668
Issue Dt:
08/26/2014
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13708126
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Pub Dt:
06/12/2014
Title:
Preventing FIN Erosion and Limiting Epi Overburden in FinFET Structures by Composite Hardmask
87
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8581392
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11/12/2013
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13708499
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12/07/2012
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US20130092938
Pub Dt:
04/18/2013
Title:
SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE
88
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8815684
Issue Dt:
08/26/2014
Application #:
13708531
Filing Dt:
12/07/2012
Publication #:
US20140159162
Pub Dt:
06/12/2014
Title:
BULK FINFET WITH SUPER STEEP RETROGRADE WELL
89
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9007800
Issue Dt:
04/14/2015
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13708988
Filing Dt:
12/08/2012
Publication #:
US20140160836
Pub Dt:
06/12/2014
Title:
THREE-DIMENSIONAL MEMORY ARRAY AND OPERATION SCHEME
90
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9059206
Issue Dt:
06/16/2015
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13709095
Filing Dt:
12/10/2012
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US20140159124
Pub Dt:
06/12/2014
Title:
EPITAXIAL GROWN EXTREMELY SHALLOW EXTENSION REGION
91
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NONE
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Filing Dt:
12/10/2012
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US20140162447
Pub Dt:
06/12/2014
Title:
FINFET HYBRID FULL METAL GATE WITH BORDERLESS CONTACTS
92
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8722174
Issue Dt:
05/13/2014
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13709397
Filing Dt:
12/10/2012
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Pub Dt:
04/25/2013
Title:
METHOD OF FORMING SELF-ASSEMBLED PATTERNS USING BLOCK COPOLYMERS, AND ARTICLES THEREOF
93
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8889561
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11/18/2014
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13709541
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12/10/2012
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US20140159164
Pub Dt:
06/12/2014
Title:
DOUBLE SIDEWALL IMAGE TRANSFER PROCESS
94
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8728927
Issue Dt:
05/20/2014
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13709662
Filing Dt:
12/10/2012
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Pub Dt:
06/12/2014
Title:
BORDERLESS CONTACTS FOR SEMICONDUCTOR TRANSISTORS
95
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8739085
Issue Dt:
05/27/2014
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13709748
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12/10/2012
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US20140165015
Pub Dt:
06/12/2014
Title:
VECTORIZATION OF BIT-LEVEL NETLISTS
96
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8895211
Issue Dt:
11/25/2014
Application #:
13710498
Filing Dt:
12/11/2012
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US20140162176
Pub Dt:
06/12/2014
Title:
SEMICONDUCTOR DEVICE RESOLUTION ENHANCEMENT BY ETCHING MULTIPLE SIDES OF A MASK
97
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8887014
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11/11/2014
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13710551
Filing Dt:
12/11/2012
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US20140164820
Pub Dt:
06/12/2014
Title:
MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING
98
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8898544
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11/25/2014
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13710561
Filing Dt:
12/11/2012
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US20140164871
Pub Dt:
06/12/2014
Title:
DRAM ERROR DETECTION, EVALUATION, AND CORRECTION
99
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8823149
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09/02/2014
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13710575
Filing Dt:
12/11/2012
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US20140159125
Pub Dt:
06/12/2014
Title:
CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
100
Patent #:
8767432
Issue Dt:
07/01/2014
Application #:
13710616
Filing Dt:
12/11/2012
Publication #:
US20140160829
Pub Dt:
06/12/2014
Title:
METHOD AND APPARATUS FOR CONTROLLED APPLICATION OF OERSTED FIELD TO MAGNETIC MEMORY STRUCTURE
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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