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Reel/Frame:	056987/0001			Pages:	1045
		Recorded:	05/12/2021
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 18026
Page 121 of 181
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Patent #:	8652919	Issue Dt:	02/18/2014	Application #:	13740673	Filing Dt:	01/14/2013
Publication #:	US20130130462	Pub Dt:	05/23/2013
Title:	TUNABLE SEMICONDUCTOR DEVICE

Patent #:	9029214	Issue Dt:	05/12/2015	Application #:	13740974	Filing Dt:	01/14/2013
Publication #:	US20140197498	Pub Dt:	07/17/2014
Title:	INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED SILICIDE CONTACTS

Patent #:	9117946	Issue Dt:	08/25/2015	Application #:	13741416	Filing Dt:	01/15/2013
Publication #:	US20140197507	Pub Dt:	07/17/2014
Title:	BURIED WAVEGUIDE PHOTODETECTOR

Patent #:	8799848	Issue Dt:	08/05/2014	Application #:	13741490	Filing Dt:	01/15/2013
Publication #:	US20140201699	Pub Dt:	07/17/2014
Title:	METHODS FOR MODELING OF FINFET WIDTH QUANTIZATION

Patent #:	8986921	Issue Dt:	03/24/2015	Application #:	13741611	Filing Dt:	01/15/2013
Publication #:	US20140199628	Pub Dt:	07/17/2014
Title:	LITHOGRAPHIC MATERIAL STACK INCLUDING A METAL-COMPOUND HARD MASK

Patent #:	8987133	Issue Dt:	03/24/2015	Application #:	13741638	Filing Dt:	01/15/2013
Publication #:	US20140199832	Pub Dt:	07/17/2014
Title:	TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING

Patent #:	8869081	Issue Dt:	10/21/2014	Application #:	13741645	Filing Dt:	01/15/2013
Publication #:	US20140201693	Pub Dt:	07/17/2014
Title:	AUTOMATING INTEGRATED CIRCUIT DEVICE LIBRARY GENERATION IN MODEL BASED METROLOGY

Patent #:	8791550	Issue Dt:	07/29/2014	Application #:	13741947	Filing Dt:	01/15/2013
Publication #:	US20140197522	Pub Dt:	07/17/2014
Title:	HYBRID CONDUCTOR THROUGH-SILICON-VIA FOR POWER DISTRIBUTION AND SIGNAL TRANSMISSION

Patent #:	8601348	Issue Dt:	12/03/2013	Application #:	13742338	Filing Dt:	01/15/2013
Publication #:	US20130132801	Pub Dt:	05/23/2013
Title:	ERROR CHECKING ADDRESSABLE BLOCKS IN STORAGE

Patent #:	8946371	Issue Dt:	02/03/2015	Application #:	13742465	Filing Dt:	01/16/2013
Publication #:	US20130189836	Pub Dt:	07/25/2013
Title:	PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF

Patent #:	9006373	Issue Dt:	04/14/2015	Application #:	13742490	Filing Dt:	01/16/2013
Publication #:	US20130207278	Pub Dt:	08/15/2013
Title:	PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF

Patent #:	8637388	Issue Dt:	01/28/2014	Application #:	13742508	Filing Dt:	01/16/2013
Publication #:	US20130127063	Pub Dt:	05/23/2013
Title:	SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE

Patent #:	8981031	Issue Dt:	03/17/2015	Application #:	13742526	Filing Dt:	01/16/2013
Publication #:	US20130197253	Pub Dt:	08/01/2013
Title:	PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF

Patent #:	9058903	Issue Dt:	06/16/2015	Application #:	13742733	Filing Dt:	01/16/2013
Publication #:	US20140201579	Pub Dt:	07/17/2014
Title:	METHODS AND CIRCUITS FOR DISRUPTING INTEGRATED CIRCUIT FUNCTION

Patent #:	8871624	Issue Dt:	10/28/2014	Application #:	13742916	Filing Dt:	01/16/2013
Publication #:	US20130130489	Pub Dt:	05/23/2013
Title:	SEALED AIR GAP FOR SEMICONDUCTOR CHIP

Patent #:	8928048	Issue Dt:	01/06/2015	Application #:	13743454	Filing Dt:	01/17/2013
Publication #:	US20140197468	Pub Dt:	07/17/2014
Title:	METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICE

Patent #:	9066460	Issue Dt:	06/23/2015	Application #:	13743642	Filing Dt:	01/17/2013
Publication #:	US20140198452	Pub Dt:	07/17/2014
Title:	DISASSEMBLABLE ELECTRONIC ASSEMBLY WITH LEAK-INHIBITING COOLANT CAPILLARIES

Patent #:	8839159	Issue Dt:	09/16/2014	Application #:	13743810	Filing Dt:	01/17/2013
Publication #:	US20140201697	Pub Dt:	07/17/2014
Title:	DETERMINING OVERALL OPTIMAL YIELD POINT FOR A SEMICONDUCTOR WAFER

Patent #:	8916442	Issue Dt:	12/23/2014	Application #:	13743886	Filing Dt:	01/17/2013
Publication #:	US20140197411	Pub Dt:	07/17/2014
Title:	METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE

Patent #:	9455372	Issue Dt:	09/27/2016	Application #:	13743935	Filing Dt:	01/17/2013
Publication #:	US20130143335	Pub Dt:	06/06/2013
Title:	METHOD AND APPARATUS FOR OPTICAL MODULATION

Patent #:	8815725	Issue Dt:	08/26/2014	Application #:	13744468	Filing Dt:	01/18/2013
Publication #:	US20140203427	Pub Dt:	07/24/2014
Title:	LOW ALPHA PARTICLE EMISSION ELECTRICALLY-CONDUCTIVE COATING

Patent #:	9455188	Issue Dt:	09/27/2016	Application #:	13744551	Filing Dt:	01/18/2013
Publication #:	US20140203446	Pub Dt:	07/24/2014
Title:	THROUGH SILICON VIA DEVICE HAVING LOW STRESS, THIN FILM GAPS AND METHODS FOR FORMING THE SAME

Patent #:	NONE	Issue Dt:		Application #:	13744601	Filing Dt:	01/18/2013
Publication #:	US20130270656	Pub Dt:	10/17/2013
Title:	REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES

Patent #:	8656322	Issue Dt:	02/18/2014	Application #:	13744606	Filing Dt:	01/18/2013
Title:	FIN DESIGN LEVEL MASK DECOMPOSITION FOR DIRECTED SELF ASSEMBLY

Patent #:	9059494	Issue Dt:	06/16/2015	Application #:	13744761	Filing Dt:	01/18/2013
Publication #:	US20140203885	Pub Dt:	07/24/2014
Title:	MARCHAND BALUN STRUCTURE AND DESIGN METHOD

Patent #:	8564935	Issue Dt:	10/22/2013	Application #:	13745221	Filing Dt:	01/18/2013
Publication #:	US20130128413	Pub Dt:	05/23/2013
Title:	HIGH ENERGY DENSITY STORAGE MATERIAL DEVICE USING NANOCHANNEL STRUCTURE

Patent #:	9070742	Issue Dt:	06/30/2015	Application #:	13745547	Filing Dt:	01/18/2013
Publication #:	US20140203376	Pub Dt:	07/24/2014
Title:	FINFET INTEGRATED CIRCUITS WITH UNIFORM FIN HEIGHT AND METHODS FOR FABRICATING THE SAME

Patent #:	8969145	Issue Dt:	03/03/2015	Application #:	13745770	Filing Dt:	01/19/2013
Publication #:	US20140203238	Pub Dt:	07/24/2014
Title:	Wire-Last Integration Method and Structure for III-V Nanowire Devices

Patent #:	8691640	Issue Dt:	04/08/2014	Application #:	13745927	Filing Dt:	01/21/2013
Title:	METHODS OF FORMING DIELECTRICALLY ISOLATED FINS FOR A FINFET SEMICONDUCTOR BY PERFORMING AN ETCHING PROCESS WHEREIN THE ETCH RATE IS MODIFIED VIA INCLUSION OF A DOPANT MATERIAL

Patent #:	8975094	Issue Dt:	03/10/2015	Application #:	13745929	Filing Dt:	01/21/2013
Publication #:	US20140203279	Pub Dt:	07/24/2014
Title:	TEST STRUCTURE AND METHOD TO FACILTIATE DEVELOPMENT/OPTIMIZATION OF PROCESS PARAMETERS

Patent #:	9123421	Issue Dt:	09/01/2015	Application #:	13745963	Filing Dt:	01/21/2013
Publication #:	US20140204647	Pub Dt:	07/24/2014
Title:	RACETRACK MEMORY CELLS WITH A VERTICAL NANOWIRE STORAGE ELEMENT

Patent #:	9059552	Issue Dt:	06/16/2015	Application #:	13745965	Filing Dt:	01/21/2013
Publication #:	US20140206206	Pub Dt:	07/24/2014
Title:	LAND GRID ARRAY (LGA) SOCKET CARTRIDGE AND METHOD OF FORMING

Patent #:	9269561	Issue Dt:	02/23/2016	Application #:	13746359	Filing Dt:	01/22/2013
Publication #:	US20140147986	Pub Dt:	05/29/2014
Title:	WAFER DEBONDING USING LONG-WAVELENGTH INFRARED RADIATION ABLATION

Patent #:	9208013	Issue Dt:	12/08/2015	Application #:	13746463	Filing Dt:	01/22/2013
Publication #:	US20140208150	Pub Dt:	07/24/2014
Title:	CROSS COMMUNICATION OF COMMON PROBLEM DETERMINATION AND RESOLUTION

Patent #:	8839168	Issue Dt:	09/16/2014	Application #:	13746508	Filing Dt:	01/22/2013
Publication #:	US20140208285	Pub Dt:	07/24/2014
Title:	SELF-ALIGNED DOUBLE PATTERNING VIA ENCLOSURE DESIGN

Patent #:	8975531	Issue Dt:	03/10/2015	Application #:	13746627	Filing Dt:	01/22/2013
Publication #:	US20140202746	Pub Dt:	07/24/2014
Title:	COMPOSITE COPPER WIRE INTERCONNECT STRUCTURES AND METHODS OF FORMING

Patent #:	9291660	Issue Dt:	03/22/2016	Application #:	13746699	Filing Dt:	01/22/2013
Publication #:	US20140203814	Pub Dt:	07/24/2014
Title:	METHOD AND APPARATUS FOR MEASURING ALPHA PARTICLE INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES

Patent #:	9245790	Issue Dt:	01/26/2016	Application #:	13747579	Filing Dt:	01/23/2013
Publication #:	US20140203827	Pub Dt:	07/24/2014
Title:	INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH MULTIPLE EMBEDDED INTERCONNECT CONNECTION TO SAME THROUGH-SEMICONDUCTOR VIA

Patent #:	9286425	Issue Dt:	03/15/2016	Application #:	13747798	Filing Dt:	01/23/2013
Publication #:	US20130132924	Pub Dt:	05/23/2013
Title:	METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS

Patent #:	9065481	Issue Dt:	06/23/2015	Application #:	13747842	Filing Dt:	01/23/2013
Publication #:	US20130339823	Pub Dt:	12/19/2013
Title:	BAD WORDLINE/ARRAY DETECTION IN MEMORY

Patent #:	8835255	Issue Dt:	09/16/2014	Application #:	13747907	Filing Dt:	01/23/2013
Publication #:	US20140206157	Pub Dt:	07/24/2014
Title:	METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A VERTICAL NANOWIRE

Patent #:	8735241	Issue Dt:	05/27/2014	Application #:	13747972	Filing Dt:	01/23/2013
Title:	SEMICONDUCTOR DEVICE STRUCTURE AND METHODS FOR FORMING A CMOS INTEGRATED CIRCUIT STRUCTURE

Patent #:	9263782	Issue Dt:	02/16/2016	Application #:	13748048	Filing Dt:	01/23/2013
Publication #:	US20140203894	Pub Dt:	07/24/2014
Title:	NOTCH FILTER STRUCTURE WITH OPEN STUBS IN SEMICONDUCTOR SUBSTRATE AND DESIGN STRUCTURE

Patent #:	9761481	Issue Dt:	09/12/2017	Application #:	13748159	Filing Dt:	01/23/2013
Publication #:	US20140203449	Pub Dt:	07/24/2014
Title:	INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH METAL LAYER CONNECTION TO THROUGH-SEMICONDUCTOR VIA

Patent #:	8896032	Issue Dt:	11/25/2014	Application #:	13748197	Filing Dt:	01/23/2013
Publication #:	US20140203332	Pub Dt:	07/24/2014
Title:	SELF-ALIGNED BIOSENSORS WITH ENHANCED SENSITIVITY

Patent #:	8912032	Issue Dt:	12/16/2014	Application #:	13748226	Filing Dt:	01/23/2013
Publication #:	US20130137202	Pub Dt:	05/30/2013
Title:	TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES

Patent #:	9059183	Issue Dt:	06/16/2015	Application #:	13748662	Filing Dt:	01/24/2013
Publication #:	US20130134566	Pub Dt:	05/30/2013
Title:	STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING

Patent #:	8933562	Issue Dt:	01/13/2015	Application #:	13748821	Filing Dt:	01/24/2013
Publication #:	US20140203433	Pub Dt:	07/24/2014
Title:	IN-SITU THERMOELECTRIC COOLING

Patent #:	8847354	Issue Dt:	09/30/2014	Application #:	13749146	Filing Dt:	01/24/2013
Publication #:	US20130134557	Pub Dt:	05/30/2013
Title:	METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY

Patent #:	8829339	Issue Dt:	09/09/2014	Application #:	13749222	Filing Dt:	01/24/2013
Publication #:	US20140166096	Pub Dt:	06/19/2014
Title:	FIELD-EFFECT INTER-DIGITATED BACK CONTACT PHOTOVOLTAIC DEVICE

Patent #:	8839170	Issue Dt:	09/16/2014	Application #:	13749851	Filing Dt:	01/25/2013
Publication #:	US20130326459	Pub Dt:	12/05/2013
Title:	POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL

Patent #:	8839165	Issue Dt:	09/16/2014	Application #:	13749925	Filing Dt:	01/25/2013
Publication #:	US20140215429	Pub Dt:	07/31/2014
Title:	POWER/PERFORMANCE OPTIMIZATION THROUGH CONTINUOUSLY VARIABLE TEMPERATURE-BASED VOLTAGE CONTROL

Patent #:	9201989	Issue Dt:	12/01/2015	Application #:	13750751	Filing Dt:	01/25/2013
Publication #:	US20140214372	Pub Dt:	07/31/2014
Title:	INTERPOLATION TECHNIQUES USED FOR TIME ALIGNMENT OF MULTIPLE SIMULATION MODELS

Patent #:	8889491	Issue Dt:	11/18/2014	Application #:	13751238	Filing Dt:	01/28/2013
Publication #:	US20140210040	Pub Dt:	07/31/2014
Title:	METHOD OF FORMING ELECTRONIC FUSE LINE WITH MODIFIED CAP

Patent #:	8921939	Issue Dt:	12/30/2014	Application #:	13751361	Filing Dt:	01/28/2013
Publication #:	US20130140636	Pub Dt:	06/06/2013
Title:	STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS

Patent #:	9064942	Issue Dt:	06/23/2015	Application #:	13751490	Filing Dt:	01/28/2013
Publication #:	US20140209854	Pub Dt:	07/31/2014
Title:	Nanowire Capacitor for Bidirectional Operation

Patent #:	9059075	Issue Dt:	06/16/2015	Application #:	13751799	Filing Dt:	01/28/2013
Publication #:	US20140131724	Pub Dt:	05/15/2014
Title:	SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON

Patent #:	8952503	Issue Dt:	02/10/2015	Application #:	13752737	Filing Dt:	01/29/2013
Publication #:	US20140210059	Pub Dt:	07/31/2014
Title:	ORGANIC MODULE EMI SHIELDING STRUCTURES AND METHODS

Patent #:	8527920	Issue Dt:	09/03/2013	Application #:	13752934	Filing Dt:	01/29/2013
Title:	AUTOMATED SYNTHESIS OF HIGH-PERFORMANCE TWO OPERAND BINARY PARALLEL PREFIX ADDER

Patent #:	9305016	Issue Dt:	04/05/2016	Application #:	13752948	Filing Dt:	01/29/2013
Publication #:	US20130144851	Pub Dt:	06/06/2013
Title:	EFFICIENT DATA EXTRACTION BY A REMOTE APPLICATION

Patent #:	8828839	Issue Dt:	09/09/2014	Application #:	13753269	Filing Dt:	01/29/2013
Publication #:	US20140213033	Pub Dt:	07/31/2014
Title:	METHODS FOR FABRICATING ELECTRICALLY-ISOLATED FINFET SEMICONDUCTOR DEVICES

Patent #:	8934312	Issue Dt:	01/13/2015	Application #:	13753989	Filing Dt:	01/30/2013
Publication #:	US20140211581	Pub Dt:	07/31/2014
Title:	PROCESS VARIATION SKEW IN AN SRAM COLUMN ARCHITECTURE

Patent #:	8999767	Issue Dt:	04/07/2015	Application #:	13755030	Filing Dt:	01/31/2013
Publication #:	US20140210041	Pub Dt:	07/31/2014
Title:	ELECTRONIC FUSE HAVING AN INSULATION LAYER

Patent #:	NONE	Issue Dt:		Application #:	13755182	Filing Dt:	01/31/2013
Publication #:	US20140211175	Pub Dt:	07/31/2014
Title:	ENHANCING RESOLUTION IN LITHOGRAPHIC PROCESSES USING HIGH REFRACTIVE INDEX FLUIDS

Patent #:	8710500	Issue Dt:	04/29/2014	Application #:	13755192	Filing Dt:	01/31/2013
Publication #:	US20130140566	Pub Dt:	06/06/2013
Title:	BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE

Patent #:	8815685	Issue Dt:	08/26/2014	Application #:	13755246	Filing Dt:	01/31/2013
Publication #:	US20140213037	Pub Dt:	07/31/2014
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING CONFINED EPITAXIAL GROWTH REGIONS

Patent #:	8924896	Issue Dt:	12/30/2014	Application #:	13755374	Filing Dt:	01/31/2013
Publication #:	US20140215415	Pub Dt:	07/31/2014
Title:	AUTOMATED DESIGN LAYOUT PATTERN CORRECTION BASED ON CONTEXT-AWARE PATTERNS

Patent #:	NONE	Issue Dt:		Application #:	13755427	Filing Dt:	01/31/2013
Publication #:	US20140210011	Pub Dt:	07/31/2014
Title:	Dual Silicide Process

Patent #:	9147031	Issue Dt:	09/29/2015	Application #:	13755726	Filing Dt:	01/31/2013
Publication #:	US20140173547	Pub Dt:	06/19/2014
Title:	ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION

Patent #:	8865596	Issue Dt:	10/21/2014	Application #:	13755807	Filing Dt:	01/31/2013
Publication #:	US20130143409	Pub Dt:	06/06/2013
Title:	METHODS FOR FORMING SEMICONDUCTOR STRUCTURES USING SELECTIVELY-FORMED SIDEWALL SPACERS

Patent #:	8766259	Issue Dt:	07/01/2014	Application #:	13756638	Filing Dt:	02/01/2013
Publication #:	US20130140565	Pub Dt:	06/06/2013
Title:	TEST STRUCTURE FOR DETECTION OF GAP IN CONDUCTIVE LAYER OF MULTILAYER GATE STACK

Patent #:	8679971	Issue Dt:	03/25/2014	Application #:	13756981	Filing Dt:	02/01/2013
Publication #:	US20130143400	Pub Dt:	06/06/2013
Title:	METAL-CONTAMINATION-FREE THROUGH-SUBSTRATE VIA STRUCTURE

Patent #:	8536610	Issue Dt:	09/17/2013	Application #:	13757040	Filing Dt:	02/01/2013
Publication #:	US20130142211	Pub Dt:	06/06/2013
Title:	PARALLEL OPTICAL TRANSCEIVER MODULE

Patent #:	8716156	Issue Dt:	05/06/2014	Application #:	13757069	Filing Dt:	02/01/2013
Title:	METHODS OF FORMING FINS FOR A FINFET SEMICONDUCTOR DEVICE USING A MANDREL OXIDATION PROCESS

Patent #:	NONE	Issue Dt:		Application #:	13757139	Filing Dt:	02/01/2013
Publication #:	US20140220756	Pub Dt:	08/07/2014
Title:	METHODS OF FORMING SEMICONDUCTOR DEVICES BY FORMING A SEMICONDUCTOR LAYER ABOVE SOURCE/DRAIN REGIONS PRIOR TO REMOVING A GATE CAP LAYER

Patent #:	9029919	Issue Dt:	05/12/2015	Application #:	13757205	Filing Dt:	02/01/2013
Publication #:	US20140217480	Pub Dt:	08/07/2014
Title:	METHODS OF FORMING SILICON/GERMANIUM PROTECTION LAYER ABOVE SOURCE/DRAIN REGIONS OF A TRANSISTOR AND A DEVICE HAVING SUCH A PROTECTION LAYER

Patent #:	8826197	Issue Dt:	09/02/2014	Application #:	13757218	Filing Dt:	02/01/2013
Publication #:	US20140223396	Pub Dt:	08/07/2014
Title:	PATTERN-BASED REPLACEMENT FOR LAYOUT REGULARIZATION

Patent #:	8975195	Issue Dt:	03/10/2015	Application #:	13757286	Filing Dt:	02/01/2013
Publication #:	US20140220786	Pub Dt:	08/07/2014
Title:	METHODS FOR OPTICAL PROXIMITY CORRECTION IN THE DESIGN AND FABRICATION OF INTEGRATED CIRCUITS

Patent #:	8835306	Issue Dt:	09/16/2014	Application #:	13757504	Filing Dt:	02/01/2013
Publication #:	US20140220775	Pub Dt:	08/07/2014
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING EMBEDDED ELECTRICAL INTERCONNECTS

Patent #:	8956945	Issue Dt:	02/17/2015	Application #:	13757961	Filing Dt:	02/04/2013
Publication #:	US20140217551	Pub Dt:	08/07/2014
Title:	TRENCH ISOLATION FOR BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY

Patent #:	8716837	Issue Dt:	05/06/2014	Application #:	13758204	Filing Dt:	02/04/2013
Publication #:	US20130147017	Pub Dt:	06/13/2013
Title:	BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES

Patent #:	9368578	Issue Dt:	06/14/2016	Application #:	13758225	Filing Dt:	02/04/2013
Publication #:	US20140217467	Pub Dt:	08/07/2014
Title:	METHODS OF FORMING SUBSTRATES COMPRISED OF DIFFERENT SEMICONDUCTOR MATERIALS AND THE RESULTING DEVICE

Patent #:	NONE	Issue Dt:		Application #:	13758382	Filing Dt:	02/04/2013
Publication #:	US20130140638	Pub Dt:	06/06/2013
Title:	HIGH DENSITY SIX TRANSISTOR FINFET SRAM CELL LAYOUT

Patent #:	8881072	Issue Dt:	11/04/2014	Application #:	13759102	Filing Dt:	02/05/2013
Publication #:	US20130152027	Pub Dt:	06/13/2013
Title:	METHOD FOR COMPENSATING FOR VARIATIONS IN STRUCTURES OF AN INTEGRATED CIRCUIT

Patent #:	8921191	Issue Dt:	12/30/2014	Application #:	13759156	Filing Dt:	02/05/2013
Publication #:	US20140217517	Pub Dt:	08/07/2014
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Title:	PAD-LESS GATE-ALL AROUND SEMICONDUCTOR NANOWIRE FETS ON BULK SEMICONDUCTOR WAFERS

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Title:	VARIABLE RESISTANCE SWITCH FOR WIDE BANDWIDTH RESONANT GLOBAL CLOCK DISTRIBUTION

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Title:	PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL

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Title:	CORROSION SENSORS

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100

Patent #:	9006087	Issue Dt:	04/14/2015	Application #:	13761476	Filing Dt:	02/07/2013
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Title:	DIODE STRUCTURE AND METHOD FOR WIRE-LAST NANOMESH TECHNOLOGIES

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

440 STONE BREAK ROAD EXTENSION

MALTA, NEW YORK 12020

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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