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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
04/18/2000
Application #:
09111815
Filing Dt:
07/08/1998
Title:
UPGRADEABLE MICROPROCESSOR AND MOTHERBOARD
2
Patent #:
Issue Dt:
08/29/2000
Application #:
09112146
Filing Dt:
07/09/1998
Title:
CONCURRENT EXECUTION OF MULTIPLE INSTRUCTIONS IN CYCLIC COUNTER BASED LOGIC COMPONENT OPERATION STAGES
3
Patent #:
Issue Dt:
12/10/2002
Application #:
09112158
Filing Dt:
07/09/1998
Title:
METHOD OF FORMING RELIABLE CAPPED COPPER INTERCONNECTS
4
Patent #:
Issue Dt:
04/03/2001
Application #:
09112161
Filing Dt:
07/09/1998
Title:
METHOD OF FORMING RELIABLE COPPER INTERCONNECTS
5
Patent #:
Issue Dt:
10/16/2001
Application #:
09112472
Filing Dt:
07/09/1998
Title:
COPPER INTERCONNECT WITH IMPROVED ELECTROMIGRATION RESISTANCE
6
Patent #:
Issue Dt:
05/18/1999
Application #:
09112529
Filing Dt:
07/08/1998
Title:
ULTRA THIN HIGH K SPACER MATERIAL FOR USE IN TRANSISTOR FABRICATION
7
Patent #:
Issue Dt:
02/06/2001
Application #:
09112919
Filing Dt:
07/09/1998
Title:
CHIP INTERCONNECT WIRING STRUCTURE WITH LOW DIELECTRIC CONSTANT INSULATOR AND METHODS FOR FABRICATING THE SAME
8
Patent #:
Issue Dt:
04/11/2000
Application #:
09113436
Filing Dt:
07/10/1998
Title:
METALORGANIC DECOMPOSITION DEPOSITION OF THIN CONDUCTIVE FILM ON INTEGRATED CIRCUITS USING REDUCING AMBIENT
9
Patent #:
Issue Dt:
11/27/2001
Application #:
09113916
Filing Dt:
07/10/1998
Title:
REFRACTORY METAL CAPPED LOW RESISTIVITY METAL CONDUCTOR LINES AND VIAS
10
Patent #:
Issue Dt:
08/29/2000
Application #:
09115123
Filing Dt:
07/14/1998
Title:
Processor Configured To Generate Lookahead Results From Operand Collapse Unit And For Inhibiting Receipt/Execution Of The First Instruction Based On The Lookahead Result
11
Patent #:
Issue Dt:
08/08/2000
Application #:
09116066
Filing Dt:
07/15/1998
Title:
FORMING A SELF-ALIGNED SILICIDE GATE CONDUCTOR TO A GREATER THICKNESS THAN JUNCTION SILICIDE STRUCTURES USING A DUAL-SALICIDATION PROCESS
12
Patent #:
Issue Dt:
08/14/2001
Application #:
09116417
Filing Dt:
07/15/1998
Title:
TRANSISTOR HAVING A NITROGEN INCORPORATED EPITAXIALLY GROWN GATE DIELECTRIC AND METHOD OF MAKING SAME
13
Patent #:
Issue Dt:
04/24/2001
Application #:
09116631
Filing Dt:
07/16/1998
Title:
METHOD AND CIRCUIT FOR PRELOADING PREDICTION CIRCUITS IN MICROPROCESSORS
14
Patent #:
Issue Dt:
08/22/2000
Application #:
09116792
Filing Dt:
07/16/1998
Title:
ACOUSTICALLY AGITATED DELIVERY
15
Patent #:
Issue Dt:
01/11/2000
Application #:
09118389
Filing Dt:
07/17/1998
Title:
IMPROVED LDD TRANSISTOR USING NOVEL GATE TRIM TECHNIQUE
16
Patent #:
Issue Dt:
07/17/2001
Application #:
09123177
Filing Dt:
07/27/1998
Title:
BURIED LOCAL INTERCONNECT
17
Patent #:
Issue Dt:
10/03/2000
Application #:
09123534
Filing Dt:
07/28/1998
Title:
COMBINED SEGMENTED AND NONSEGMENTED BAR-IN-BAR TARGETS
18
Patent #:
Issue Dt:
08/08/2000
Application #:
09123657
Filing Dt:
07/28/1998
Title:
METHOD OF MAKING ULTRA THIN GATE OXIDE USING ALUMINUM OXIDE
19
Patent #:
Issue Dt:
08/29/2000
Application #:
09123673
Filing Dt:
07/28/1998
Title:
METHOD OF INTEGRATION OF NITROGEN BEARING HIGH K FILM
20
Patent #:
Issue Dt:
06/26/2001
Application #:
09124098
Filing Dt:
07/29/1998
Title:
PREFETCH INSTRUCTION MECHANISM FOR PROCESSOR
21
Patent #:
Issue Dt:
01/02/2001
Application #:
09124604
Filing Dt:
07/29/1998
Title:
SEMICONDUCTOR DEVICE HAVING GROWN OXIDE SPACERS AND METHOD OF MANUFACTURE THEREOF
22
Patent #:
Issue Dt:
04/03/2001
Application #:
09126142
Filing Dt:
07/30/1998
Title:
INTEGRATED CIRCUIT TEST COVERAGE EVALUATION AND ADJUSTMENT MECHANISM AND METHOD
23
Patent #:
Issue Dt:
10/31/2000
Application #:
09126212
Filing Dt:
07/30/1998
Title:
DUAL DAMASCENE PROCESSING FO SEMICONDUCTOR CHIP INTERCONNECTS
24
Patent #:
Issue Dt:
05/21/2002
Application #:
09126990
Filing Dt:
07/31/1998
Title:
APPARATUS AND METHOD FOR HARDWARE IMPLEMENTATION OF A DIGITAL PHASE SHIFTER
25
Patent #:
Issue Dt:
05/08/2001
Application #:
09127094
Filing Dt:
07/31/1998
Title:
PROCESSOR CONFIGURED TO SELECTIVELY FREE PHYSICAL REGISTERS UPON RETIREMENT OF INSTRUCTIONS BASED ON WHETHER OR NOT THE PHYSICAL REGISTERS ARE STILL IN USE FOR OTHER LOGICAL REGISTERS
26
Patent #:
Issue Dt:
09/19/2000
Application #:
09127100
Filing Dt:
07/31/1998
Title:
PROCESSOR CONFIGURED TO MAP LOGICAL REGISTER NUMBERS TO PHYSICAL REGISTER NUMBERS USING VIRTUAL REGISTER NUMBERS
27
Patent #:
Issue Dt:
09/12/2000
Application #:
09127294
Filing Dt:
07/31/1998
Title:
MAP UNIT HAVING RAPID MISPREDICTION RECOVERY
28
Patent #:
Issue Dt:
01/11/2000
Application #:
09127344
Filing Dt:
07/31/1998
Title:
APPARATUS FOR AND METHOD OF CONDITIONING CHEMICAL MECHANICAL POLISHING PAD DURING WORKPIECE POLISHING CYCLE
29
Patent #:
Issue Dt:
04/09/2002
Application #:
09127503
Filing Dt:
07/31/1998
Title:
METHOD AND APPARATUS FOR HANDLING AN ESD EVENT ON AN SOI INTEGRATED CIRCUIT
30
Patent #:
Issue Dt:
06/12/2001
Application #:
09128235
Filing Dt:
08/03/1998
Title:
TRENCH AND GATE DIELECTRIC FORMATION FOR SEMICONDUCTOR DEVICES
31
Patent #:
Issue Dt:
08/21/2001
Application #:
09129103
Filing Dt:
08/04/1998
Title:
CHEMICAL MECHANICAL POLISHING ENDPOINT PROCESS CONTROL
32
Patent #:
Issue Dt:
03/11/2003
Application #:
09129703
Filing Dt:
08/05/1998
Title:
ADVANCED FRABRICATION TECHNIQUE TO FORM ULTRA THIN GATE DIELECTRIC USING A SACRIFICAL POLYSILICON SEED LAYER
33
Patent #:
Issue Dt:
05/27/2008
Application #:
09129737
Filing Dt:
08/05/1998
Title:
TRANSPARENT HARD COATS FOR OPTICAL ELEMENTS
34
Patent #:
Issue Dt:
03/07/2000
Application #:
09129827
Filing Dt:
08/05/1998
Title:
NON-VOLATILE MAGNETIC MEMORY CELL AND DEVICES
35
Patent #:
Issue Dt:
01/11/2000
Application #:
09130299
Filing Dt:
08/06/1998
Title:
DOUBLE SILICON-ON-INSULATOR DEVICE AND METHOD THEREFOR
36
Patent #:
Issue Dt:
03/19/2002
Application #:
09130509
Filing Dt:
08/06/1998
Title:
VIDEO REFRESH COMPRESSION
37
Patent #:
Issue Dt:
04/02/2002
Application #:
09130528
Filing Dt:
08/04/1998
Title:
STATISTICAL PROCESS WINDOW DESIGN METHODOLOGY
38
Patent #:
Issue Dt:
05/16/2000
Application #:
09131284
Filing Dt:
08/07/1998
Title:
DEVICE LEVEL IDENTIFICATION METHODOLOGY
39
Patent #:
Issue Dt:
12/26/2000
Application #:
09131872
Filing Dt:
08/10/1998
Title:
METHOD OF RELIABLY CAPPING COPPER INTERCONNECTS
40
Patent #:
Issue Dt:
05/09/2000
Application #:
09131919
Filing Dt:
08/10/1998
Title:
METHOD FOR MAKING MULTILAYERED COAXIAL INTERCONNECT STRUCTURE
41
Patent #:
Issue Dt:
01/09/2001
Application #:
09132282
Filing Dt:
08/11/1998
Title:
A SEMICONDUCTOR DEVICE HAVING AN INTERMETALLIC LAYER ON METAL INTERCONNECTS
42
Patent #:
Issue Dt:
12/07/1999
Application #:
09132599
Filing Dt:
08/11/1998
Title:
LOW VOLTAGE ACTIVE BODY SEMICONDUCTOR DEVICE
43
Patent #:
Issue Dt:
12/19/2000
Application #:
09132803
Filing Dt:
08/13/1998
Title:
CMOS TRI-STATE CONTROL CIRCUIT FOR A BIDIRECTIONAL I/O WITH SLEW RATE CONTROL
44
Patent #:
Issue Dt:
01/01/2002
Application #:
09132944
Filing Dt:
08/11/1998
Title:
METHOD AND SYSTEM FOR PROVIDING A RESIZE LAYOUT ALLOWING FLEXIBLE PLACEMENT AND SIZING OF CONTROLS
45
Patent #:
Issue Dt:
05/01/2001
Application #:
09132980
Filing Dt:
08/12/1998
Title:
MODIFYING A DESIGN LAYER OF AN INTEGRATED CIRCUIT USING OVERLYING AND UNDERLYING DESIGN LAYERS
46
Patent #:
Issue Dt:
01/09/2001
Application #:
09135493
Filing Dt:
08/17/1998
Title:
MECHANISM TO DETERMINE ACTUAL CODE EXECUTION FLOW IN A COMPUTER
47
Patent #:
Issue Dt:
10/26/1999
Application #:
09135663
Filing Dt:
08/18/1998
Title:
MULTI-LAYER CERAMIC SUBSTRATE DECOUPLING
48
Patent #:
Issue Dt:
05/28/2002
Application #:
09135825
Filing Dt:
08/18/1998
Title:
SIMULATION BASED POWER OPTIMIZATION
49
Patent #:
Issue Dt:
10/31/2000
Application #:
09135826
Filing Dt:
08/18/1998
Title:
HIGH PERFORMANCE MOSFET AND METHOD OF FORMING THE SAME USING SALICIDATION AND JUNCTION IMPLANTATION PRIOR TO GATE FORMATION
50
Patent #:
Issue Dt:
02/27/2001
Application #:
09136585
Filing Dt:
08/19/1998
Title:
RECEPTOR PAD STRUCTURE FOR CHIP CARRIERS
51
Patent #:
Issue Dt:
01/16/2001
Application #:
09137275
Filing Dt:
08/20/1998
Title:
METHOD OF MAKING HIGH PERFORMANCE MOSFET WITH POLISHED GATE AND SOURCE/DRAIN FEATURE
52
Patent #:
Issue Dt:
05/07/2002
Application #:
09137570
Filing Dt:
08/21/1998
Title:
METHOD TO DYNAMICALY CHANGE MICROPROCESSOR TEST SOFTWARE TO REFLECT DIFFERENT SILICON REVISION LEVELS
53
Patent #:
Issue Dt:
02/06/2001
Application #:
09137579
Filing Dt:
08/21/1998
Title:
BASIC BLOCK ORIENTED TRACE CACHE UTILIZING A BASIC BLOCK SEQUENCE BUFFER TO INDICATE PROGRAM ORDER OF CACHED BASIC BLOCKS
54
Patent #:
Issue Dt:
01/16/2001
Application #:
09137583
Filing Dt:
08/21/1998
Title:
METHOD AND APPARATUS FOR CONCURRENTLY EXECUTING MULTIPLICATION AND ITERATIVE OPERATIONS
55
Patent #:
Issue Dt:
04/03/2001
Application #:
09138886
Filing Dt:
08/24/1998
Title:
MECHANISM FOR LOAD BLOCK ON STORE ADDRESS GENERATION
56
Patent #:
Issue Dt:
09/28/1999
Application #:
09138989
Filing Dt:
08/24/1998
Title:
REDUCTION OF DOPANT DIFFUSION BY THE CO-IMPLANTATION OF IMPURITIES INTO THE TRANSISTOR GATE CONDUCTOR
57
Patent #:
Issue Dt:
09/19/2000
Application #:
09139056
Filing Dt:
08/24/1998
Title:
SYMMETRICAL INSTRUCTIONS QUEUE FOR HIGH CLOCK FREQUENCY SCHEDULING
58
Patent #:
Issue Dt:
04/03/2001
Application #:
09139178
Filing Dt:
08/24/1998
Title:
UNIVERSAL DEPENDENCY VECTOR/QUEUE ENTRY
59
Patent #:
Issue Dt:
05/09/2000
Application #:
09139570
Filing Dt:
08/25/1998
Title:
GEOMETRIC PHASE ANALYSIS FOR MASK ALLIGNMENT
60
Patent #:
Issue Dt:
04/03/2001
Application #:
09139584
Filing Dt:
08/25/1998
Title:
METHOD FOR ENABLING AND CONFIGURING AN AGP CHIPSET CACHE USING A REGISTRY
61
Patent #:
Issue Dt:
07/31/2001
Application #:
09139870
Filing Dt:
08/25/1998
Title:
ERROR REPORTING MECHANISM FOR AN AGP CHIPSET DRIVER USING A REGISTRY
62
Patent #:
Issue Dt:
03/28/2000
Application #:
09140202
Filing Dt:
08/26/1998
Title:
SEMICONDUCTOR GATE CONDUCTOR WITH A SUBSTANTIALLY UNIFORM DOPING PROFILE HAVING MINIMAL SUSCEPTIBILITY TO DOPANT PENETRATION INTO THE UNDERLYING GATE DIELECTRIC
63
Patent #:
Issue Dt:
07/04/2000
Application #:
09140602
Filing Dt:
08/26/1998
Title:
START-UP CIRCUIT FOR WRITE SELECTS AND EQUILIBRATES
64
Patent #:
Issue Dt:
12/03/2002
Application #:
09140640
Filing Dt:
08/26/1998
Title:
APPARATUS AND METHOD FOR EQUALIZING RECEIVED NETWORK SIGNALS USING A SINGLE ZERO HIGH-PASS FILTER HAVING SELECTABLE IMPEDANCE
65
Patent #:
Issue Dt:
11/21/2000
Application #:
09140833
Filing Dt:
08/26/1998
Title:
APPARATUS AND METHOD FOR EQUALIZING RECEIVED NETWORK SIGNALS USING A TRANSCONDUCTANCE CONTROLLED SINGLE ZERO SINGLE POLE FILTER
66
Patent #:
Issue Dt:
10/03/2000
Application #:
09143105
Filing Dt:
08/28/1998
Title:
INTERCONNECT STRUCTURE WITH LOW K DIELECTRIC MATERIALS AND METHOD OF MAKING THE SAME WITH SINGLE AND DUAL DAMASCENE TECHNIQUES
67
Patent #:
Issue Dt:
06/20/2000
Application #:
09143196
Filing Dt:
08/31/1998
Title:
SPRING LOADED HEAT PIPE CONNECTOR FOR HINGED APPARATUS PACKAGE
68
Patent #:
Issue Dt:
06/05/2001
Application #:
09144067
Filing Dt:
08/31/1998
Title:
DIODE CONNECTED TO A MAGNETIC TUNNEL JUNCTION AND SELF ALIGNED WITH A METALLIC CONDUCTOR AND METHOD OF FORMING THE SAME
69
Patent #:
Issue Dt:
05/23/2000
Application #:
09144319
Filing Dt:
08/31/1998
Title:
CORE SECTION HAVING ASYNCHRONOUS PARTIAL RESET
70
Patent #:
Issue Dt:
12/12/2000
Application #:
09146163
Filing Dt:
09/03/1998
Title:
NETWORK INTERFACE DEVICE ARCHITECTURE FOR STORING TRANSMIT AND RECEIVE DATA IN A RANDOM ACCESS BUFFER MEMORY ACROSS INDEPENDENT CLOCK DOMAINS
71
Patent #:
Issue Dt:
11/28/2000
Application #:
09146168
Filing Dt:
09/03/1998
Title:
SELECTIVELY STORING STATUS INFORMATION ASSOCIATED WITH A DATA FRAME IN A HOLDING REGISTER BASED ON AN ASYNCHRONOUS DETERMING STOP
72
Patent #:
Issue Dt:
11/07/2000
Application #:
09146251
Filing Dt:
09/03/1998
Title:
SYSTEM FOR TRANSFERRING FRAME DATA BY TRANSFERRING THE DESCRIPTOR INDEX DATA TO IDENTIFY A SPECIFIED AMOUNT OF DATA TO BE TRANSFERRED STORED IN THE HOST COMPUTER
73
Patent #:
Issue Dt:
01/30/2001
Application #:
09146713
Filing Dt:
09/03/1998
Title:
MULTIPLE PIXEL DRIVEN MIRROR ELECTRODES FOR IMPROVED APERTURE RATIO OF REFLECTIVE DISPLAYS
74
Patent #:
Issue Dt:
07/11/2000
Application #:
09146867
Filing Dt:
09/03/1998
Title:
SILSESQUIOXANE POLYMERS, METHOD OF SYNTHESIS, PHOTORESIST COMPOSITION, AND MULTILAYER LITHOGRAPHIC METHOD
75
Patent #:
Issue Dt:
08/22/2000
Application #:
09148095
Filing Dt:
09/04/1998
Title:
METHOD OF MAKING HIGH PERFORMANCE TRANSISTORS USING CHANNEL MODULATED IMPLANT FOR ULTRA THIN OXIDE FORMATION
76
Patent #:
Issue Dt:
10/23/2001
Application #:
09148193
Filing Dt:
09/04/1998
Title:
BUMP SCRUB AFTER PLATING
77
Patent #:
Issue Dt:
08/28/2001
Application #:
09148918
Filing Dt:
09/04/1998
Title:
PROCESS OF MANUFACTURING SILICON-ON-INSULATOR CHIP HAVING AN ISOLATION BARRIER FOR RELIABILITY
78
Patent #:
Issue Dt:
04/20/2004
Application #:
09148923
Filing Dt:
09/04/1998
Title:
SYSTEM-ON-A-CHIP WITH VARIABLE BANDWIDTH
79
Patent #:
Issue Dt:
03/07/2000
Application #:
09149208
Filing Dt:
09/08/1998
Title:
SCALED INTERCONNECT ANODIZATION FOR HIGH FREQUENCY APPLICATIONS
80
Patent #:
Issue Dt:
10/03/2000
Application #:
09149398
Filing Dt:
09/08/1998
Title:
SEMICONDUCTOR DEVICE WITH A REDUCED WIDTH GATE DIELECTRIC AND METHOD OF MAKING SAME
81
Patent #:
Issue Dt:
02/20/2001
Application #:
09150874
Filing Dt:
09/10/1998
Title:
METHOD OF TILTED IMPLANT FOR POCKET, HALO AND SOURCE/DRAIN EXTENSION IN ULSI DENSE STRUCTURES
82
Patent #:
Issue Dt:
01/09/2001
Application #:
09151861
Filing Dt:
09/11/1998
Title:
IMPLEMENTATION OF THE AGP REQUEST QUEUES USING FIFOS
83
Patent #:
Issue Dt:
01/01/2002
Application #:
09152043
Filing Dt:
09/11/1998
Title:
RISC86 INSTRUCTION SET
84
Patent #:
Issue Dt:
05/22/2001
Application #:
09152748
Filing Dt:
09/14/1998
Title:
A NETWORK INTERFACE UNIT INCLUDING A MICROCONTROLLER HAVING MULTIPLE CONFIGURABLE LOGIC BLOCKS WITH A TEST/PROGRAM BUS FOR PERFORMING A PLURALITY OF SELECTED FUNCTIONS
85
Patent #:
Issue Dt:
08/13/2002
Application #:
09153753
Filing Dt:
09/15/1998
Title:
SEMICONDUCTOR FABRICATION EMPLOYING BARRIER ATOMS INCORPORATED AT THE EDGES OF A TRENCH ISOLATION STRUCTURE
86
Patent #:
Issue Dt:
01/11/2000
Application #:
09153770
Filing Dt:
09/15/1998
Title:
SUPERSCALAR MICROPROCESSOR CONFIGURED TO PREDICT RETURN ADDRESSES FROM A RETURN STACK STORAGE
87
Patent #:
Issue Dt:
01/13/2004
Application #:
09153807
Filing Dt:
09/15/1998
Title:
IMPROVING THE ELECTROMIGRATION CHARACTERISTICS OF PATTERNED METAL FEATURES IN SEMICONDUCTOR DEVICES
88
Patent #:
Issue Dt:
08/03/1999
Application #:
09153985
Filing Dt:
09/16/1998
Title:
MICROFABRICATED MAGNETIC PARTICLES FOR APPLICATIONS TO AFFINITY BINDING
89
Patent #:
Issue Dt:
05/01/2001
Application #:
09154114
Filing Dt:
09/16/1998
Title:
REFLECTIVE ELECTROPHORETIC DISPLAY WITH LATERALLY ADJACENT COLOR CELLS USING AN ABSORBING PANEL
90
Patent #:
Issue Dt:
08/07/2001
Application #:
09154284
Filing Dt:
09/16/1998
Title:
REFLECTIVE ELECTROPHORETIC DISPLAY WITH LATERALLY ADJACENT COLOR CELLS USING A REFLECTIVE PANEL
91
Patent #:
Issue Dt:
01/23/2001
Application #:
09156069
Filing Dt:
09/17/1998
Title:
METHOD AND SYSTEM FOR DETERMINING CRITICAL AREA FOR CIRCUIT LAYOUTS
92
Patent #:
Issue Dt:
06/12/2001
Application #:
09157012
Filing Dt:
09/18/1998
Title:
SPUTTERED TUNGSTEN DIFFUSION BARRIER FOR IMPROVED INTERCONNECT ROBUSTNESS
93
Patent #:
Issue Dt:
11/30/1999
Application #:
09157240
Filing Dt:
09/18/1998
Title:
SURFACE TREATMENT OF LOW-K SIOF TO PREVENT METAL INTERACTION
94
Patent #:
Issue Dt:
02/20/2001
Application #:
09157626
Filing Dt:
09/21/1998
Title:
USING MULTIPLE DECODERS AND A REORDER QUEUE TO DECODE INSTRUCTIONS OUT OF ORDER
95
Patent #:
Issue Dt:
10/31/2000
Application #:
09157627
Filing Dt:
09/21/1998
Title:
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED METAL-CONTAINING GATE
96
Patent #:
Issue Dt:
10/01/2002
Application #:
09157648
Filing Dt:
09/21/1998
Title:
USING SEPARATE CACHES FOR VARIABLE AND GENERATED FIXED-LENGTH INSTRUCTIONS
97
Patent #:
Issue Dt:
04/04/2000
Application #:
09157708
Filing Dt:
09/21/1998
Title:
OUTPUT BUFFER INCLUDING AN APPLICATION-SPECIFIC SRAM MEMORY CELL FOR LOW VOLTAGE, HIGH SPEED OPERATION
98
Patent #:
Issue Dt:
06/26/2001
Application #:
09157719
Filing Dt:
09/21/1998
Title:
FORCING REGULARITY INTO A CISC INSTRUCTION SET BY PADDING INSTRUCTIONS
99
Patent #:
Issue Dt:
10/31/2000
Application #:
09158465
Filing Dt:
09/22/1998
Title:
SYSTEM FOR STORE TO LOAD FORWARDING OF INDIVIDUAL BYTES FROM SEPARATE STORE BUFFER ENTRIES TO FORM A SINGLE LOAD WORD
100
Patent #:
Issue Dt:
09/28/1999
Application #:
09159307
Filing Dt:
09/23/1998
Title:
DEVICE DESIGN FOR ENHANCED AVALANCHE SOI CMOS
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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