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04/18/2000
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09111815
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07/08/1998
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UPGRADEABLE MICROPROCESSOR AND MOTHERBOARD
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08/29/2000
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09112146
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07/09/1998
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12/10/2002
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07/09/1998
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04/03/2001
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09112161
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07/09/1998
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10/16/2001
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09112472
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07/09/1998
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05/18/1999
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07/08/1998
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02/06/2001
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09112919
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07/09/1998
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CHIP INTERCONNECT WIRING STRUCTURE WITH LOW DIELECTRIC CONSTANT INSULATOR AND METHODS FOR FABRICATING THE SAME
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04/11/2000
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09113436
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07/10/1998
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METALORGANIC DECOMPOSITION DEPOSITION OF THIN CONDUCTIVE FILM ON INTEGRATED CIRCUITS USING REDUCING AMBIENT
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11/27/2001
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07/10/1998
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REFRACTORY METAL CAPPED LOW RESISTIVITY METAL CONDUCTOR LINES AND VIAS
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08/29/2000
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07/14/1998
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08/08/2000
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09116066
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07/15/1998
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FORMING A SELF-ALIGNED SILICIDE GATE CONDUCTOR TO A GREATER THICKNESS THAN JUNCTION SILICIDE STRUCTURES USING A DUAL-SALICIDATION PROCESS
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08/14/2001
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09116417
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07/15/1998
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TRANSISTOR HAVING A NITROGEN INCORPORATED EPITAXIALLY GROWN GATE DIELECTRIC AND METHOD OF MAKING SAME
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04/24/2001
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09116631
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07/16/1998
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METHOD AND CIRCUIT FOR PRELOADING PREDICTION CIRCUITS IN MICROPROCESSORS
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08/22/2000
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09116792
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07/16/1998
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01/11/2000
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07/17/1998
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IMPROVED LDD TRANSISTOR USING NOVEL GATE TRIM TECHNIQUE
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07/17/2001
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09123177
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07/27/1998
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BURIED LOCAL INTERCONNECT
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10/03/2000
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09123534
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07/28/1998
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COMBINED SEGMENTED AND NONSEGMENTED BAR-IN-BAR TARGETS
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08/08/2000
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09123657
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07/28/1998
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METHOD OF MAKING ULTRA THIN GATE OXIDE USING ALUMINUM OXIDE
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08/29/2000
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09123673
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07/28/1998
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METHOD OF INTEGRATION OF NITROGEN BEARING HIGH K FILM
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06/26/2001
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09124098
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07/29/1998
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PREFETCH INSTRUCTION MECHANISM FOR PROCESSOR
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01/02/2001
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09124604
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07/29/1998
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SEMICONDUCTOR DEVICE HAVING GROWN OXIDE SPACERS AND METHOD OF MANUFACTURE THEREOF
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04/03/2001
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09126142
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07/30/1998
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INTEGRATED CIRCUIT TEST COVERAGE EVALUATION AND ADJUSTMENT MECHANISM AND METHOD
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10/31/2000
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09126212
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07/30/1998
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DUAL DAMASCENE PROCESSING FO SEMICONDUCTOR CHIP INTERCONNECTS
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05/21/2002
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09126990
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07/31/1998
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APPARATUS AND METHOD FOR HARDWARE IMPLEMENTATION OF A DIGITAL PHASE SHIFTER
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05/08/2001
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09127094
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07/31/1998
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Title:
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PROCESSOR CONFIGURED TO SELECTIVELY FREE PHYSICAL REGISTERS UPON RETIREMENT OF INSTRUCTIONS BASED ON WHETHER OR NOT THE PHYSICAL REGISTERS ARE STILL IN USE FOR OTHER LOGICAL REGISTERS
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09/19/2000
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09127100
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07/31/1998
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Title:
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PROCESSOR CONFIGURED TO MAP LOGICAL REGISTER NUMBERS TO PHYSICAL REGISTER NUMBERS USING VIRTUAL REGISTER NUMBERS
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09/12/2000
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09127294
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07/31/1998
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Title:
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MAP UNIT HAVING RAPID MISPREDICTION RECOVERY
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01/11/2000
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09127344
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07/31/1998
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Title:
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APPARATUS FOR AND METHOD OF CONDITIONING CHEMICAL MECHANICAL POLISHING PAD DURING WORKPIECE POLISHING CYCLE
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04/09/2002
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09127503
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07/31/1998
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Title:
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METHOD AND APPARATUS FOR HANDLING AN ESD EVENT ON AN SOI INTEGRATED CIRCUIT
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06/12/2001
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09128235
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08/03/1998
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TRENCH AND GATE DIELECTRIC FORMATION FOR SEMICONDUCTOR DEVICES
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08/21/2001
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09129103
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08/04/1998
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CHEMICAL MECHANICAL POLISHING ENDPOINT PROCESS CONTROL
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03/11/2003
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09129703
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08/05/1998
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ADVANCED FRABRICATION TECHNIQUE TO FORM ULTRA THIN GATE DIELECTRIC USING A SACRIFICAL POLYSILICON SEED LAYER
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05/27/2008
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09129737
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08/05/1998
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TRANSPARENT HARD COATS FOR OPTICAL ELEMENTS
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03/07/2000
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09129827
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08/05/1998
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NON-VOLATILE MAGNETIC MEMORY CELL AND DEVICES
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01/11/2000
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09130299
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08/06/1998
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DOUBLE SILICON-ON-INSULATOR DEVICE AND METHOD THEREFOR
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03/19/2002
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09130509
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08/06/1998
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Title:
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VIDEO REFRESH COMPRESSION
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04/02/2002
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09130528
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08/04/1998
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Title:
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STATISTICAL PROCESS WINDOW DESIGN METHODOLOGY
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05/16/2000
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09131284
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08/07/1998
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DEVICE LEVEL IDENTIFICATION METHODOLOGY
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12/26/2000
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09131872
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08/10/1998
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METHOD OF RELIABLY CAPPING COPPER INTERCONNECTS
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05/09/2000
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09131919
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08/10/1998
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METHOD FOR MAKING MULTILAYERED COAXIAL INTERCONNECT STRUCTURE
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01/09/2001
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09132282
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08/11/1998
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Title:
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A SEMICONDUCTOR DEVICE HAVING AN INTERMETALLIC LAYER ON METAL INTERCONNECTS
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12/07/1999
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09132599
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08/11/1998
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LOW VOLTAGE ACTIVE BODY SEMICONDUCTOR DEVICE
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12/19/2000
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09132803
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08/13/1998
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CMOS TRI-STATE CONTROL CIRCUIT FOR A BIDIRECTIONAL I/O WITH SLEW RATE CONTROL
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01/01/2002
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09132944
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08/11/1998
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METHOD AND SYSTEM FOR PROVIDING A RESIZE LAYOUT ALLOWING FLEXIBLE PLACEMENT AND SIZING OF CONTROLS
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05/01/2001
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09132980
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08/12/1998
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Title:
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MODIFYING A DESIGN LAYER OF AN INTEGRATED CIRCUIT USING OVERLYING AND UNDERLYING DESIGN LAYERS
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01/09/2001
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09135493
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08/17/1998
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Title:
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MECHANISM TO DETERMINE ACTUAL CODE EXECUTION FLOW IN A COMPUTER
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10/26/1999
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09135663
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08/18/1998
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Title:
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MULTI-LAYER CERAMIC SUBSTRATE DECOUPLING
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05/28/2002
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09135825
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08/18/1998
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Title:
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SIMULATION BASED POWER OPTIMIZATION
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Issue Dt:
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10/31/2000
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09135826
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Filing Dt:
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08/18/1998
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Title:
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HIGH PERFORMANCE MOSFET AND METHOD OF FORMING THE SAME USING SALICIDATION AND JUNCTION IMPLANTATION PRIOR TO GATE FORMATION
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02/27/2001
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09136585
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08/19/1998
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Title:
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RECEPTOR PAD STRUCTURE FOR CHIP CARRIERS
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01/16/2001
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09137275
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08/20/1998
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Title:
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METHOD OF MAKING HIGH PERFORMANCE MOSFET WITH POLISHED GATE AND SOURCE/DRAIN FEATURE
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05/07/2002
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09137570
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08/21/1998
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METHOD TO DYNAMICALY CHANGE MICROPROCESSOR TEST SOFTWARE TO REFLECT DIFFERENT SILICON REVISION LEVELS
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02/06/2001
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09137579
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Filing Dt:
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08/21/1998
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Title:
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BASIC BLOCK ORIENTED TRACE CACHE UTILIZING A BASIC BLOCK SEQUENCE BUFFER TO INDICATE PROGRAM ORDER OF CACHED BASIC BLOCKS
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Issue Dt:
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01/16/2001
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09137583
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08/21/1998
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Title:
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METHOD AND APPARATUS FOR CONCURRENTLY EXECUTING MULTIPLICATION AND ITERATIVE OPERATIONS
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04/03/2001
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09138886
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08/24/1998
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Title:
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MECHANISM FOR LOAD BLOCK ON STORE ADDRESS GENERATION
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Issue Dt:
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09/28/1999
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09138989
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08/24/1998
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Title:
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REDUCTION OF DOPANT DIFFUSION BY THE CO-IMPLANTATION OF IMPURITIES INTO THE TRANSISTOR GATE CONDUCTOR
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Issue Dt:
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09/19/2000
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09139056
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08/24/1998
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Title:
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SYMMETRICAL INSTRUCTIONS QUEUE FOR HIGH CLOCK FREQUENCY SCHEDULING
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Issue Dt:
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04/03/2001
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09139178
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08/24/1998
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Title:
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UNIVERSAL DEPENDENCY VECTOR/QUEUE ENTRY
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Issue Dt:
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05/09/2000
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09139570
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Filing Dt:
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08/25/1998
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Title:
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GEOMETRIC PHASE ANALYSIS FOR MASK ALLIGNMENT
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Issue Dt:
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04/03/2001
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09139584
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08/25/1998
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Title:
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METHOD FOR ENABLING AND CONFIGURING AN AGP CHIPSET CACHE USING A REGISTRY
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Issue Dt:
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07/31/2001
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09139870
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Filing Dt:
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08/25/1998
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Title:
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ERROR REPORTING MECHANISM FOR AN AGP CHIPSET DRIVER USING A REGISTRY
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Issue Dt:
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03/28/2000
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09140202
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Filing Dt:
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08/26/1998
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Title:
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SEMICONDUCTOR GATE CONDUCTOR WITH A SUBSTANTIALLY UNIFORM DOPING PROFILE HAVING MINIMAL SUSCEPTIBILITY TO DOPANT PENETRATION INTO THE UNDERLYING GATE DIELECTRIC
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Issue Dt:
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07/04/2000
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09140602
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08/26/1998
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Title:
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START-UP CIRCUIT FOR WRITE SELECTS AND EQUILIBRATES
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Issue Dt:
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12/03/2002
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09140640
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Filing Dt:
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08/26/1998
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Title:
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APPARATUS AND METHOD FOR EQUALIZING RECEIVED NETWORK SIGNALS USING A SINGLE ZERO HIGH-PASS FILTER HAVING SELECTABLE IMPEDANCE
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Issue Dt:
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11/21/2000
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09140833
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Filing Dt:
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08/26/1998
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Title:
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APPARATUS AND METHOD FOR EQUALIZING RECEIVED NETWORK SIGNALS USING A TRANSCONDUCTANCE CONTROLLED SINGLE ZERO SINGLE POLE FILTER
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09143105
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Filing Dt:
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08/28/1998
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Title:
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INTERCONNECT STRUCTURE WITH LOW K DIELECTRIC MATERIALS AND METHOD OF MAKING THE SAME WITH SINGLE AND DUAL DAMASCENE TECHNIQUES
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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09143196
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Filing Dt:
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08/31/1998
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Title:
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SPRING LOADED HEAT PIPE CONNECTOR FOR HINGED APPARATUS PACKAGE
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Patent #:
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Issue Dt:
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06/05/2001
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09144067
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Filing Dt:
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08/31/1998
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Title:
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DIODE CONNECTED TO A MAGNETIC TUNNEL JUNCTION AND SELF ALIGNED WITH A METALLIC CONDUCTOR AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09144319
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Filing Dt:
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08/31/1998
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Title:
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CORE SECTION HAVING ASYNCHRONOUS PARTIAL RESET
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Issue Dt:
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12/12/2000
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09146163
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Filing Dt:
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09/03/1998
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Title:
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NETWORK INTERFACE DEVICE ARCHITECTURE FOR STORING TRANSMIT AND RECEIVE DATA IN A RANDOM ACCESS BUFFER MEMORY ACROSS INDEPENDENT CLOCK DOMAINS
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09146168
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Filing Dt:
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09/03/1998
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Title:
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SELECTIVELY STORING STATUS INFORMATION ASSOCIATED WITH A DATA FRAME IN A HOLDING REGISTER BASED ON AN ASYNCHRONOUS DETERMING STOP
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09146251
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Filing Dt:
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09/03/1998
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Title:
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SYSTEM FOR TRANSFERRING FRAME DATA BY TRANSFERRING THE DESCRIPTOR INDEX DATA TO IDENTIFY A SPECIFIED AMOUNT OF DATA TO BE TRANSFERRED STORED IN THE HOST COMPUTER
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09146713
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Filing Dt:
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09/03/1998
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Title:
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MULTIPLE PIXEL DRIVEN MIRROR ELECTRODES FOR IMPROVED APERTURE RATIO OF REFLECTIVE DISPLAYS
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Issue Dt:
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07/11/2000
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Application #:
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09146867
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Filing Dt:
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09/03/1998
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Title:
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SILSESQUIOXANE POLYMERS, METHOD OF SYNTHESIS, PHOTORESIST COMPOSITION, AND MULTILAYER LITHOGRAPHIC METHOD
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Patent #:
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Issue Dt:
|
08/22/2000
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Application #:
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09148095
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Filing Dt:
|
09/04/1998
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Title:
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METHOD OF MAKING HIGH PERFORMANCE TRANSISTORS USING CHANNEL MODULATED IMPLANT FOR ULTRA THIN OXIDE FORMATION
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Patent #:
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Issue Dt:
|
10/23/2001
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Application #:
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09148193
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Filing Dt:
|
09/04/1998
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Title:
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BUMP SCRUB AFTER PLATING
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Patent #:
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|
Issue Dt:
|
08/28/2001
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Application #:
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09148918
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Filing Dt:
|
09/04/1998
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Title:
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PROCESS OF MANUFACTURING SILICON-ON-INSULATOR CHIP HAVING AN ISOLATION BARRIER FOR RELIABILITY
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Patent #:
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Issue Dt:
|
04/20/2004
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Application #:
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09148923
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Filing Dt:
|
09/04/1998
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Title:
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SYSTEM-ON-A-CHIP WITH VARIABLE BANDWIDTH
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Patent #:
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|
Issue Dt:
|
03/07/2000
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Application #:
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09149208
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Filing Dt:
|
09/08/1998
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Title:
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SCALED INTERCONNECT ANODIZATION FOR HIGH FREQUENCY APPLICATIONS
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|
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Patent #:
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|
Issue Dt:
|
10/03/2000
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Application #:
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09149398
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Filing Dt:
|
09/08/1998
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Title:
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SEMICONDUCTOR DEVICE WITH A REDUCED WIDTH GATE DIELECTRIC AND METHOD OF MAKING SAME
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|
Patent #:
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|
Issue Dt:
|
02/20/2001
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Application #:
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09150874
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Filing Dt:
|
09/10/1998
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Title:
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METHOD OF TILTED IMPLANT FOR POCKET, HALO AND SOURCE/DRAIN EXTENSION IN ULSI DENSE STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
01/09/2001
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Application #:
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09151861
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Filing Dt:
|
09/11/1998
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Title:
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IMPLEMENTATION OF THE AGP REQUEST QUEUES USING FIFOS
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|
|
Patent #:
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|
Issue Dt:
|
01/01/2002
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Application #:
|
09152043
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Filing Dt:
|
09/11/1998
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Title:
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RISC86 INSTRUCTION SET
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|
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Patent #:
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|
Issue Dt:
|
05/22/2001
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Application #:
|
09152748
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Filing Dt:
|
09/14/1998
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Title:
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A NETWORK INTERFACE UNIT INCLUDING A MICROCONTROLLER HAVING MULTIPLE CONFIGURABLE LOGIC BLOCKS WITH A TEST/PROGRAM BUS FOR PERFORMING A PLURALITY OF SELECTED FUNCTIONS
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|
|
Patent #:
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|
Issue Dt:
|
08/13/2002
|
Application #:
|
09153753
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Filing Dt:
|
09/15/1998
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Title:
|
SEMICONDUCTOR FABRICATION EMPLOYING BARRIER ATOMS INCORPORATED AT THE EDGES OF A TRENCH ISOLATION STRUCTURE
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|
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Patent #:
|
|
Issue Dt:
|
01/11/2000
|
Application #:
|
09153770
|
Filing Dt:
|
09/15/1998
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Title:
|
SUPERSCALAR MICROPROCESSOR CONFIGURED TO PREDICT RETURN ADDRESSES FROM A RETURN STACK STORAGE
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|
|
Patent #:
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|
Issue Dt:
|
01/13/2004
|
Application #:
|
09153807
|
Filing Dt:
|
09/15/1998
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Title:
|
IMPROVING THE ELECTROMIGRATION CHARACTERISTICS OF PATTERNED METAL FEATURES IN SEMICONDUCTOR DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
08/03/1999
|
Application #:
|
09153985
|
Filing Dt:
|
09/16/1998
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Title:
|
MICROFABRICATED MAGNETIC PARTICLES FOR APPLICATIONS TO AFFINITY BINDING
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|
|
Patent #:
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|
Issue Dt:
|
05/01/2001
|
Application #:
|
09154114
|
Filing Dt:
|
09/16/1998
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Title:
|
REFLECTIVE ELECTROPHORETIC DISPLAY WITH LATERALLY ADJACENT COLOR CELLS USING AN ABSORBING PANEL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09154284
|
Filing Dt:
|
09/16/1998
|
Title:
|
REFLECTIVE ELECTROPHORETIC DISPLAY WITH LATERALLY ADJACENT COLOR CELLS USING A REFLECTIVE PANEL
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|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09156069
|
Filing Dt:
|
09/17/1998
|
Title:
|
METHOD AND SYSTEM FOR DETERMINING CRITICAL AREA FOR CIRCUIT LAYOUTS
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|
|
Patent #:
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|
Issue Dt:
|
06/12/2001
|
Application #:
|
09157012
|
Filing Dt:
|
09/18/1998
|
Title:
|
SPUTTERED TUNGSTEN DIFFUSION BARRIER FOR IMPROVED INTERCONNECT ROBUSTNESS
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|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
09157240
|
Filing Dt:
|
09/18/1998
|
Title:
|
SURFACE TREATMENT OF LOW-K SIOF TO PREVENT METAL INTERACTION
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|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09157626
|
Filing Dt:
|
09/21/1998
|
Title:
|
USING MULTIPLE DECODERS AND A REORDER QUEUE TO DECODE INSTRUCTIONS OUT OF ORDER
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|
|
Patent #:
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|
Issue Dt:
|
10/31/2000
|
Application #:
|
09157627
|
Filing Dt:
|
09/21/1998
|
Title:
|
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED METAL-CONTAINING GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09157648
|
Filing Dt:
|
09/21/1998
|
Title:
|
USING SEPARATE CACHES FOR VARIABLE AND GENERATED FIXED-LENGTH INSTRUCTIONS
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|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
09157708
|
Filing Dt:
|
09/21/1998
|
Title:
|
OUTPUT BUFFER INCLUDING AN APPLICATION-SPECIFIC SRAM MEMORY CELL FOR LOW VOLTAGE, HIGH SPEED OPERATION
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|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09157719
|
Filing Dt:
|
09/21/1998
|
Title:
|
FORCING REGULARITY INTO A CISC INSTRUCTION SET BY PADDING INSTRUCTIONS
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|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09158465
|
Filing Dt:
|
09/22/1998
|
Title:
|
SYSTEM FOR STORE TO LOAD FORWARDING OF INDIVIDUAL BYTES FROM SEPARATE STORE BUFFER ENTRIES TO FORM A SINGLE LOAD WORD
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|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
09159307
|
Filing Dt:
|
09/23/1998
|
Title:
|
DEVICE DESIGN FOR ENHANCED AVALANCHE SOI CMOS
|
|