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Reel/Frame:	056987/0001			Pages:	1045
		Recorded:	05/12/2021
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 18026
Page 141 of 181
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Patent #:	NONE	Issue Dt:		Application #:	14197686	Filing Dt:	03/05/2014
Publication #:	US20150255555	Pub Dt:	09/10/2015
Title:	METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY DEVICE

Patent #:	8872274	Issue Dt:	10/28/2014	Application #:	14197762	Filing Dt:	03/05/2014
Publication #:	US20140183637	Pub Dt:	07/03/2014
Title:	STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN

Patent #:	9478509	Issue Dt:	10/25/2016	Application #:	14198711	Filing Dt:	03/06/2014
Publication #:	US20150255410	Pub Dt:	09/10/2015
Title:	MECHANICALLY ANCHORED BACKSIDE C4 PAD

Patent #:	9171935	Issue Dt:	10/27/2015	Application #:	14200104	Filing Dt:	03/07/2014
Publication #:	US20150255569	Pub Dt:	09/10/2015
Title:	FINFET FORMATION WITH LATE FIN REVEAL

Patent #:	9312145	Issue Dt:	04/12/2016	Application #:	14200197	Filing Dt:	03/07/2014
Publication #:	US20150255277	Pub Dt:	09/10/2015
Title:	CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS

Patent #:	9412822	Issue Dt:	08/09/2016	Application #:	14200737	Filing Dt:	03/07/2014
Publication #:	US20150255542	Pub Dt:	09/10/2015
Title:	METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9082698	Issue Dt:	07/14/2015	Application #:	14201122	Filing Dt:	03/07/2014
Title:	METHODS TO IMPROVE FINFET SEMICONDUCTOR DEVICE BEHAVIOR USING CO-IMPLANTATION UNDER THE CHANNEL REGION

Patent #:	9236299	Issue Dt:	01/12/2016	Application #:	14201255	Filing Dt:	03/07/2014
Publication #:	US20150255339	Pub Dt:	09/10/2015
Title:	METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE

Patent #:	9214385	Issue Dt:	12/15/2015	Application #:	14202067	Filing Dt:	03/10/2014
Publication #:	US20140183757	Pub Dt:	07/03/2014
Title:	SEMICONDUCTOR DEVICE INCLUDING PASSIVATION LAYER ENCAPSULANT

Patent #:	9123785	Issue Dt:	09/01/2015	Application #:	14202268	Filing Dt:	03/10/2014
Publication #:	US20150255340	Pub Dt:	09/10/2015
Title:	METHOD TO ETCH CU/TA/TAN SELECTIVELY USING DILUTE AQUEOUS HF/HCL SOLUTION

Patent #:	9076688	Issue Dt:	07/07/2015	Application #:	14202675	Filing Dt:	03/10/2014
Title:	SCATTEROMETRY FOR NESTED AND ISOLATED STRUCTURES

Patent #:	8987083	Issue Dt:	03/24/2015	Application #:	14202985	Filing Dt:	03/10/2014
Title:	UNIFORM GATE HEIGHT FOR SEMICONDUCTOR STRUCTURE WITH N AND P TYPE FINS

Patent #:	9436081	Issue Dt:	09/06/2016	Application #:	14205569	Filing Dt:	03/12/2014
Publication #:	US20150261084	Pub Dt:	09/17/2015
Title:	METHODS OF MODIFYING MASKING RETICLES TO REMOVE FORBIDDEN PITCH REGIONS THEREOF

Patent #:	NONE	Issue Dt:		Application #:	14206203	Filing Dt:	03/12/2014
Publication #:	US20150263089	Pub Dt:	09/17/2015
Title:	NON-PLANAR SEMICONDUCTOR DEVICE WITH P-N JUNCTION LOCATED IN SUBSTRATE

Patent #:	NONE	Issue Dt:		Application #:	14206438	Filing Dt:	03/12/2014
Publication #:	US20150006835	Pub Dt:	01/01/2015
Title:	Backup Management for a Plurality of Logical Partitions

Patent #:	NONE	Issue Dt:		Application #:	14207319	Filing Dt:	03/12/2014
Publication #:	US20140190003	Pub Dt:	07/10/2014
Title:	SYSTEM AND METHOD FOR FORMING AN INDUCTOR WITH LAMINATED YOKE

Patent #:	9184288	Issue Dt:	11/10/2015	Application #:	14207822	Filing Dt:	03/13/2014
Publication #:	US20150263169	Pub Dt:	09/17/2015
Title:	SEMICONDUCTOR STRUCTURES WITH BRIDGING FILMS AND METHODS OF FABRICATION

Patent #:	NONE	Issue Dt:		Application #:	14208423	Filing Dt:	03/13/2014
Publication #:	US20140191332	Pub Dt:	07/10/2014
Title:	PFET DEVICES WITH DIFFERENT STRUCTURES AND PERFORMANCE CHARACTERISTICS

Patent #:	NONE	Issue Dt:		Application #:	14210408	Filing Dt:	03/13/2014
Publication #:	US20150032516	Pub Dt:	01/29/2015
Title:	MANAGING ELECTRIC VEHICLE (EV) CHARGING STATION USAGE

Patent #:	NONE	Issue Dt:		Application #:	14211479	Filing Dt:	03/14/2014
Publication #:	US20150262911	Pub Dt:	09/17/2015
Title:	TSV WITH END CAP, METHOD AND 3D INTEGRATED CIRCUIT

Patent #:	NONE	Issue Dt:		Application #:	14213338	Filing Dt:	03/14/2014
Publication #:	US20150120412	Pub Dt:	04/30/2015
Title:	ACTIVE IMPROVEMENT OF COUPONS BASED UPON CUSTOMER ASSISTED RESOLUTION OF INFORMATION GAPS

Patent #:	9224811	Issue Dt:	12/29/2015	Application #:	14215398	Filing Dt:	03/17/2014
Publication #:	US20150263088	Pub Dt:	09/17/2015
Title:	STACKED SEMICONDUCTOR DEVICE

Patent #:	9190418	Issue Dt:	11/17/2015	Application #:	14217572	Filing Dt:	03/18/2014
Publication #:	US20150270284	Pub Dt:	09/24/2015
Title:	JUNCTION BUTTING IN SOI TRANSISTOR WITH EMBEDDED SOURCE/DRAIN

Patent #:	9666717	Issue Dt:	05/30/2017	Application #:	14217691	Filing Dt:	03/18/2014
Publication #:	US20150270400	Pub Dt:	09/24/2015
Title:	SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS

Patent #:	10854472	Issue Dt:	12/01/2020	Application #:	14219039	Filing Dt:	03/19/2014
Publication #:	US20150270142	Pub Dt:	09/24/2015
Title:	METHOD FOR FORMING A METAL GATE INCLUDING DE-OXIDATION OF AN OXIDIZED SURFACE OF THE METAL GATE UTILIZING A REDUCING AGENT

Patent #:	NONE	Issue Dt:		Application #:	14219059	Filing Dt:	03/19/2014
Publication #:	US20150270175	Pub Dt:	09/24/2015
Title:	PARTIALLY CRYSTALLIZED FIN HARD MASK FOR FIN FIELD-EFFECT-TRANSISTOR (FINFET) DEVICE

Patent #:	9443772	Issue Dt:	09/13/2016	Application #:	14219193	Filing Dt:	03/19/2014
Publication #:	US20150270178	Pub Dt:	09/24/2015
Title:	DIFFUSION-CONTROLLED SEMICONDUCTOR CONTACT CREATION

Patent #:	NONE	Issue Dt:		Application #:	14219258	Filing Dt:	03/19/2014
Publication #:	US20140321080	Pub Dt:	10/30/2014
Title:	ELECTRICAL SOCKET

Patent #:	9553028	Issue Dt:	01/24/2017	Application #:	14219365	Filing Dt:	03/19/2014
Publication #:	US20150270176	Pub Dt:	09/24/2015
Title:	METHODS OF FORMING REDUCED RESISTANCE LOCAL INTERCONNECT STRUCTURES AND THE RESULTING DEVICES

Patent #:	9841773	Issue Dt:	12/12/2017	Application #:	14219460	Filing Dt:	03/19/2014
Publication #:	US20140316605	Pub Dt:	10/23/2014
Title:	Cooling System Management

Patent #:	8963255	Issue Dt:	02/24/2015	Application #:	14219910	Filing Dt:	03/19/2014
Publication #:	US20140203298	Pub Dt:	07/24/2014
Title:	STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS

Patent #:	NONE	Issue Dt:		Application #:	14220260	Filing Dt:	03/20/2014
Publication #:	US20150270159	Pub Dt:	09/24/2015
Title:	FABRICATION OF SEMICONDUCTOR STRUCTURES USING OXIDIZED POLYCRYSTALLINE SILICON AS CONFORMAL STOP LAYERS

Patent #:	9064972	Issue Dt:	06/23/2015	Application #:	14220437	Filing Dt:	03/20/2014
Publication #:	US20140206160	Pub Dt:	07/24/2014
Title:	Method of Forming A Gated Diode Structure for Eliminating RIE Damage From Cap Removal

Patent #:	NONE	Issue Dt:		Application #:	14220464	Filing Dt:	03/20/2014
Publication #:	US20150056967	Pub Dt:	02/26/2015
Title:	SYSTEM AND METHOD FOR COMMUNITY BASED MOBILE DEVICE PROFILING

Patent #:	9178495	Issue Dt:	11/03/2015	Application #:	14221859	Filing Dt:	03/21/2014
Publication #:	US20150270828	Pub Dt:	09/24/2015
Title:	ESTABLISHING A THERMAL PROFILE ACROSS A SEMICONDUCTOR CHIP

Patent #:	8828862	Issue Dt:	09/09/2014	Application #:	14222931	Filing Dt:	03/24/2014
Publication #:	US20140203453	Pub Dt:	07/24/2014
Title:	AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION

Patent #:	9236315	Issue Dt:	01/12/2016	Application #:	14222999	Filing Dt:	03/24/2014
Publication #:	US20140203280	Pub Dt:	07/24/2014
Title:	ELECTRICAL TEST STRUCTURE FOR DEVICES EMPLOYING HIGH-K DIELECTRICS OR METAL GATES

Patent #:	9263580	Issue Dt:	02/16/2016	Application #:	14223373	Filing Dt:	03/24/2014
Publication #:	US20150270398	Pub Dt:	09/24/2015
Title:	METHODS OF FORMING ISOLATED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9064890	Issue Dt:	06/23/2015	Application #:	14223545	Filing Dt:	03/24/2014
Title:	METHODS OF FORMING ISOLATION MATERIAL ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9236345	Issue Dt:	01/12/2016	Application #:	14223592	Filing Dt:	03/24/2014
Publication #:	US20150270222	Pub Dt:	09/24/2015
Title:	OXIDE MEDIATED EPITAXIAL NICKEL DISILICIDE ALLOY CONTACT FORMATION

Patent #:	9436845	Issue Dt:	09/06/2016	Application #:	14224099	Filing Dt:	03/25/2014
Publication #:	US20150278551	Pub Dt:	10/01/2015
Title:	PHYSICALLY UNCLONABLE FUSE USING A NOR TYPE MEMORY ARRAY

Patent #:	9323008	Issue Dt:	04/26/2016	Application #:	14224210	Filing Dt:	03/25/2014
Publication #:	US20150277064	Pub Dt:	10/01/2015
Title:	OPTOELECTRONIC STRUCTURES HAVING MULTI-LEVEL OPTICAL WAVEGUIDES AND METHODS OF FORMING THE STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	14224331	Filing Dt:	03/25/2014
Publication #:	US20140201971	Pub Dt:	07/24/2014
Title:	ASSEMBLY OF ELECTRONIC AND OPTICAL DEVICES

Patent #:	9378093	Issue Dt:	06/28/2016	Application #:	14224431	Filing Dt:	03/25/2014
Publication #:	US20140325262	Pub Dt:	10/30/2014
Title:	CONTROLLING DATA STORAGE IN AN ARRAY OF STORAGE DEVICES

Patent #:	NONE	Issue Dt:		Application #:	14224654	Filing Dt:	03/25/2014
Publication #:	US20150142886	Pub Dt:	05/21/2015
Title:	SYSTEM AND METHOD FOR IDENTIFYING COLLABORATORS ON A SHARED MOBILE DEVICE

Patent #:	9460963	Issue Dt:	10/04/2016	Application #:	14225529	Filing Dt:	03/26/2014
Publication #:	US20150279738	Pub Dt:	10/01/2015
Title:	SELF-ALIGNED CONTACTS AND METHODS OF FABRICATION

Patent #:	NONE	Issue Dt:		Application #:	14225758	Filing Dt:	03/26/2014
Publication #:	US20140317443	Pub Dt:	10/23/2014
Title:	METHOD AND APPARATUS FOR TESTING A STORAGE SYSTEM

Patent #:	NONE	Issue Dt:		Application #:	14226024	Filing Dt:	03/26/2014
Publication #:	US20140203342	Pub Dt:	07/24/2014
Title:	FERROELECTRIC RANDOM ACCESS MEMORY WITH OPTIMIZED HARDMASK

Patent #:	9324854	Issue Dt:	04/26/2016	Application #:	14226176	Filing Dt:	03/26/2014
Publication #:	US20140203339	Pub Dt:	07/24/2014
Title:	SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS AND A REPLACEMENT GATE ELECTRODE STRUCTURE

Patent #:	9142651	Issue Dt:	09/22/2015	Application #:	14226488	Filing Dt:	03/26/2014
Publication #:	US20150279963	Pub Dt:	10/01/2015
Title:	METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE SO AS TO REDUCE PUNCH-THROUGH LEAKAGE CURRENTS AND THE RESULTING DEVICE

Patent #:	8946010	Issue Dt:	02/03/2015	Application #:	14226746	Filing Dt:	03/26/2014
Publication #:	US20140206181	Pub Dt:	07/24/2014
Title:	THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHS

Patent #:	9586291	Issue Dt:	03/07/2017	Application #:	14226953	Filing Dt:	03/27/2014
Publication #:	US20150035173	Pub Dt:	02/05/2015
Title:	ADHESIVES FOR BONDING HANDLER WAFERS TO DEVICE WAFERS AND ENABLING MID-WAVELENGTH INFRARED LASER ABLATION RELEASE

Patent #:	9105742	Issue Dt:	08/11/2015	Application #:	14227267	Filing Dt:	03/27/2014
Title:	DUAL EPITAXIAL PROCESS INCLUDING SPACER ADJUSTMENT

Patent #:	8850127	Issue Dt:	09/30/2014	Application #:	14227398	Filing Dt:	03/27/2014
Publication #:	US20140215159	Pub Dt:	07/31/2014
Title:	MANAGING CONCURRENT ACCESSES TO A CACHE

Patent #:	9209135	Issue Dt:	12/08/2015	Application #:	14227807	Filing Dt:	03/27/2014
Publication #:	US20140210088	Pub Dt:	07/31/2014
Title:	METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME

Patent #:	9484367	Issue Dt:	11/01/2016	Application #:	14228106	Filing Dt:	03/27/2014
Publication #:	US20140209985	Pub Dt:	07/31/2014
Title:	GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS

Patent #:	9323882	Issue Dt:	04/26/2016	Application #:	14228611	Filing Dt:	03/28/2014
Publication #:	US20150278426	Pub Dt:	10/01/2015
Title:	METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF

Patent #:	NONE	Issue Dt:		Application #:	14228890	Filing Dt:	03/28/2014
Publication #:	US20140231878	Pub Dt:	08/21/2014
Title:	COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY

Patent #:	8963283	Issue Dt:	02/24/2015	Application #:	14230039	Filing Dt:	03/31/2014
Publication #:	US20140210039	Pub Dt:	07/31/2014
Title:	METHOD OF FABRICATING ISOLATED CAPACITORS AND STRUCTURE THEREOF

Patent #:	9059286	Issue Dt:	06/16/2015	Application #:	14230087	Filing Dt:	03/31/2014
Publication #:	US20140213029	Pub Dt:	07/31/2014
Title:	PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION

Patent #:	9257324	Issue Dt:	02/09/2016	Application #:	14230206	Filing Dt:	03/31/2014
Publication #:	US20140213036	Pub Dt:	07/31/2014
Title:	FORMING STRUCTURES ON RESISTIVE SUBSTRATES

Patent #:	9170482	Issue Dt:	10/27/2015	Application #:	14231913	Filing Dt:	04/01/2014
Publication #:	US20140215417	Pub Dt:	07/31/2014
Title:	TRIMMING OF DUMMY FILL SHAPES HOLES TO AFFECT NEAR-NEIGHBOR DUMMY FILL SHAPES WITH BUILT-IN OPTICAL PROXIMITY CORRECTIONS FOR SEMICONDUCTOR APPLICATIONS

Patent #:	NONE	Issue Dt:		Application #:	14236280	Filing Dt:	01/30/2014
Publication #:	US20140331287	Pub Dt:	11/06/2014
Title:	AUTHENTICATION POLICY ENFORCEMENT

Patent #:	9165836	Issue Dt:	10/20/2015	Application #:	14242046	Filing Dt:	04/01/2014
Publication #:	US20150279742	Pub Dt:	10/01/2015
Title:	METHODS OF FORMING REPLACEMENT GATE STRUCTURES USING A GATE HEIGHT REGISTER PROCESS TO IMPROVE GATE HEIGHT UNIFORMITY AND THE RESULTING INTEGRATED CIRCUIT PRODUCTS

Patent #:	9704973	Issue Dt:	07/11/2017	Application #:	14242130	Filing Dt:	04/01/2014
Publication #:	US20150279971	Pub Dt:	10/01/2015
Title:	METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS

Patent #:	9355936	Issue Dt:	05/31/2016	Application #:	14242203	Filing Dt:	04/01/2014
Publication #:	US20140209908	Pub Dt:	07/31/2014
Title:	FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING

Patent #:	9720101	Issue Dt:	08/01/2017	Application #:	14242283	Filing Dt:	04/01/2014
Publication #:	US20150006112	Pub Dt:	01/01/2015
Title:	METHOD OF CONSUMER/PRODUCER RAW MATERIAL SELECTION

Patent #:	9171934	Issue Dt:	10/27/2015	Application #:	14242329	Filing Dt:	04/01/2014
Publication #:	US20150279972	Pub Dt:	10/01/2015
Title:	METHODS OF FORMING SEMICONDUCTOR DEVICES USING A LAYER OF MATERIAL HAVING A PLURALITY OF TRENCHES FORMED THEREIN

Patent #:	9299781	Issue Dt:	03/29/2016	Application #:	14242416	Filing Dt:	04/01/2014
Publication #:	US20150279935	Pub Dt:	10/01/2015
Title:	SEMICONDUCTOR DEVICES WITH CONTACT STRUCTURES AND A GATE STRUCTURE POSITIONED IN TRENCHES FORMED IN A LAYER OF MATERIAL

Patent #:	9245980	Issue Dt:	01/26/2016	Application #:	14242472	Filing Dt:	04/01/2014
Publication #:	US20150279973	Pub Dt:	10/01/2015
Title:	METHODS OF FORMING SUBSTANTIALLY DEFECT-FREE, FULLY-STRAINED SILICON-GERMANIUM FINS FOR A FINFET SEMICONDUCTOR DEVICE

Patent #:	9524908	Issue Dt:	12/20/2016	Application #:	14242529	Filing Dt:	04/01/2014
Publication #:	US20150279959	Pub Dt:	10/01/2015
Title:	METHODS OF REMOVING PORTIONS OF FINS BY PREFORMING A SELECTIVELY ETCHABLE MATERIAL IN THE SUBSTRATE

Patent #:	9465290	Issue Dt:	10/11/2016	Application #:	14243238	Filing Dt:	04/02/2014
Publication #:	US20140210034	Pub Dt:	07/31/2014
Title:	NEAR-INFRARED ABSORBING FILM COMPOSITIONS

Patent #:	9413169	Issue Dt:	08/09/2016	Application #:	14243295	Filing Dt:	04/02/2014
Publication #:	US20150288174	Pub Dt:	10/08/2015
Title:	ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH A FAIL-SAFE MECHANISM

Patent #:	NONE	Issue Dt:		Application #:	14243398	Filing Dt:	04/02/2014
Publication #:	US20150287743	Pub Dt:	10/08/2015
Title:	MULTI-HEIGHT FIN FIELD EFFECT TRANSISTORS

Patent #:	9252061	Issue Dt:	02/02/2016	Application #:	14243491	Filing Dt:	04/02/2014
Publication #:	US20150287651	Pub Dt:	10/08/2015
Title:	OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION

Patent #:	NONE	Issue Dt:		Application #:	14243528	Filing Dt:	04/02/2014
Publication #:	US20150287176	Pub Dt:	10/08/2015
Title:	METHOD AND APPRATUS FOR HYBRID TEST PATTERN GENERATION FOR OPC MODEL CALIBRATION

Patent #:	NONE	Issue Dt:		Application #:	14243551	Filing Dt:	04/02/2014
Publication #:	US20150286763	Pub Dt:	10/08/2015
Title:	PATTERN MATCHING FOR PREDICTING DEFECT LIMITED YIELD

Patent #:	9466701	Issue Dt:	10/11/2016	Application #:	14244261	Filing Dt:	04/03/2014
Publication #:	US20150287795	Pub Dt:	10/08/2015
Title:	PROCESSES FOR PREPARING INTEGRATED CIRCUITS WITH IMPROVED SOURCE/DRAIN CONTACT STRUCTURES AND INTEGRATED CIRCUITS PREPARED ACCORDING TO SUCH PROCESSES

Patent #:	NONE	Issue Dt:		Application #:	14244322	Filing Dt:	04/03/2014
Publication #:	US20150287824	Pub Dt:	10/08/2015
Title:	INTEGRATED CIRCUITS WITH STRESSED SEMICONDUCTOR SUBSTRATES AND PROCESSES FOR PREPARING INTEGRATED CIRCUITS INCLUDING THE STRESSED SEMICONDUCTOR SUBSTRATES

Patent #:	9312189	Issue Dt:	04/12/2016	Application #:	14244651	Filing Dt:	04/03/2014
Publication #:	US20150287646	Pub Dt:	10/08/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES

Patent #:	9401362	Issue Dt:	07/26/2016	Application #:	14245656	Filing Dt:	04/04/2014
Publication #:	US20150287725	Pub Dt:	10/08/2015
Title:	MULTIPLE THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE

Patent #:	9582629	Issue Dt:	02/28/2017	Application #:	14245868	Filing Dt:	04/04/2014
Publication #:	US20150286764	Pub Dt:	10/08/2015
Title:	METHODS OF GENERATING CIRCUIT LAYOUTS USING SELF-ALLIGNED DOUBLE PATTERNING (SADP) TECHNIQUES

Patent #:	9352286	Issue Dt:	05/31/2016	Application #:	14246041	Filing Dt:	04/05/2014
Publication #:	US20140217014	Pub Dt:	08/07/2014
Title:	COMPOSITE FILTRATION MEMBRANES AND METHODS OF PREPARATION THEREOF

Patent #:	9472455	Issue Dt:	10/18/2016	Application #:	14246197	Filing Dt:	04/07/2014
Publication #:	US20150287604	Pub Dt:	10/08/2015
Title:	METHODS OF CROSS-COUPLING LINE SEGMENTS ON A WAFER

Patent #:	9804231	Issue Dt:	10/31/2017	Application #:	14246376	Filing Dt:	04/07/2014
Publication #:	US20140316725	Pub Dt:	10/23/2014
Title:	POWER NOISE HISTOGRAM OF A COMPUTER SYSTEM

Patent #:	NONE	Issue Dt:		Application #:	14246459	Filing Dt:	04/07/2014
Publication #:	US20140323155	Pub Dt:	10/30/2014
Title:	RESPONDING TO AN UNAVAILABLE COMMUNICATION TARGET DEVICE

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100

Patent #:	NONE	Issue Dt:		Application #:	14250554	Filing Dt:	04/11/2014
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Title:	ROUTING INFORMATION PROCESSING METHOD, COMPUTER PROGRAM, AND SYSTEM

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

440 STONE BREAK ROAD EXTENSION

MALTA, NEW YORK 12020

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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