|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
14250725
|
Filing Dt:
|
04/11/2014
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET AND METHODS OF FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
14250727
|
Filing Dt:
|
04/11/2014
|
Publication #:
|
|
Pub Dt:
|
10/30/2014
| | | | |
Title:
|
TAPE HEAD WITH THERMAL TAPE-HEAD DISTANCE SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2015
|
Application #:
|
14251386
|
Filing Dt:
|
04/11/2014
|
Publication #:
|
|
Pub Dt:
|
02/05/2015
| | | | |
Title:
|
INCREASED EFFICIENCY OF DATA PAYLOADS TO DATA ARRAYS ACCESSED THROUGH REGISTERS IN A DISTRIBUTED VIRTUAL BRIDGE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2016
|
Application #:
|
14251402
|
Filing Dt:
|
04/11/2014
|
Publication #:
|
|
Pub Dt:
|
10/15/2015
| | | | |
Title:
|
STAGGERED ELECTRICAL FRAME STRUCTURES FOR FRAME AREA REDUCTION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14251728
|
Filing Dt:
|
04/14/2014
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
Title:
|
INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2016
|
Application #:
|
14252447
|
Filing Dt:
|
04/14/2014
|
Publication #:
|
|
Pub Dt:
|
10/15/2015
| | | | |
Title:
|
DEFECT-FREE RELAXED COVERING LAYER ON SEMICONDUCTOR SUBSTRATE WITH LATTICE MISMATCH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14253235
|
Filing Dt:
|
04/15/2014
|
Publication #:
|
|
Pub Dt:
|
10/15/2015
| | | | |
Title:
|
TRISTATE INVERTER ARRAY TEST STRUCTURE AND METHOD OF TESTING A MICROCHIP
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14253668
|
Filing Dt:
|
04/15/2014
|
Publication #:
|
|
Pub Dt:
|
04/02/2015
| | | | |
Title:
|
METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITSI
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14253852
|
Filing Dt:
|
04/15/2014
|
Publication #:
|
|
Pub Dt:
|
04/16/2015
| | | | |
Title:
|
APPARATUS AND METHODS FOR AUTOMATICALLY REFLECTING CHANGES TO A COMPUTING SOLUTION IN AN IMAGE FOR THE COMPUTING SOLUTION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14253962
|
Filing Dt:
|
04/16/2014
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
CACHE ALLOCATION IN A COMPUTERIZED SYSTEM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14254460
|
Filing Dt:
|
04/16/2014
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SURFACE TREATING FOR DIRECTED SELF-ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
14254710
|
Filing Dt:
|
04/16/2014
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
TENSILE NITRIDE PROFILE SHAPER ETCH TO PROVIDE VOID FREE GAPFILL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14254866
|
Filing Dt:
|
04/16/2014
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
METHODS FOR THE PRODUCTION OF INTEGRATED CIRCUITS COMPRISING EPITAXIALLY GROWN REPLACEMENT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2017
|
Application #:
|
14254939
|
Filing Dt:
|
04/17/2014
|
Publication #:
|
|
Pub Dt:
|
08/14/2014
| | | | |
Title:
|
CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
14255037
|
Filing Dt:
|
04/17/2014
|
Publication #:
|
|
Pub Dt:
|
08/14/2014
| | | | |
Title:
|
ELONGATED VIA STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
14255067
|
Filing Dt:
|
04/17/2014
|
Publication #:
|
|
Pub Dt:
|
08/14/2014
| | | | |
Title:
|
METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2016
|
Application #:
|
14255497
|
Filing Dt:
|
04/17/2014
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
SELECTIVE PURGING OF A LOG STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14255547
|
Filing Dt:
|
04/17/2014
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
FRAUDULENT DATA DETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2016
|
Application #:
|
14257143
|
Filing Dt:
|
04/21/2014
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
PRECISION TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
|
Application #:
|
14257236
|
Filing Dt:
|
04/21/2014
|
Publication #:
|
|
Pub Dt:
|
10/30/2014
| | | | |
Title:
|
PARALLEL DATA PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14257395
|
Filing Dt:
|
04/21/2014
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE EMPLOYING A FERROMAGNETIC GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2016
|
Application #:
|
14257464
|
Filing Dt:
|
04/21/2014
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
RECONFIGURABLE BRANCH LINE COUPLER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14257899
|
Filing Dt:
|
04/21/2014
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
MODIFICATION OF A THRESHOLD VOLTAGE OF A TRANSISTOR BY OXYGEN TREATMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
14258063
|
Filing Dt:
|
04/22/2014
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
Title:
|
FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14258279
|
Filing Dt:
|
04/22/2014
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
SELF-ALIGNED CONTACT OPENINGS OVER FINS OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14258421
|
Filing Dt:
|
04/22/2014
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
SEMICONDUCTOR WAFER WITH NONSTICK SEAL REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
|
Application #:
|
14259179
|
Filing Dt:
|
04/23/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH A PLANAR BLOCK AREA TO ENABLE VARIALBLE FIN PITCH AND WIDTH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14259348
|
Filing Dt:
|
04/23/2014
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
SHARING WIRELESS TRAFFIC
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2016
|
Application #:
|
14259726
|
Filing Dt:
|
04/23/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
SOURCE/DRAIN PROFILE ENGINEERING FOR ENHANCED P-MOSFET
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14259852
|
Filing Dt:
|
04/23/2014
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
BATTERY SYSTEM FOR ELECTRICAL DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
14260399
|
Filing Dt:
|
04/24/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
CONTACT AND SOLDER BALL INTERCONNECT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
14260913
|
Filing Dt:
|
04/24/2014
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2016
|
Application #:
|
14261021
|
Filing Dt:
|
04/24/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM GATE METAL AND METHODS FOR FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
14261559
|
Filing Dt:
|
04/25/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2016
|
Application #:
|
14261632
|
Filing Dt:
|
04/25/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
NET-VOLTAGE-AWARE OPTICAL PROXIMITY CORRECTION (OPC)
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2017
|
Application #:
|
14261823
|
Filing Dt:
|
04/25/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
SELF-ALIGNED GATE CONTACT FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2017
|
Application #:
|
14262882
|
Filing Dt:
|
04/28/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
FABRICATING FIELD EFFECT TRANSISTOR(S) WITH STRESSED CHANNEL REGION(S) AND LOW-RESISTANCE SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
14263067
|
Filing Dt:
|
04/28/2014
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
Methodology and Apparatus for Tuning Driving Current of Semiconductor Transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2016
|
Application #:
|
14263329
|
Filing Dt:
|
04/28/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
MEASURING SETUP AND HOLD TIMES USING A VIRTUAL DELAY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
14263340
|
Filing Dt:
|
04/28/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14263399
|
Filing Dt:
|
04/28/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
FORMING GATE TIE BETWEEN ABUTTING CELLS AND RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
14264125
|
Filing Dt:
|
04/29/2014
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
14264163
|
Filing Dt:
|
04/29/2014
|
Title:
|
METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
14264179
|
Filing Dt:
|
04/29/2014
|
Title:
|
FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR WITH PUNCH-THROUGH STOP REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2020
|
Application #:
|
14264240
|
Filing Dt:
|
04/29/2014
|
Publication #:
|
|
Pub Dt:
|
10/29/2015
| | | | |
Title:
|
MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14264460
|
Filing Dt:
|
04/29/2014
|
Publication #:
|
|
Pub Dt:
|
11/27/2014
| | | | |
Title:
|
OUTPUTTING FAULT DATA FOR A HARDWARE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
14265401
|
Filing Dt:
|
04/30/2014
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
FINFETS AND FIN ISOLATION STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
14265409
|
Filing Dt:
|
04/30/2014
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
Method For Defining A Default State of a Charge Trap Based Memory Cell
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2015
|
Application #:
|
14265410
|
Filing Dt:
|
04/30/2014
|
Title:
|
LOW ENERGY ION IMPLANTATION OF A JUNCTION BUTTING REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
14265536
|
Filing Dt:
|
04/30/2014
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
SPACER TO PREVENT SOURCE-DRAIN CONTACT ENCROACHMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
14265623
|
Filing Dt:
|
04/30/2014
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
METHODS AND APPARATUS FOR DETECTION OF GASEOUS CORROSIVE CONTAMINANTS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14266278
|
Filing Dt:
|
04/30/2014
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
WIDE-BOTTOM CONTACT FOR NON-PLANAR SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
14266455
|
Filing Dt:
|
04/30/2014
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2015
|
Application #:
|
14267010
|
Filing Dt:
|
05/01/2014
|
Title:
|
METHODS OF FORMING ALTERNATIVE MATERIAL FINS WITH REDUCED DEFECT DENSITY FOR A FINFET SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14267088
|
Filing Dt:
|
05/01/2014
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
Natural language processing (NLP) query formulation engine for a computing device
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2016
|
Application #:
|
14267216
|
Filing Dt:
|
05/01/2014
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
METHODS OF FORMING EPITAXIAL SEMICONDUCTOR MATERIAL IN TRENCHES LOCATED ABOVE THE SOURCE AND DRAIN REGIONS OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14267405
|
Filing Dt:
|
05/01/2014
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
VERTICAL TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2017
|
Application #:
|
14267541
|
Filing Dt:
|
05/01/2014
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
Non-Planar Semiconductor Device with Multiple-Head Epitaxial Structure on Fin
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2015
|
Application #:
|
14267555
|
Filing Dt:
|
05/01/2014
|
Title:
|
METHODS OF FORMING REPLACEMENT SPACER STRUCTURES ON SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14267634
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Filing Dt:
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05/01/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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METHODS OF FORMING EPITAXIAL SEMICONDUCTOR CLADDING MATERIAL ON FINS OF A FINFET SEMICONDUCTOR DEVICE
|
|
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Patent #:
|
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Issue Dt:
|
12/08/2015
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Application #:
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14267959
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Filing Dt:
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05/02/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
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Application #:
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14268277
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Filing Dt:
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05/02/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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MEMORY TESTER DESIGN FOR SOFT ERROR RATE (SER) FAILURE ANALYSIS
|
|
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Patent #:
|
|
Issue Dt:
|
02/16/2016
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Application #:
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14268415
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Filing Dt:
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05/02/2014
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Publication #:
|
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Pub Dt:
|
11/05/2015
| | | | |
Title:
|
METHODS FOR REMOVING SELECTED FINS THAT ARE FORMED FOR FINFET SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
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14268440
|
Filing Dt:
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05/02/2014
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Publication #:
|
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Pub Dt:
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12/11/2014
| | | | |
Title:
|
PORTABLE COMPUTER MONITORING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
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Application #:
|
14268478
|
Filing Dt:
|
05/02/2014
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Title:
|
METHODS OF FORMING GATE STRUCTURES BY A GATE-CUT-LAST PROCESS AND THE RESULTING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2016
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Application #:
|
14268579
|
Filing Dt:
|
05/02/2014
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Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A SPACER ETCH BLOCK CAP AND THE RESULTING DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14269353
|
Filing Dt:
|
05/05/2014
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Publication #:
|
|
Pub Dt:
|
04/23/2015
| | | | |
Title:
|
SUBSTITUTION OF WORK PRODUCTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
14269566
|
Filing Dt:
|
05/05/2014
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14269599
|
Filing Dt:
|
05/05/2014
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
LOW LEAKAGE, HIGH FREQUENCY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14270824
|
Filing Dt:
|
05/06/2014
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Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
METHODS OF FABRICATING INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14270833
|
Filing Dt:
|
05/06/2014
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Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE INCLUDING A SET OF MERGED FINS FORMED ADJACENT A SET OF UNMERGED FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2016
|
Application #:
|
14270941
|
Filing Dt:
|
05/06/2014
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE COMPRISING A STACKED DIE CONFIGURATION INCLUDING AN INTEGRATED PELTIER ELEMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14270995
|
Filing Dt:
|
05/06/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
REDUCED SILICON GOUGING DURING OXIDE SPACER FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14271515
|
Filing Dt:
|
05/07/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
METAL-INSULATOR-METAL BACK END OF LINE CAPACITOR STRUCTURES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14272442
|
Filing Dt:
|
05/07/2014
|
Publication #:
|
|
Pub Dt:
|
12/25/2014
| | | | |
Title:
|
SELECTIVE DUPLICATION OF TAPE CARTRIDGE CONTENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
14272691
|
Filing Dt:
|
05/08/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
Sublithographic Kelvin Structure Patterned With DSA
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
14272787
|
Filing Dt:
|
05/08/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYERS FOR INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14272916
|
Filing Dt:
|
05/08/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
INTEGRATED CIRCUITS HAVING MAGNETIC TUNNEL JUNCTIONS (MTJ) AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2016
|
Application #:
|
14272952
|
Filing Dt:
|
05/08/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
INTEGRATED CIRCUITS HAVING IMPROVED GATE STRUCTURES AND METHODS FOR FABRICATING SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14273237
|
Filing Dt:
|
05/08/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
FORMING INTERCONNECT STRUCTURE WITH POLYMERIC LAYER AND RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
14273247
|
Filing Dt:
|
05/08/2014
|
Title:
|
PERFORMANCE SCREEN RING OSCILLATOR FORMED FROM MULTI-DIMENSIONAL PAIRINGS OF SCAN CHAINS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14273658
|
Filing Dt:
|
05/09/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
THROUGH CRACK STOP VIA
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14274042
|
Filing Dt:
|
05/09/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
METHOD OF INSPECTING A SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14274406
|
Filing Dt:
|
05/09/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING AN ELECTRICALLY-DECOUPLED FIN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
14274962
|
Filing Dt:
|
05/12/2014
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
14275448
|
Filing Dt:
|
05/12/2014
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14276360
|
Filing Dt:
|
05/13/2014
|
Publication #:
|
|
Pub Dt:
|
11/06/2014
| | | | |
Title:
|
INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14276515
|
Filing Dt:
|
05/13/2014
|
Publication #:
|
|
Pub Dt:
|
11/19/2015
| | | | |
Title:
|
MEANDER RESISTOR
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14278674
|
Filing Dt:
|
05/15/2014
|
Publication #:
|
|
Pub Dt:
|
11/19/2015
| | | | |
Title:
|
HIGH DENSITY FINFET DEVICES WITH UNMERGED FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
14278689
|
Filing Dt:
|
05/15/2014
|
Publication #:
|
|
Pub Dt:
|
11/19/2015
| | | | |
Title:
|
WAVEGUIDE DEVICES WITH SUPPORTING ANCHORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
14278974
|
Filing Dt:
|
05/15/2014
|
Title:
|
REDUCING COLOR CONFLICTS IN TRIPLE PATTERNING LITHOGRAPHY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14279495
|
Filing Dt:
|
05/16/2014
|
Publication #:
|
|
Pub Dt:
|
11/19/2015
| | | | |
Title:
|
METHODS OF FORMING NANOWIRE DEVICES WITH METAL-INSULATOR-SEMICONDUCTOR SOURCE/DRAIN CONTACTS AND THE RESULTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14280998
|
Filing Dt:
|
05/19/2014
|
Publication #:
|
|
Pub Dt:
|
11/19/2015
| | | | |
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH DIFFERENT FIN SETS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2017
|
Application #:
|
14281021
|
Filing Dt:
|
05/19/2014
|
Publication #:
|
|
Pub Dt:
|
11/19/2015
| | | | |
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
14281192
|
Filing Dt:
|
05/19/2014
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
14281726
|
Filing Dt:
|
05/19/2014
|
Title:
|
DOUBLE/MULTIPLE FIN STRUCTURE FOR FINFET DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14281744
|
Filing Dt:
|
05/19/2014
|
Publication #:
|
|
Pub Dt:
|
12/11/2014
| | | | |
Title:
|
REBUILDING DATA OF A STORAGE SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2018
|
Application #:
|
14282089
|
Filing Dt:
|
05/20/2014
|
Publication #:
|
|
Pub Dt:
|
11/26/2015
| | | | |
Title:
|
MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2016
|
Application #:
|
14282143
|
Filing Dt:
|
05/20/2014
|
Publication #:
|
|
Pub Dt:
|
11/27/2014
| | | | |
Title:
|
TESTING AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2017
|
Application #:
|
14282257
|
Filing Dt:
|
05/20/2014
|
Publication #:
|
|
Pub Dt:
|
11/26/2015
| | | | |
Title:
|
METAL GATE STRUCTURE AND METHOD OF FORMATION
|
|