|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
14633998
|
Filing Dt:
|
02/27/2015
|
Title:
|
LOW LINE RESISTIVITY AND REPEATABLE METAL RECESS USING CVD COBALT REFLOW
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14634222
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
06/18/2015
| | | | |
Title:
|
INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14634255
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/01/2016
| | | | |
Title:
|
MIM CAPACITOR WITH RESISTOR LAYER AS LOWER PLATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
14634483
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/01/2016
| | | | |
Title:
|
CO-FABRICATION OF NON-PLANAR SEMICONDUCTOR DEVICES HAVING DIFFERENT THRESHOLD VOLTAGES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14634820
|
Filing Dt:
|
02/28/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14634978
|
Filing Dt:
|
03/02/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
COIL INDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2018
|
Application #:
|
14635005
|
Filing Dt:
|
03/02/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
METHOD TO PROTECT SENSITIVE DEVICES FROM ELECTROSTATIC DISCHARGE DAMAGE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14635071
|
Filing Dt:
|
03/02/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
METHODS OF FORMING A MASKING PATTERN AND A SEMICONDUCTOR DEVICE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2017
|
Application #:
|
14635125
|
Filing Dt:
|
03/02/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
ELECTROMIGRATION TESTING OF INTERCONNECT ANALOGUES HAVING BOTTOM-CONNECTED SENSORY PINS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14636679
|
Filing Dt:
|
03/03/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
REMOVAL OF INTEGRATED CIRCUIT CHIPS FROM A WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
14637442
|
Filing Dt:
|
03/04/2015
|
Title:
|
METHOD TO IMPROVE SELECTIVITY COBALT CAP PROCESS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14637448
|
Filing Dt:
|
03/04/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
SLOTTED SUBSTRATE FOR DIE ATTACH INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2017
|
Application #:
|
14637459
|
Filing Dt:
|
03/04/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
METHOD AND DEVICE FOR SPLITTING A HIGH-POWER LIGHT BEAM TO PROVIDE SIMULTANEOUS SUB-BEAMS TO PHOTOLITHOGRAPHY SCANNERS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14639620
|
Filing Dt:
|
03/05/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING TWO PHOTORESIST EXPOSURE PROCESSES FOR PROVIDING A GATE CUT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
14640047
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
MULTIPLE VOLUME ENCRYPTION OF STORAGE DEVICES USING SELF ENCRYPTING DRIVE (SED)
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2016
|
Application #:
|
14640151
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
FERROELECTRIC FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
14640698
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14640735
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14640757
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
ETSOI WITH REDUCED EXTENSION RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
14640851
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
FinFET DEVICE HAVING A MERGE SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2016
|
Application #:
|
14641462
|
Filing Dt:
|
03/09/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
MULTI-FIN FINFETS WITH MERGED-FIN SOURCE/DRAINS AND REPLACEMENT GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
14641551
|
Filing Dt:
|
03/09/2015
|
Title:
|
METHODS OF FORMING CONTACTS ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2016
|
Application #:
|
14641699
|
Filing Dt:
|
03/09/2015
|
Title:
|
INTERCONNECT STRUCTURES AND METHODS OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
14641917
|
Filing Dt:
|
03/09/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
DIAMOND SHAPED SOURCE DRAIN EPITAXY WITH UNDERLYING BUFFER LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14642909
|
Filing Dt:
|
03/10/2015
|
Title:
|
FABRICATION OF A DEEP TRENCH MEMORY CELL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14643224
|
Filing Dt:
|
03/10/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
STACKED CARBON-BASED FETS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14643323
|
Filing Dt:
|
03/10/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
OPTICAL DIE PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
14643326
|
Filing Dt:
|
03/10/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING BACKGATE REGIONS AND METHOD FOR THE FORMATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2016
|
Application #:
|
14643409
|
Filing Dt:
|
03/10/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
METHODS OF FORMING EMBEDDED SOURCE/DRAIN REGIONS ON FINFET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
14643436
|
Filing Dt:
|
03/10/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
14644269
|
Filing Dt:
|
03/11/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
CAP LAYER FOR SPACER-CONSTRAINED EPITAXIALLY GROWN MATERIAL ON FINS OF A FINFET DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14644416
|
Filing Dt:
|
03/11/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
PHOTO-PATTERNABLE DIELECTRIC MATERIALS AND FORMULATIONS AND METHODS OF USE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2017
|
Application #:
|
14645121
|
Filing Dt:
|
03/11/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
METHODS, APPARATUS AND SYSTEM FOR FABRICATING HIGH PERFORMANCE FINFET DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14645350
|
Filing Dt:
|
03/11/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
BACKWARD COMPATIBLE HEAD FOR QUASI-STATIC TILTED READING AND/OR RECORDING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2018
|
Application #:
|
14645449
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14645477
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
INTEGRATED STRAINED FIN AND RELAXED FIN
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2017
|
Application #:
|
14645541
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
LEAKAGE TESTING OF INTEGRATED CIRCUITS USING A LOGARITHMIC TRANSDUCER AND A VOLTMETER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
14645598
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2017
|
Application #:
|
14645871
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
METHOD, APPARATUS AND SYSTEM FOR USING FREE-ELECTRON LASER COMPATIBLE EUV BEAM FOR SEMICONDUCTOR WAFER METROLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2017
|
Application #:
|
14656412
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
METHODS, APPARATUS AND SYSTEM FOR PROVIDING SOURCE-DRAIN EPITAXY LAYER WITH LATERAL OVER-GROWTH SUPPRESSION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14656649
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
FINFET WITH ACTIVE REGION SHAPED STRUCTURES AND CHANNEL SEPARATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2018
|
Application #:
|
14656671
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2016
|
Application #:
|
14656770
|
Filing Dt:
|
03/13/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING NON-MAGNETIC SINGLE CORE INDUCTOR AND METHOD OF PRODUCING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
14656790
|
Filing Dt:
|
03/13/2015
|
Publication #:
|
|
Pub Dt:
|
10/01/2015
| | | | |
Title:
|
DIGITAL IC SIMULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
14657864
|
Filing Dt:
|
03/13/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
14658279
|
Filing Dt:
|
03/16/2015
|
Title:
|
ELIMINATING FIELD OXIDE LOSS PRIOR TO FINFET SOURCE/DRAIN EPITAXIAL GROWTH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14658361
|
Filing Dt:
|
03/16/2015
|
Publication #:
|
|
Pub Dt:
|
09/22/2016
| | | | |
Title:
|
HIGH-VOLTAGE TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14658587
|
Filing Dt:
|
03/16/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
OPTIMIZING PERFORMANCE OF A COMPUTER SYSTEM IN RESPONSE TO A SOFTWARE CHANGE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14658898
|
Filing Dt:
|
03/16/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
CONTACT RESISTANCE REDUCTION IN FINFETS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14658975
|
Filing Dt:
|
03/16/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
CONTACT RESISTANCE REDUCTION IN FINFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2017
|
Application #:
|
14659749
|
Filing Dt:
|
03/17/2015
|
Publication #:
|
|
Pub Dt:
|
09/22/2016
| | | | |
Title:
|
SILICIDED NANOWIRES FOR NANOBRIDGE WEAK LINKS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2017
|
Application #:
|
14659793
|
Filing Dt:
|
03/17/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2018
|
Application #:
|
14661202
|
Filing Dt:
|
03/18/2015
|
Publication #:
|
|
Pub Dt:
|
09/22/2016
| | | | |
Title:
|
TRANSISTORS PATTERNED WITH ELECTROSTATIC DISCHARGE PROTECTION AND METHODS OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2016
|
Application #:
|
14661383
|
Filing Dt:
|
03/18/2015
|
Title:
|
REBALANCING IN TWIN CELL MEMORY SCHEMES TO ENABLE MULTIPLE WRITES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
14662468
|
Filing Dt:
|
03/19/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
14662734
|
Filing Dt:
|
03/19/2015
|
Publication #:
|
|
Pub Dt:
|
09/22/2016
| | | | |
Title:
|
TRANSISTOR STRUCTURE HAVING N-TYPE AND P-TYPE ELONGATED REGIONS INTERSECTING UNDER COMMON GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2016
|
Application #:
|
14662743
|
Filing Dt:
|
03/19/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14663256
|
Filing Dt:
|
03/19/2015
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14663754
|
Filing Dt:
|
03/20/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
14663806
|
Filing Dt:
|
03/20/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
14664036
|
Filing Dt:
|
03/20/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
METHOD TO FABRICATE COPPER WIRING STRUCTURES AND STRUCTURES FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14664435
|
Filing Dt:
|
03/20/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2017
|
Application #:
|
14664959
|
Filing Dt:
|
03/23/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
METHOD TO IDENTIFY EXTRINSIC SRAM BITS FOR FAILURE ANALYSIS BASED ON FAIL COUNT VOLTAGE RESPONSE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
14664970
|
Filing Dt:
|
03/23/2015
|
Title:
|
METHOD OF USING A BACK-END-OF-LINE CONNECTION STRUCTURE TO DISTRIBUTE CURRENT EVENLY AMONG MULTIPLE TSVS IN A SERIES FOR DELIVERY TO A TOP DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2017
|
Application #:
|
14665242
|
Filing Dt:
|
03/23/2015
|
Publication #:
|
|
Pub Dt:
|
12/03/2015
| | | | |
Title:
|
METHOD OF CHECKING THE LAYOUT INTEGRITY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14665432
|
Filing Dt:
|
03/23/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14666420
|
Filing Dt:
|
03/24/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
MEMORY CELL, MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELLS AND METHOD INCLUDING READ AND WRITE OPERATIONS AT A MEMORY CELL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14666590
|
Filing Dt:
|
03/24/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
TAPE HEAD WITH TAPE-BEARING SURFACE EXHIBITING AN ARRAY OF PROTRUDING TOPOGRAPHIC FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14667174
|
Filing Dt:
|
03/24/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2017
|
Application #:
|
14667778
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
SHORT-CHANNEL NFET DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14667872
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
FORMING TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKING FAULT AND RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2018
|
Application #:
|
14668017
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
GLASS INTERPOSER WITH EMBEDDED THERMOELECTRIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
14668018
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
DENSE FINFET SRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
14668031
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
METHOD OF FORMING A GLASS INTERPOSER WITH THERMAL VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
|
Application #:
|
14669055
|
Filing Dt:
|
03/26/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
MACRO TO MONITOR N-P BUMP
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14669213
|
Filing Dt:
|
03/26/2015
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
HARDMASK CAPPING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2016
|
Application #:
|
14670800
|
Filing Dt:
|
03/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
DUAL CHANNEL FINFET WITH RELAXED PFET REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
14671027
|
Filing Dt:
|
03/27/2015
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS BY MODIFIED RF POWER RAMP-UP
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2018
|
Application #:
|
14671265
|
Filing Dt:
|
03/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
DYNAMIC INTEGRATED CIRCUIT FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
14671819
|
Filing Dt:
|
03/27/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
HIGH DENSITY TIMING BASED SERVO FORMAT FOR USE WITH TILTED TRANSDUCER ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14672157
|
Filing Dt:
|
03/28/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14672160
|
Filing Dt:
|
03/28/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2017
|
Application #:
|
14673185
|
Filing Dt:
|
03/30/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
VIA LEAKAGE AND BREAKDOWN TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2016
|
Application #:
|
14673926
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
MAINTAINING A CLUSTER OF VIRTUAL MACHINES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
14673958
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
FORMATION OF A HIGH ASPECT RATIO TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT RATIO TRENCH ISOLATION REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2016
|
Application #:
|
14674108
|
Filing Dt:
|
03/31/2015
|
Title:
|
METHODS OF PERFORMING FIN CUT ETCH PROCESSES FOR TAPER FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2017
|
Application #:
|
14674157
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
RETICLE, SYSTEM COMPRISING A PLURALITY OF RETICLES AND METHOD FOR THE FORMATION THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14674242
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2016
|
Application #:
|
14674460
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14674571
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
PREDICTING PROCESS FAIL LIMITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2016
|
Application #:
|
14674792
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
SELF-ALIGNED DOUBLE PATTERNING PROCESS FOR TWO DIMENSIONAL PATTERNS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2017
|
Application #:
|
14674859
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
ANONYMOUS VEHICLE COMMUNICATION PROTOCOL IN VEHICLE-TO-VEHICLE NETWORKS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
14674924
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
METHODS OF FORMING DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
14675316
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
COMPOSITE MEMBRANES AND METHODS OF PREPARATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2016
|
Application #:
|
14675880
|
Filing Dt:
|
04/01/2015
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
METHOD FOR FORMING AIR GAP STRUCTURE USING CARBON-CONTAINING SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2016
|
Application #:
|
14676034
|
Filing Dt:
|
04/01/2015
|
Title:
|
METHODS OF REMOVING FINS SO AS TO FORM ISOLATION STRUCTURES ON PRODUCTS THAT INCLUDE FINFET SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2016
|
Application #:
|
14676097
|
Filing Dt:
|
04/01/2015
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
METHODS OF FORMING FEATURES HAVING DIFFERING PITCH SPACING AND CRITICAL DIMENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
14676165
|
Filing Dt:
|
04/01/2015
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
METHOD FOR FORMING SINGLE DIFFUSION BREAKS BETWEEN FINFET DEVICES AND THE RESULTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
14676239
|
Filing Dt:
|
04/01/2015
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2016
|
Application #:
|
14676345
|
Filing Dt:
|
04/01/2015
|
Title:
|
METHOD FOR SINGLE FIN CUTS USING SELECTIVE ION IMPLANTS
|
|