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NONE
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14706495
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05/07/2015
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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SOLID STATE NANOPORE DEVICES AND METHODS OF MANUFACTURE
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NONE
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14707775
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Filing Dt:
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05/08/2015
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Pub Dt:
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09/03/2015
| | | | |
Title:
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BURIED-CHANNEL FIELD-EFFECT TRANSISTORS
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Patent #:
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NONE
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Application #:
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14707822
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Filing Dt:
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05/08/2015
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Publication #:
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Pub Dt:
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09/03/2015
| | | | |
Title:
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ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES
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Patent #:
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Issue Dt:
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02/21/2017
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14707923
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Filing Dt:
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05/08/2015
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14708350
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Filing Dt:
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05/11/2015
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Publication #:
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Pub Dt:
|
08/27/2015
| | | | |
Title:
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JOINING A CHIP TO A SUBSTRATE WITH SOLDER ALLOYS HAVING DIFFERENT REFLOW TEMPERATURES
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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14708405
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Filing Dt:
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05/11/2015
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Publication #:
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Pub Dt:
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09/03/2015
| | | | |
Title:
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METHODS OF FORMING REPLACEMENT GATE STRUCTURES AND FINS ON FINFET DEVICES AND THE RESULTING DEVICES
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Patent #:
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Issue Dt:
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10/18/2016
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Application #:
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14708753
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Filing Dt:
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05/11/2015
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS
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Patent #:
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Issue Dt:
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03/07/2017
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Application #:
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14709889
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Filing Dt:
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05/12/2015
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Publication #:
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Pub Dt:
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11/17/2016
| | | | |
Title:
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ALIGNMENT MONITORING STRUCTURE AND ALIGNMENT MONITORING METHOD FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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02/14/2017
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14709924
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Filing Dt:
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05/12/2015
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Publication #:
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Pub Dt:
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11/19/2015
| | | | |
Title:
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ARTICLES INCLUDING BONDED METAL STRUCTURES AND METHODS OF PREPARING THE SAME
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Patent #:
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Issue Dt:
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09/20/2016
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Application #:
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14710053
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Filing Dt:
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05/12/2015
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Title:
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METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
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Patent #:
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NONE
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Application #:
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14710204
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Filing Dt:
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05/12/2015
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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RESISTIVE RANDOM ACCESS MEMORY DEVICES WITH EXTREMELY REACTIVE CONTACTS
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Patent #:
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Issue Dt:
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11/08/2016
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Application #:
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14710894
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
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11/17/2016
| | | | |
Title:
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VIA FORMATION USING SIDEWALL IMAGE TRANSFER PROCESS TO DEFINE LATERAL DIMENSION
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Patent #:
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Issue Dt:
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12/15/2015
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Application #:
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14710935
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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METHOD OF SELF-CORRECTING POWER GRID FOR SEMICONDUCTOR STRUCTURES
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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14711029
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH FIELD-INDUCING STRUCTURE
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Patent #:
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Issue Dt:
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12/29/2015
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Application #:
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14711069
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
|
08/27/2015
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES
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Patent #:
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Issue Dt:
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03/01/2016
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Application #:
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14711119
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
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09/03/2015
| | | | |
Title:
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THICK AND THIN DATA VOLUME MANAGEMENT
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Patent #:
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Issue Dt:
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08/23/2016
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Application #:
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14711196
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH LOW-K SPACERS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14711280
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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CAP LAYERS FOR SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACT ELEMENTS
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Patent #:
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Issue Dt:
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12/22/2015
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Application #:
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14711377
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
|
09/03/2015
| | | | |
Title:
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METHOD OF USING AN EUV MASK DURING EUV PHOTOLITHOGRAPHY PROCESSES
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Patent #:
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Issue Dt:
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12/20/2016
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Application #:
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14711380
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
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11/17/2016
| | | | |
Title:
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FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES
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Patent #:
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Issue Dt:
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05/17/2016
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Application #:
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14711462
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
|
09/03/2015
| | | | |
Title:
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HETEROJUNCTION LIGHT EMITTING DIODE
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Patent #:
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Issue Dt:
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10/10/2017
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Application #:
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14712092
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Filing Dt:
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05/14/2015
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Publication #:
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Pub Dt:
|
08/27/2015
| | | | |
Title:
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BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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14712197
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Filing Dt:
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05/14/2015
|
Publication #:
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Pub Dt:
|
11/17/2016
| | | | |
Title:
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LITHOGRAPHY STACK AND METHOD
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|
Patent #:
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Issue Dt:
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11/08/2016
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Application #:
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14712388
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Filing Dt:
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05/14/2015
|
Publication #:
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Pub Dt:
|
11/17/2016
| | | | |
Title:
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GATE CONTACT STRUCTURE HAVING GATE CONTACT LAYER
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Patent #:
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Issue Dt:
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03/14/2017
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Application #:
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14712397
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Filing Dt:
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05/14/2015
|
Publication #:
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|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
DUAL SHALLOW TRENCH ISOLATION (STI) STRUCTURE FOR FIELD EFFECT TRANSISTOR (FET)
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
14712767
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Filing Dt:
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05/14/2015
|
Publication #:
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|
Pub Dt:
|
11/17/2016
| | | | |
Title:
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METHODS, APPARATUS AND SYSTEM FOR FABRICATING FINFET DEVICES USING CONTINUOUS ACTIVE AREA DESIGN
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Patent #:
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Issue Dt:
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08/08/2017
|
Application #:
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14712830
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Filing Dt:
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05/14/2015
|
Publication #:
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|
Pub Dt:
|
11/17/2016
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR IMPROVED STANDARD CELL DESIGN AND ROUTING FOR IMPROVING STANDARD CELL ROUTABILITY
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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14713327
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Filing Dt:
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05/15/2015
|
Publication #:
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|
Pub Dt:
|
09/03/2015
| | | | |
Title:
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INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE
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Patent #:
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Issue Dt:
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01/17/2017
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Application #:
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14714779
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Filing Dt:
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05/18/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
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SHALLOW TRENCH ISOLATION STRUCTURES
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Patent #:
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Issue Dt:
|
04/26/2016
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Application #:
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14715050
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Filing Dt:
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05/18/2015
|
Title:
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METHODS OF FORMING ELASTICALLY RELAXED SiGe VIRTUAL SUBSTRATES ON BULK SILICON
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Patent #:
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Issue Dt:
|
06/07/2016
|
Application #:
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14715109
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Filing Dt:
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05/18/2015
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Title:
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METHODS OF FORMING ELASTICALLY RELAXED SIGE VIRTUAL SUBSTRATES ON BULK SILICON
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|
Patent #:
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Issue Dt:
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12/27/2016
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Application #:
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14715693
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Filing Dt:
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05/19/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
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SILICON-ON-INSULATOR HEAT SINK
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|
Patent #:
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Issue Dt:
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11/17/2015
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Application #:
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14716236
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Filing Dt:
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05/19/2015
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Publication #:
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|
Pub Dt:
|
10/01/2015
| | | | |
Title:
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REDUCING WAFER BONDING MISALIGNMENT BY VARYING THERMAL TREATMENT PRIOR TO BONDING
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Patent #:
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Issue Dt:
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05/02/2017
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Application #:
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14716565
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Filing Dt:
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05/19/2015
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Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR OFFSET METAL POWER RAIL FOR CELL DESIGN
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Patent #:
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Issue Dt:
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01/17/2017
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Application #:
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14716696
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Filing Dt:
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05/19/2015
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Publication #:
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Pub Dt:
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01/21/2016
| | | | |
Title:
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SHALLOW TRENCH ISOLATION STRUCTURE WITH SIGMA CAVITY
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Patent #:
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Issue Dt:
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07/10/2018
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Application #:
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14716938
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Filing Dt:
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05/20/2015
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Publication #:
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Pub Dt:
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11/24/2016
| | | | |
Title:
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PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14716959
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Filing Dt:
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05/20/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
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FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING
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Patent #:
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Issue Dt:
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10/18/2016
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Application #:
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14717344
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Filing Dt:
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05/20/2015
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Publication #:
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Pub Dt:
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09/24/2015
| | | | |
Title:
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ACTIVE MATRIX USING HYBRID INTEGRATED CIRCUIT AND BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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14717387
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Filing Dt:
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05/20/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
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METHODS FOR FABRICATION INTERCONNECT STRUCTURES WITH FUNCTIONAL COMPONENTS AND ELECTRICAL CONDUCTIVE CONTACT STRUCTURES ON A SAME LEVEL
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Patent #:
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Issue Dt:
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10/10/2017
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Application #:
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14718314
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Filing Dt:
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05/21/2015
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Publication #:
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Pub Dt:
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11/24/2016
| | | | |
Title:
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THIN FILM BASED FAN OUT AND MULTI DIE PACKAGE PLATFORM
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Patent #:
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Issue Dt:
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04/05/2016
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Application #:
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14718331
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Filing Dt:
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05/21/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
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FILE SYSTEM LEVEL DATA PROTECTION DURING POTENTIAL SECURITY BREACH
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Patent #:
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NONE
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Application #:
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14718402
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Filing Dt:
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05/21/2015
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Publication #:
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Pub Dt:
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11/24/2016
| | | | |
Title:
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INTERFACE PASSIVATION LAYERS AND METHODS OF FABRICATING
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Patent #:
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Issue Dt:
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01/24/2017
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Application #:
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14718502
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Filing Dt:
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05/21/2015
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Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
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E-FUSE IN SOI CONFIGURATION
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Patent #:
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Issue Dt:
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11/08/2016
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Application #:
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14718574
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Filing Dt:
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05/21/2015
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Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
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DEVICE COMPRISING A PLURALITY OF FDSOI STATIC RANDOM-ACCESS MEMORY BITCELLS AND METHOD OF OPERATION THEREOF
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Patent #:
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Issue Dt:
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11/20/2018
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Application #:
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14718747
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Filing Dt:
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05/21/2015
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Publication #:
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Pub Dt:
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11/24/2016
| | | | |
Title:
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EDGE TRIM PROCESSES AND RESULTANT STRUCTURES
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Patent #:
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Issue Dt:
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12/06/2016
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Application #:
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14718760
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Filing Dt:
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05/21/2015
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Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
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IMPLANT-FREE PUNCH THROUGH DOPING LAYER FORMATION FOR BULK FINFET STRUCTURES
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Patent #:
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Issue Dt:
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04/04/2017
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Application #:
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14719424
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Filing Dt:
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05/22/2015
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Publication #:
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Pub Dt:
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12/03/2015
| | | | |
Title:
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SEMICONDUCTOR DEVICE STRUCTURE INCLUDING ACTIVE REGION HAVING AN EXTENSION PORTION
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Patent #:
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Issue Dt:
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11/01/2016
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Application #:
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14720328
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Filing Dt:
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05/22/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
|
BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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|
Patent #:
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NONE
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Issue Dt:
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Application #:
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14720393
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Filing Dt:
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05/22/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
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BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
|
14720427
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Filing Dt:
|
05/22/2015
|
Publication #:
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|
Pub Dt:
|
09/10/2015
| | | | |
Title:
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FORMING CRYSTALLINE COMPOUND MATERIAL ON EXPOSED BOTTOM OF TRENCH FORMED IN SINGLE CRYSTALLINE SUBSTRATE
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Patent #:
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Issue Dt:
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08/28/2018
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Application #:
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14721402
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Filing Dt:
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05/26/2015
|
Publication #:
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Pub Dt:
|
12/01/2016
| | | | |
Title:
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METHOD AND STRUCTURE FOR FORMATION OF REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
14721822
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Filing Dt:
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05/26/2015
|
Publication #:
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|
Pub Dt:
|
12/01/2016
| | | | |
Title:
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INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING REPLACEMENT METAL GATE ELECTRODES
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
14721840
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Filing Dt:
|
05/26/2015
|
Publication #:
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|
Pub Dt:
|
09/10/2015
| | | | |
Title:
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SHALLOW JUNCTION PHOTOVOLTAIC DEVICES
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Patent #:
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Issue Dt:
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10/17/2017
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Application #:
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14722074
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Filing Dt:
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05/26/2015
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Publication #:
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Pub Dt:
|
12/01/2016
| | | | |
Title:
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DEFECT DETECTION PROCESS IN A SEMICONDUCTOR MANUFACTURING ENVIRONMENT
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
14722295
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Filing Dt:
|
05/27/2015
|
Publication #:
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|
Pub Dt:
|
07/14/2016
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE COMPRISING AN ALUMINUM GATE ELECTRODE PORTION AND METHOD FOR THE FORMATION THEREOF
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Patent #:
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|
Issue Dt:
|
06/07/2016
|
Application #:
|
14722302
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Filing Dt:
|
05/27/2015
|
Title:
|
METHODS TO FORM CONDUCTIVE THIN FILM STRUCTURES
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|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
14722411
|
Filing Dt:
|
05/27/2015
|
Publication #:
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|
Pub Dt:
|
09/10/2015
| | | | |
Title:
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DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING
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|
Patent #:
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|
Issue Dt:
|
07/19/2016
|
Application #:
|
14722818
|
Filing Dt:
|
05/27/2015
|
Title:
|
METHOD FOR FORMING SOURCE/DRAIN CONTACTS DURING CMOS INTEGRATION USING CONFINED EPITAXIAL GROWTH TECHNIQUES
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|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
14723095
|
Filing Dt:
|
05/27/2015
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Publication #:
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|
Pub Dt:
|
10/01/2015
| | | | |
Title:
|
UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS
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|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
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Application #:
|
14723681
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Filing Dt:
|
05/28/2015
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Publication #:
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Pub Dt:
|
09/17/2015
| | | | |
Title:
|
FINFET SEMICONDUCTOR DEVICE HAVING INCREASED GATE HEIGHT CONTROL
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Patent #:
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|
Issue Dt:
|
12/19/2017
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Application #:
|
14723703
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Filing Dt:
|
05/28/2015
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Publication #:
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Pub Dt:
|
09/17/2015
| | | | |
Title:
|
VACUUM TRAP
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|
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Patent #:
|
|
Issue Dt:
|
08/02/2016
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Application #:
|
14725151
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Filing Dt:
|
05/29/2015
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Publication #:
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Pub Dt:
|
09/17/2015
| | | | |
Title:
|
PASSIVATION OF BACK-ILLUMINATED IMAGE SENSOR
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|
|
Patent #:
|
|
Issue Dt:
|
08/30/2016
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Application #:
|
14725392
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Filing Dt:
|
05/29/2015
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Publication #:
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Pub Dt:
|
09/17/2015
| | | | |
Title:
|
REPLACEMENT GATE STRUCTURE WITH LOW-K SIDEWALL SPACER FOR SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
14725430
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Filing Dt:
|
05/29/2015
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Publication #:
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Pub Dt:
|
10/08/2015
| | | | |
Title:
|
DEVICES AND METHODS OF FORMING FINS AT TIGHT FIN PITCHES
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
14725505
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Filing Dt:
|
05/29/2015
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Publication #:
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Pub Dt:
|
09/17/2015
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS
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|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
14725552
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Filing Dt:
|
05/29/2015
|
Title:
|
FABRICATING FIN STRUCTURES WITH DOPED MIDDLE PORTIONS
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|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14725581
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Filing Dt:
|
05/29/2015
|
Publication #:
|
|
Pub Dt:
|
10/08/2015
| | | | |
Title:
|
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
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|
|
Patent #:
|
|
Issue Dt:
|
04/19/2016
|
Application #:
|
14725663
|
Filing Dt:
|
05/29/2015
|
Publication #:
|
|
Pub Dt:
|
10/15/2015
| | | | |
Title:
|
METHODS OF FORMING SUBSTANTIALLY SELF-ALIGNED ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14725755
|
Filing Dt:
|
05/29/2015
|
Publication #:
|
|
Pub Dt:
|
09/17/2015
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14725795
|
Filing Dt:
|
05/29/2015
|
Publication #:
|
|
Pub Dt:
|
09/17/2015
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2017
|
Application #:
|
14726712
|
Filing Dt:
|
06/01/2015
|
Publication #:
|
|
Pub Dt:
|
12/01/2016
| | | | |
Title:
|
HYBRID FIN CUTTING PROCESSES FOR FINFET SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
03/21/2017
|
Application #:
|
14726945
|
Filing Dt:
|
06/01/2015
|
Publication #:
|
|
Pub Dt:
|
12/01/2016
| | | | |
Title:
|
SUB-NANOSECOND DISTRIBUTED CLOCK SYNCHRONIZATION USING ALIGNMENT MARKER IN ETHERNET IEEE 1588 PROTOCOL
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|
|
Patent #:
|
|
Issue Dt:
|
09/06/2016
|
Application #:
|
14727219
|
Filing Dt:
|
06/01/2015
|
Title:
|
MERGED SOURCE DRAIN EPITAXY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14727245
|
Filing Dt:
|
06/01/2015
|
Publication #:
|
|
Pub Dt:
|
12/31/2015
| | | | |
Title:
|
VIRTUAL MACHINE BACKUP
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2017
|
Application #:
|
14727458
|
Filing Dt:
|
06/01/2015
|
Publication #:
|
|
Pub Dt:
|
12/01/2016
| | | | |
Title:
|
METHODS OF FORMING REPLACEMENT FINS FOR A FINFET DEVICE USING A TARGETED THICKNESS FOR THE PATTERNED FIN ETCH MASK
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|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
14728100
|
Filing Dt:
|
06/02/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
DESIGN OF TEMPERATURE-COMPLIANT INTEGRATED CIRCUITS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14729177
|
Filing Dt:
|
06/03/2015
|
Publication #:
|
|
Pub Dt:
|
10/20/2016
| | | | |
Title:
|
Automatic Analytical Cloud Scaling of Hardware Using Resource Sub-Cloud
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
14729188
|
Filing Dt:
|
06/03/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
14729298
|
Filing Dt:
|
06/03/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
14729342
|
Filing Dt:
|
06/03/2015
|
Publication #:
|
|
Pub Dt:
|
07/28/2016
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BACK-END-OF-THE-LINE INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2017
|
Application #:
|
14729845
|
Filing Dt:
|
06/03/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
METHOD AND STRUCTURE TO FORM TENSILE STRAINED SIGE FINS AND COMPRESSIVE STRAINED SIGE FINS ON A SAME SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2017
|
Application #:
|
14730294
|
Filing Dt:
|
06/04/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
DIODES AND FABRICATION METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2016
|
Application #:
|
14730320
|
Filing Dt:
|
06/04/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
SILICON GERMANIUM FIN
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2016
|
Application #:
|
14730375
|
Filing Dt:
|
06/04/2015
|
Publication #:
|
|
Pub Dt:
|
09/24/2015
| | | | |
Title:
|
Automating Capacity Upgrade on Demand
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|
|
Patent #:
|
|
Issue Dt:
|
08/28/2018
|
Application #:
|
14730503
|
Filing Dt:
|
06/04/2015
|
Publication #:
|
|
Pub Dt:
|
09/24/2015
| | | | |
Title:
|
Laser Surgical Apparatus and Methods of its Use Minimizing Damage During the Ablation of Tissue Using a Focused Ultrashort Pulsed Laser Beam Wherein the Slope of Fluence Breakdown is a Function of the Pulse Width
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|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14730735
|
Filing Dt:
|
06/04/2015
|
Title:
|
METHOD OF UNIFORM FIN RECESSING USING ISOTROPIC ETCH
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|
|
Patent #:
|
|
Issue Dt:
|
01/10/2017
|
Application #:
|
14731480
|
Filing Dt:
|
06/05/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
INTEGRATION OF HYBRID GERMANIUM AND GROUP III-V CONTACT EPILAYER IN CMOS
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|
|
Patent #:
|
|
Issue Dt:
|
07/18/2017
|
Application #:
|
14731569
|
Filing Dt:
|
06/05/2015
|
Publication #:
|
|
Pub Dt:
|
09/24/2015
| | | | |
Title:
|
GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH
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|
|
Patent #:
|
|
Issue Dt:
|
07/18/2017
|
Application #:
|
14731569
|
Filing Dt:
|
06/05/2015
|
Publication #:
|
|
Pub Dt:
|
09/24/2015
| | | | |
Title:
|
GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14731644
|
Filing Dt:
|
06/05/2015
|
Publication #:
|
|
Pub Dt:
|
09/24/2015
| | | | |
Title:
|
SEMICONDUCTOR DEVICES WITH A REPLACEMENT GATE STRUCTURE HAVING A RECESSED CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2016
|
Application #:
|
14731876
|
Filing Dt:
|
06/05/2015
|
Publication #:
|
|
Pub Dt:
|
12/17/2015
| | | | |
Title:
|
REPLACEMENT GATE STRUCTURE ON FINFET DEVICES WITH REDUCED SIZE FIN IN THE CHANNEL REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2017
|
Application #:
|
14731960
|
Filing Dt:
|
06/05/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
METHODS OF FORMING A GATE CONTACT ABOVE AN ACTIVE REGION OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2020
|
Application #:
|
14732038
|
Filing Dt:
|
06/05/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
METHODS OF FORMING V0 STRUCTURES FOR SEMICONDUCTOR DEVICES BY FORMING A PROTECTION LAYER WITH A NON-UNIFORM THICKNESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2016
|
Application #:
|
14732078
|
Filing Dt:
|
06/05/2015
|
Title:
|
METHODS OF FORMING V0 STRUCTURES FOR SEMICONDUCTOR DEVICES THAT INCLUDES RECESSING A CONTACT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2016
|
Application #:
|
14732689
|
Filing Dt:
|
06/06/2015
|
Publication #:
|
|
Pub Dt:
|
09/24/2015
| | | | |
Title:
|
FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14732705
|
Filing Dt:
|
06/06/2015
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14732835
|
Filing Dt:
|
06/08/2015
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14732938
|
Filing Dt:
|
06/08/2015
|
Publication #:
|
|
Pub Dt:
|
10/01/2015
| | | | |
Title:
|
FINFET DEVICES WITH DIFFERENT FIN HEIGHTS IN THE CHANNEL AND SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2017
|
Application #:
|
14733235
|
Filing Dt:
|
06/08/2015
|
Publication #:
|
|
Pub Dt:
|
09/24/2015
| | | | |
Title:
|
SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2017
|
Application #:
|
14733398
|
Filing Dt:
|
06/08/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
ELECTRONIC DEVICE INCLUDING MOAT POWER METALLIZATION IN TRENCH
|
|