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Reel/Frame:	056987/0001			Pages:	1045
		Recorded:	05/12/2021
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 18026
Page 156 of 181
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Patent #:	9330965	Issue Dt:	05/03/2016	Application #:	14837827	Filing Dt:	08/27/2015
Publication #:	US20150371896	Pub Dt:	12/24/2015
Title:	DOUBLE SELF ALIGNED VIA PATTERNING

Patent #:	NONE	Issue Dt:		Application #:	14838215	Filing Dt:	08/27/2015
Publication #:	US20170063357	Pub Dt:	03/02/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR USING TUNABLE TIMING CIRCUITS FOR FDSOI TECHNOLOGY

Patent #:	9613898	Issue Dt:	04/04/2017	Application #:	14838554	Filing Dt:	08/28/2015
Publication #:	US20170062333	Pub Dt:	03/02/2017
Title:	RAISED E-FUSE

Patent #:	10042969	Issue Dt:	08/07/2018	Application #:	14838705	Filing Dt:	08/28/2015
Publication #:	US20170061062	Pub Dt:	03/02/2017
Title:	RELIABILITY OF AN ELECTRONIC DEVICE

Patent #:	9698101	Issue Dt:	07/04/2017	Application #:	14839108	Filing Dt:	08/28/2015
Publication #:	US20170062325	Pub Dt:	03/02/2017
Title:	SELF-ALIGNED LOCAL INTERCONNECT TECHNOLOGY

Patent #:	9564486	Issue Dt:	02/07/2017	Application #:	14839378	Filing Dt:	08/28/2015
Publication #:	US20150372080	Pub Dt:	12/24/2015
Title:	SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET

Patent #:	9817927	Issue Dt:	11/14/2017	Application #:	14841037	Filing Dt:	08/31/2015
Publication #:	US20170061044	Pub Dt:	03/02/2017
Title:	HARD MASK ETCH AND DIELECTRIC ETCH AWARE OVERLAP FOR VIA AND METAL LAYERS

Patent #:	NONE	Issue Dt:		Application #:	14841508	Filing Dt:	08/31/2015
Publication #:	US20150371760	Pub Dt:	12/24/2015
Title:	HIGH EFFICIENCY ON-CHIP 3D TRANSFORMER STRUCTURE

Patent #:	9659785	Issue Dt:	05/23/2017	Application #:	14841951	Filing Dt:	09/01/2015
Publication #:	US20170062233	Pub Dt:	03/02/2017
Title:	FIN CUT FOR TAPER DEVICE

Patent #:	9666791	Issue Dt:	05/30/2017	Application #:	14841997	Filing Dt:	09/01/2015
Publication #:	US20160141489	Pub Dt:	05/19/2016
Title:	TOPOLOGICAL METHOD TO BUILD SELF-ALIGNED MTJ WITHOUT A MASK

Patent #:	9564447	Issue Dt:	02/07/2017	Application #:	14842345	Filing Dt:	09/01/2015
Publication #:	US20170062442	Pub Dt:	03/02/2017
Title:	METHODS FOR FABRICATING PROGRAMMABLE DEVICES AND RELATED STRUCTURES

Patent #:	9263290	Issue Dt:	02/16/2016	Application #:	14843085	Filing Dt:	09/02/2015
Publication #:	US20150380262	Pub Dt:	12/31/2015
Title:	SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH

Patent #:	9613862	Issue Dt:	04/04/2017	Application #:	14843109	Filing Dt:	09/02/2015
Publication #:	US20170062275	Pub Dt:	03/02/2017
Title:	CHAMFERLESS VIA STRUCTURES

Patent #:	9741625	Issue Dt:	08/22/2017	Application #:	14844163	Filing Dt:	09/03/2015
Publication #:	US20170069550	Pub Dt:	03/09/2017
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH STI STRUCTURES ON AN SOI SUBSTRATE

Patent #:	9704759	Issue Dt:	07/11/2017	Application #:	14845543	Filing Dt:	09/04/2015
Publication #:	US20170069547	Pub Dt:	03/09/2017
Title:	METHODS OF FORMING CMOS BASED INTEGRATED CIRCUIT PRODUCTS USING DISPOSABLE SPACERS

Patent #:	NONE	Issue Dt:		Application #:	14845896	Filing Dt:	09/04/2015
Publication #:	US20170069518	Pub Dt:	03/09/2017
Title:	ELECTROSTATIC SUBSTRATE HOLDER WITH NON-PLANAR SURFACE AND METHOD OF ETCHING

Patent #:	10038096	Issue Dt:	07/31/2018	Application #:	14847462	Filing Dt:	09/08/2015
Publication #:	US20170069759	Pub Dt:	03/09/2017
Title:	THREE-DIMENSIONAL FINFET TRANSISTOR WITH PORTION(S) OF THE FIN CHANNEL REMOVED IN GATE-LAST FLOW

Patent #:	9418935	Issue Dt:	08/16/2016	Application #:	14848558	Filing Dt:	09/09/2015
Title:	INTEGRATED CIRCUIT LINE ENDS FORMED USING ADDITIVE PROCESSING

Patent #:	10048311	Issue Dt:	08/14/2018	Application #:	14848804	Filing Dt:	09/09/2015
Publication #:	US20170067955	Pub Dt:	03/09/2017
Title:	DETECTION OF GATE-TO-SOURCE/DRAIN SHORTS

Patent #:	9564358	Issue Dt:	02/07/2017	Application #:	14849269	Filing Dt:	09/09/2015
Title:	FORMING RELIABLE CONTACTS ON TIGHT SEMICONDUCTOR PITCH

Patent #:	9478622	Issue Dt:	10/25/2016	Application #:	14849335	Filing Dt:	09/09/2015
Publication #:	US20150380502	Pub Dt:	12/31/2015
Title:	WRAP-AROUND CONTACT FOR FINFET

Patent #:	NONE	Issue Dt:		Application #:	14849483	Filing Dt:	09/09/2015
Publication #:	US20150380510	Pub Dt:	12/31/2015
Title:	STRUCTURE AND METHOD OF FORMING SILICIDE ON FINS

Patent #:	9589833	Issue Dt:	03/07/2017	Application #:	14850093	Filing Dt:	09/10/2015
Publication #:	US20170076978	Pub Dt:	03/16/2017
Title:	PREVENTING LEAKAGE INSIDE AIR-GAP SPACER DURING CONTACT FORMATION

Patent #:	9435947	Issue Dt:	09/06/2016	Application #:	14850381	Filing Dt:	09/10/2015
Publication #:	US20150378096	Pub Dt:	12/31/2015
Title:	INTEGRATION OF OPTICAL COMPONENTS IN INTEGRATED CIRCUITS BY SEPARATING TWO SUBSTRATES WITH AN INSULATION LAYER

Patent #:	10020395	Issue Dt:	07/10/2018	Application #:	14853012	Filing Dt:	09/14/2015
Publication #:	US20170077297	Pub Dt:	03/16/2017
Title:	SEMICONDUCTOR DEVICE WITH GATE INSIDE U-SHAPED CHANNEL AND METHODS OF MAKING SUCH A DEVICE

Patent #:	9711644	Issue Dt:	07/18/2017	Application #:	14853073	Filing Dt:	09/14/2015
Publication #:	US20170077301	Pub Dt:	03/16/2017
Title:	METHODS OF MAKING SOURCE/DRAIN REGIONS POSITIONED INSIDE U-SHAPED SEMICONDUCTOR MATERIAL USING SOURCE/DRAIN PLACEHOLDER STRUCTURES

Patent #:	9590118	Issue Dt:	03/07/2017	Application #:	14853146	Filing Dt:	09/14/2015
Publication #:	US20170077314	Pub Dt:	03/16/2017
Title:	WAFER WITH SOI STRUCTURE HAVING A BURIED INSULATING MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	14853303	Filing Dt:	09/14/2015
Publication #:	US20170077234	Pub Dt:	03/16/2017
Title:	DEVICES AND METHODS OF CREATING ELASTIC RELAXATION OF EPITAXIALLY GROWN LATTICE MISMATCHED FILMS

Patent #:	10049942	Issue Dt:	08/14/2018	Application #:	14853373	Filing Dt:	09/14/2015
Publication #:	US20170076991	Pub Dt:	03/16/2017
Title:	ASYMMETRIC SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME

Patent #:	NONE	Issue Dt:		Application #:	14853537	Filing Dt:	09/14/2015
Publication #:	US20160005657	Pub Dt:	01/07/2016
Title:	SEMICONDUCTOR STRUCTURE WITH INCREASED SPACE AND VOLUME BETWEEN SHAPED EPITAXIAL STRUCTURES

Patent #:	9553058	Issue Dt:	01/24/2017	Application #:	14854565	Filing Dt:	09/15/2015
Title:	WAFER BACKSIDE REDISTRIBUTION LAYER WARPAGE CONTROL

Patent #:	9412740	Issue Dt:	08/09/2016	Application #:	14855881	Filing Dt:	09/16/2015
Publication #:	US20160005733	Pub Dt:	01/07/2016
Title:	INTEGRATED CIRCUIT PRODUCT WITH A GATE HEIGHT REGISTRATION STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	14856065	Filing Dt:	09/16/2015
Publication #:	US20160005734	Pub Dt:	01/07/2016
Title:	INTEGRATED CIRCUIT PRODUCT COMPRISED OF MULTIPLE P-TYPE SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES

Patent #:	9903707	Issue Dt:	02/27/2018	Application #:	14857914	Filing Dt:	09/18/2015
Publication #:	US20170082423	Pub Dt:	03/23/2017
Title:	THREE-DIMENSIONAL SCATTEROMETRY FOR MEASURING DIELECTRIC THICKNESS

Patent #:	9508597	Issue Dt:	11/29/2016	Application #:	14858154	Filing Dt:	09/18/2015
Title:	3D FIN TUNNELING FIELD EFFECT TRANSISTOR

Patent #:	9564350	Issue Dt:	02/07/2017	Application #:	14858475	Filing Dt:	09/18/2015
Title:	METHOD AND APPARATUS FOR STORING AND TRANSPORTING SEMICONDUCTOR WAFERS IN A VACUUM POD

Patent #:	NONE	Issue Dt:		Application #:	14859729	Filing Dt:	09/21/2015
Publication #:	US20160013291	Pub Dt:	01/14/2016
Title:	METHODS OF FORMING ISOLATED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9704881	Issue Dt:	07/11/2017	Application #:	14859914	Filing Dt:	09/21/2015
Publication #:	US20170084629	Pub Dt:	03/23/2017
Title:	SEMICONDUCTOR DEVICE WITH REDUCED POLY SPACING EFFECT

Patent #:	9614058	Issue Dt:	04/04/2017	Application #:	14860276	Filing Dt:	09/21/2015
Publication #:	US20160013296	Pub Dt:	01/14/2016
Title:	METHODS OF FORMING LOW DEFECT REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES

Patent #:	NONE	Issue Dt:		Application #:	14860755	Filing Dt:	09/22/2015
Publication #:	US20160027713	Pub Dt:	01/28/2016
Title:	ESTABLISHING A THERMAL PROFILE ACROSS A SEMICONDUCTOR CHIP

Patent #:	9437501	Issue Dt:	09/06/2016	Application #:	14861326	Filing Dt:	09/22/2015
Title:	STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)

Patent #:	9576954	Issue Dt:	02/21/2017	Application #:	14862258	Filing Dt:	09/23/2015
Title:	NEW POC PROCESS FLOW FOR CONFORMAL RECESS FILL

Patent #:	9435852	Issue Dt:	09/06/2016	Application #:	14862587	Filing Dt:	09/23/2015
Title:	INTEGRATED CIRCUIT (IC) TEST STRUCTURE WITH MONITOR CHAIN AND TEST WIRES

Patent #:	9735111	Issue Dt:	08/15/2017	Application #:	14862894	Filing Dt:	09/23/2015
Publication #:	US20170084537	Pub Dt:	03/23/2017
Title:	DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD

Patent #:	NONE	Issue Dt:		Application #:	14864191	Filing Dt:	09/24/2015
Publication #:	US20160012952	Pub Dt:	01/14/2016
Title:	INDUCTOR STRUCTURE HAVING EMBEDDED AIRGAP

Patent #:	9601428	Issue Dt:	03/21/2017	Application #:	14865589	Filing Dt:	09/25/2015
Publication #:	US20160284643	Pub Dt:	09/29/2016
Title:	SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF

Patent #:	NONE	Issue Dt:		Application #:	14865784	Filing Dt:	09/25/2015
Publication #:	US20160049399	Pub Dt:	02/18/2016
Title:	GATE STRUCTURES FOR SEMICONDUCTOR DEVICES WITH A CONDUCTIVE ETCH STOP LAYER

Patent #:	9268491	Issue Dt:	02/23/2016	Application #:	14866531	Filing Dt:	09/25/2015
Publication #:	US20160019001	Pub Dt:	01/21/2016
Title:	THICK AND THIN DATA VOLUME MANAGEMENT

Patent #:	NONE	Issue Dt:		Application #:	14866878	Filing Dt:	09/26/2015
Publication #:	US20160035743	Pub Dt:	02/04/2016
Title:	FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE

Patent #:	9691897	Issue Dt:	06/27/2017	Application #:	14867193	Filing Dt:	09/28/2015
Publication #:	US20170092764	Pub Dt:	03/30/2017
Title:	THREE-DIMENSIONAL SEMICONDUCTOR TRANSISTOR WITH GATE CONTACT IN ACTIVE REGION

Patent #:	9691497	Issue Dt:	06/27/2017	Application #:	14867331	Filing Dt:	09/28/2015
Publication #:	US20170092373	Pub Dt:	03/30/2017
Title:	PROGRAMMABLE DEVICES WITH CURRENT-FACILITATED MIGRATION AND FABRICATION METHODS

Patent #:	9812393	Issue Dt:	11/07/2017	Application #:	14867341	Filing Dt:	09/28/2015
Publication #:	US20170092583	Pub Dt:	03/30/2017
Title:	PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF

Patent #:	10797188	Issue Dt:	10/06/2020	Application #:	14867675	Filing Dt:	09/28/2015
Publication #:	US20160020353	Pub Dt:	01/21/2016
Title:	OPTICAL SEMICONDUCTOR STRUCTURE FOR EMITTING LIGHT THROUGH APERTURE

Patent #:	9397200	Issue Dt:	07/19/2016	Application #:	14867800	Filing Dt:	09/28/2015
Publication #:	US20160118472	Pub Dt:	04/28/2016
Title:	METHODS OF FORMING 3D DEVICES WITH DIELECTRIC ISOLATION AND A STRAINED CHANNEL REGION

Patent #:	9536981	Issue Dt:	01/03/2017	Application #:	14868414	Filing Dt:	09/29/2015
Title:	FIELD EFFECT TRANSISTOR DEVICE SPACERS

Patent #:	9543297	Issue Dt:	01/10/2017	Application #:	14869397	Filing Dt:	09/29/2015
Title:	FIN-FET REPLACEMENT METAL GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Patent #:	9536750	Issue Dt:	01/03/2017	Application #:	14870932	Filing Dt:	09/30/2015
Title:	METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME

Patent #:	9620587	Issue Dt:	04/11/2017	Application #:	14871181	Filing Dt:	09/30/2015
Publication #:	US20160020204	Pub Dt:	01/21/2016
Title:	THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE

Patent #:	9455316	Issue Dt:	09/27/2016	Application #:	14871289	Filing Dt:	09/30/2015
Publication #:	US20160020277	Pub Dt:	01/21/2016
Title:	THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE

Patent #:	9972550	Issue Dt:	05/15/2018	Application #:	14873677	Filing Dt:	10/02/2015
Publication #:	US20170098585	Pub Dt:	04/06/2017
Title:	SOURCE/DRAIN EPITAXIAL ELECTRICAL MONITOR

Patent #:	9608096	Issue Dt:	03/28/2017	Application #:	14874039	Filing Dt:	10/02/2015
Publication #:	US20170098699	Pub Dt:	04/06/2017
Title:	IMPLEMENTING STRESS IN A BIPOLAR JUNCTION TRANSISTOR

Patent #:	10128114	Issue Dt:	11/13/2018	Application #:	14874623	Filing Dt:	10/05/2015
Publication #:	US20170098544	Pub Dt:	04/06/2017
Title:	AMORPHIZATION INDUCED METAL-SILICON CONTACT FORMATION

Patent #:	9754911	Issue Dt:	09/05/2017	Application #:	14875032	Filing Dt:	10/05/2015
Publication #:	US20170098623	Pub Dt:	04/06/2017
Title:	IC STRUCTURE WITH ANGLED INTERCONNECT ELEMENTS

Patent #:	NONE	Issue Dt:		Application #:	14875917	Filing Dt:	10/06/2015
Publication #:	US20160035641	Pub Dt:	02/04/2016
Title:	SEMICONDUCTOR DEVICE INCLUDING PASSIVATION LAYER ENCAPSULANT

Patent #:	9559009	Issue Dt:	01/31/2017	Application #:	14876212	Filing Dt:	10/06/2015
Publication #:	US20160027700	Pub Dt:	01/28/2016
Title:	GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS

Patent #:	9691787	Issue Dt:	06/27/2017	Application #:	14878332	Filing Dt:	10/08/2015
Publication #:	US20170104011	Pub Dt:	04/13/2017
Title:	CO-FABRICATED BULK DEVICES AND SEMICONDUCTOR-ON-INSULATOR DEVICES

Patent #:	9478625	Issue Dt:	10/25/2016	Application #:	14878440	Filing Dt:	10/08/2015
Title:	METAL RESISTOR USING FINFET-BASED REPLACEMENT GATE PROCESS

Patent #:	9818873	Issue Dt:	11/14/2017	Application #:	14879220	Filing Dt:	10/09/2015
Publication #:	US20170104100	Pub Dt:	04/13/2017
Title:	FORMING STRESSED EPITAXIAL LAYERS BETWEEN GATES SEPARATED BY DIFFERENT PITCHES

Patent #:	9470712	Issue Dt:	10/18/2016	Application #:	14879645	Filing Dt:	10/09/2015
Title:	APPARATUS AND METHOD FOR ATOMIC FORCE PROBING/SEM NANO-PROBING/SCANNING PROBE MICROSCOPY AND COLLIMATED ION MILLING

Patent #:	10622457	Issue Dt:	04/14/2020	Application #:	14879968	Filing Dt:	10/09/2015
Publication #:	US20170104082	Pub Dt:	04/13/2017
Title:	FORMING REPLACEMENT LOW-K SPACER IN TIGHT PITCH FIN FIELD EFFECT TRANSISTORS

Patent #:	9397175	Issue Dt:	07/19/2016	Application #:	14881766	Filing Dt:	10/13/2015
Publication #:	US20160035841	Pub Dt:	02/04/2016
Title:	MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS

Patent #:	NONE	Issue Dt:		Application #:	14882308	Filing Dt:	10/13/2015
Publication #:	US20160035728	Pub Dt:	02/04/2016
Title:	RETROGRADE DOPED LAYER FOR DEVICE ISOLATION

Patent #:	9852954	Issue Dt:	12/26/2017	Application #:	14882640	Filing Dt:	10/14/2015
Publication #:	US20160035630	Pub Dt:	02/04/2016
Title:	METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	14882869	Filing Dt:	10/14/2015
Publication #:	US20170110376	Pub Dt:	04/20/2017
Title:	STRUCTURES WITH THINNED DIELECTRIC MATERIAL

Patent #:	NONE	Issue Dt:		Application #:	14885080	Filing Dt:	10/16/2015
Publication #:	US20160043046	Pub Dt:	02/11/2016
Title:	ETCHING OF UNDER BUMP METALLIZATION LAYER AND RESULTING DEVICE

Patent #:	9589806	Issue Dt:	03/07/2017	Application #:	14886424	Filing Dt:	10/19/2015
Title:	INTEGRATED CIRCUIT WITH REPLACEMENT GATE STACKS AND METHOD OF FORMING SAME

Patent #:	9660027	Issue Dt:	05/23/2017	Application #:	14887572	Filing Dt:	10/20/2015
Publication #:	US20170110539	Pub Dt:	04/20/2017
Title:	EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR

Patent #:	9735242	Issue Dt:	08/15/2017	Application #:	14887927	Filing Dt:	10/20/2015
Publication #:	US20170110549	Pub Dt:	04/20/2017
Title:	SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

Patent #:	9633948	Issue Dt:	04/25/2017	Application #:	14887984	Filing Dt:	10/20/2015
Publication #:	US20160111374	Pub Dt:	04/21/2016
Title:	LOW ENERGY ETCH PROCESS FOR NITROGEN-CONTAINING DIELECTRIC LAYER

Patent #:	9711513	Issue Dt:	07/18/2017	Application #:	14918048	Filing Dt:	10/20/2015
Publication #:	US20170047336	Pub Dt:	02/16/2017
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF

Patent #:	10049570	Issue Dt:	08/14/2018	Application #:	14918776	Filing Dt:	10/21/2015
Publication #:	US20170116849	Pub Dt:	04/27/2017
Title:	CONTROLLING RIGHT-OF-WAY FOR PRIORITY VEHICLES

Patent #:	9875905	Issue Dt:	01/23/2018	Application #:	14920179	Filing Dt:	10/22/2015
Publication #:	US20170117156	Pub Dt:	04/27/2017
Title:	FINFET DEVICES HAVING FINS WITH A TAPERED CONFIGURATION AND METHODS OF FABRICATING THE SAME

Patent #:	10032884	Issue Dt:	07/24/2018	Application #:	14920354	Filing Dt:	10/22/2015
Publication #:	US20170117274	Pub Dt:	04/27/2017
Title:	UNMERGED EPITAXIAL PROCESS FOR FINFET DEVICES WITH AGGRESSIVE FIN PITCH SCALING

Patent #:	10228685	Issue Dt:	03/12/2019	Application #:	14920376	Filing Dt:	10/22/2015
Publication #:	US20170115658	Pub Dt:	04/27/2017
Title:	Use of Multivariate Models to Control Manufacturing Operations

Patent #:	NONE	Issue Dt:		Application #:	14920721	Filing Dt:	10/22/2015
Publication #:	US20160044023	Pub Dt:	02/11/2016
Title:	AUTHENTICATION POLICY ENFORCEMENT

Patent #:	9722045	Issue Dt:	08/01/2017	Application #:	14921434	Filing Dt:	10/23/2015
Publication #:	US20170117387	Pub Dt:	04/27/2017
Title:	BUFFER LAYER FOR MODULATING Vt ACROSS DEVICES

Patent #:	NONE	Issue Dt:		Application #:	14922457	Filing Dt:	10/26/2015
Publication #:	US20160043202	Pub Dt:	02/11/2016
Title:	SELF-ALIGNED BIPOLAR JUNCTION TRANSISTOR HAVING SELF-PLANARIZING ISOLATION RAISED BASE STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	14922549	Filing Dt:	10/26/2015
Publication #:	US20160043223	Pub Dt:	02/11/2016
Title:	FINFET SEMICONDUCTOR DEVICES WITH STRESSED LAYERS

Patent #:	10078107	Issue Dt:	09/18/2018	Application #:	14924439	Filing Dt:	10/27/2015
Publication #:	US20170115337	Pub Dt:	04/27/2017
Title:	WAFER LEVEL ELECTRICAL TEST FOR OPTICAL PROXIMITY CORRECTION AND/OR ETCH BIAS

Patent #:	9362284	Issue Dt:	06/07/2016	Application #:	14924486	Filing Dt:	10/27/2015
Publication #:	US20160049400	Pub Dt:	02/18/2016
Title:	THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES

Patent #:	9947774	Issue Dt:	04/17/2018	Application #:	14925630	Filing Dt:	10/28/2015
Publication #:	US20170125551	Pub Dt:	05/04/2017
Title:	FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH DUAL STRAINED CHANNELS WITH SOLID PHASE DOPING

Patent #:	NONE	Issue Dt:		Application #:	14925690	Filing Dt:	10/28/2015
Publication #:	US20160049503	Pub Dt:	02/18/2016
Title:	BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE

Patent #:	9660040	Issue Dt:	05/23/2017	Application #:	14926657	Filing Dt:	10/29/2015
Publication #:	US20160049481	Pub Dt:	02/18/2016
Title:	TRANSISTOR CONTACTS SELF-ALIGNED TWO DIMENSIONS

Patent #:	9754903	Issue Dt:	09/05/2017	Application #:	14926880	Filing Dt:	10/29/2015
Publication #:	US20170125361	Pub Dt:	05/04/2017
Title:	SEMICONDUCTOR STRUCTURE WITH ANTI-EFUSE DEVICE

Patent #:	9741853	Issue Dt:	08/22/2017	Application #:	14926897	Filing Dt:	10/29/2015
Publication #:	US20170125587	Pub Dt:	05/04/2017
Title:	STRESS MEMORIZATION TECHNIQUES FOR TRANSISTOR DEVICES

Patent #:	9570555	Issue Dt:	02/14/2017	Application #:	14926936	Filing Dt:	10/29/2015
Title:	SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES

Patent #:	9853110	Issue Dt:	12/26/2017	Application #:	14927765	Filing Dt:	10/30/2015
Publication #:	US20170125530	Pub Dt:	05/04/2017
Title:	METHOD OF FORMING A GATE CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE

Patent #:	9601392	Issue Dt:	03/21/2017	Application #:	14927943	Filing Dt:	10/30/2015
Title:	DEVICE CHARACTERIZATION BY TIME DEPENDENT CHARGING DYNAMICS

Patent #:	NONE	Issue Dt:		Application #:	14928057	Filing Dt:	10/30/2015
Publication #:	US20160099344	Pub Dt:	04/07/2016
Title:	FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS

100

Patent #:	NONE	Issue Dt:		Application #:	14928088	Filing Dt:	10/30/2015
Publication #:	US20160047058	Pub Dt:	02/18/2016
Title:	METAL PLATING SYSTEM INCLUDING GAS BUBBLE REMOVAL UNIT

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

440 STONE BREAK ROAD EXTENSION

MALTA, NEW YORK 12020

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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