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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 157 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
10115719
Issue Dt:
10/30/2018
Application #:
14928272
Filing Dt:
10/30/2015
Publication #:
US20160126239
Pub Dt:
05/05/2016
Title:
INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM MIM CAPACITOR MATERIAL AND METHODS FOR FABRICATING SAME
2
Patent #:
9960284
Issue Dt:
05/01/2018
Application #:
14928595
Filing Dt:
10/30/2015
Publication #:
US20170125610
Pub Dt:
05/04/2017
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A VARACTOR
3
Patent #:
9551674
Issue Dt:
01/24/2017
Application #:
14928605
Filing Dt:
10/30/2015
Title:
METHOD OF PRODUCING AN UN-DISTORTED DARK FIELD STRAIN MAP AT HIGH SPATIAL RESOLUTION THROUGH DARK FIELD ELECTRON HOLOGRAPHY
4
Patent #:
10199479
Issue Dt:
02/05/2019
Application #:
14928681
Filing Dt:
10/30/2015
Publication #:
US20160056263
Pub Dt:
02/25/2016
Title:
METHODS OF FORMING A GATE CAP LAYER ABOVE A REPLACEMENT GATE STRUCTURE
5
Patent #:
9923078
Issue Dt:
03/20/2018
Application #:
14928719
Filing Dt:
10/30/2015
Publication #:
US20170125543
Pub Dt:
05/04/2017
Title:
TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS
6
Patent #:
9530553
Issue Dt:
12/27/2016
Application #:
14929869
Filing Dt:
11/02/2015
Title:
HIGH PERFORMANCE INDUCTOR/TRANSFORMER AND METHODS OF MAKING SUCH INDUCTOR/TRANSFORMER STRUCTURES
7
Patent #:
9536982
Issue Dt:
01/03/2017
Application #:
14930895
Filing Dt:
11/03/2015
Title:
ETCH STOP FOR AIRGAP PROTECTION
8
Patent #:
9484255
Issue Dt:
11/01/2016
Application #:
14930933
Filing Dt:
11/03/2015
Title:
HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS
9
Patent #:
NONE
Issue Dt:
Application #:
14931277
Filing Dt:
11/03/2015
Publication #:
US20160064250
Pub Dt:
03/03/2016
Title:
METHODS OF FORMING METASTABLE REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE BY PERFORMING A REPLACEMENT GROWTH PROCESS
10
Patent #:
10161915
Issue Dt:
12/25/2018
Application #:
14932372
Filing Dt:
11/04/2015
Publication #:
US20170122913
Pub Dt:
05/04/2017
Title:
IN-SITU CONTACTLESS MONITORING OF PHOTOMASK PELLICLE DEGRADATION
11
Patent #:
9419101
Issue Dt:
08/16/2016
Application #:
14932394
Filing Dt:
11/04/2015
Title:
MULTI-LAYER SPACER USED IN FINFET
12
Patent #:
NONE
Issue Dt:
Application #:
14932409
Filing Dt:
11/04/2015
Publication #:
US20160056106
Pub Dt:
02/25/2016
Title:
STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME
13
Patent #:
10263065
Issue Dt:
04/16/2019
Application #:
14932441
Filing Dt:
11/04/2015
Publication #:
US20170125509
Pub Dt:
05/04/2017
Title:
METAL RESISTOR FORMING METHOD USING ION IMPLANTATION
14
Patent #:
9673115
Issue Dt:
06/06/2017
Application #:
14933107
Filing Dt:
11/05/2015
Publication #:
US20170133287
Pub Dt:
05/11/2017
Title:
TEST STRUCTURES AND METHOD OF FORMING AN ACCORDING TEST STRUCTURE
15
Patent #:
NONE
Issue Dt:
Application #:
14933501
Filing Dt:
11/05/2015
Publication #:
US20160056238
Pub Dt:
02/25/2016
Title:
RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH
16
Patent #:
9537006
Issue Dt:
01/03/2017
Application #:
14933557
Filing Dt:
11/05/2015
Publication #:
US20160056288
Pub Dt:
02/25/2016
Title:
CIRCUIT ELEMENT INCLUDING A LAYER OF A STRESS-CREATING MATERIAL PROVIDING A VARIABLE STRESS
17
Patent #:
9905460
Issue Dt:
02/27/2018
Application #:
14933650
Filing Dt:
11/05/2015
Publication #:
US20170133325
Pub Dt:
05/11/2017
Title:
METHODS OF SELF-FORMING BARRIER FORMATION IN METAL INTERCONNECTION APPLICATIONS
18
Patent #:
9798088
Issue Dt:
10/24/2017
Application #:
14933668
Filing Dt:
11/05/2015
Publication #:
US20170131476
Pub Dt:
05/11/2017
Title:
BARRIER STRUCTURES FOR UNDERFILL BLOCKOUT REGIONS
19
Patent #:
NONE
Issue Dt:
Application #:
14934042
Filing Dt:
11/05/2015
Publication #:
US20170133406
Pub Dt:
05/11/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR STACKED CMOS LOGIC CIRCUITS ON FINS
20
Patent #:
9368513
Issue Dt:
06/14/2016
Application #:
14934369
Filing Dt:
11/06/2015
Publication #:
US20160071886
Pub Dt:
03/10/2016
Title:
HIGHLY CONFORMAL EXTENSION DOPING IN ADVANCED MULTI-GATE DEVICES
21
Patent #:
9906213
Issue Dt:
02/27/2018
Application #:
14934793
Filing Dt:
11/06/2015
Publication #:
US20170133923
Pub Dt:
05/11/2017
Title:
REDUCING THERMAL RUNAWAY IN INVERTER DEVICES
22
Patent #:
9466505
Issue Dt:
10/11/2016
Application #:
14935767
Filing Dt:
11/09/2015
Publication #:
US20160064236
Pub Dt:
03/03/2016
Title:
METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS
23
Patent #:
9659862
Issue Dt:
05/23/2017
Application #:
14936582
Filing Dt:
11/09/2015
Publication #:
US20170133319
Pub Dt:
05/11/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES
24
Patent #:
9548318
Issue Dt:
01/17/2017
Application #:
14936848
Filing Dt:
11/10/2015
Title:
CONNECTING TO BACK-PLATE CONTACTS OR DIODE JUNCTIONS THROUGH A RMG ELECTRODE AND RESULTING DEVICES
25
Patent #:
9548312
Issue Dt:
01/17/2017
Application #:
14937041
Filing Dt:
11/10/2015
Title:
METHOD INCLUDING A FORMATION OF A CONTROL GATE OF A NONVOLATILE MEMORY CELL AND SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL
26
Patent #:
9704807
Issue Dt:
07/11/2017
Application #:
14939251
Filing Dt:
11/12/2015
Publication #:
US20170141035
Pub Dt:
05/18/2017
Title:
PATTERN PLACEMENT ERROR COMPENSATION LAYER
27
Patent #:
9748176
Issue Dt:
08/29/2017
Application #:
14939319
Filing Dt:
11/12/2015
Publication #:
US20170141036
Pub Dt:
05/18/2017
Title:
PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING
28
Patent #:
9754829
Issue Dt:
09/05/2017
Application #:
14939464
Filing Dt:
11/12/2015
Publication #:
US20170140985
Pub Dt:
05/18/2017
Title:
SELF-ALIGNED CONDUCTIVE POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER
29
Patent #:
9472558
Issue Dt:
10/18/2016
Application #:
14940499
Filing Dt:
11/13/2015
Title:
SEMICONDUCTOR STRUCTURES WITH STACKED NON-PLANAR FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE STRUCTURES
30
Patent #:
9799767
Issue Dt:
10/24/2017
Application #:
14940597
Filing Dt:
11/13/2015
Publication #:
US20170141226
Pub Dt:
05/18/2017
Title:
METHODS OF FORMING PMOS AND NMOS FINFET DEVICES ON CMOS BASED INTEGRATED CIRCUIT PRODUCTS
31
Patent #:
9748387
Issue Dt:
08/29/2017
Application #:
14940655
Filing Dt:
11/13/2015
Publication #:
US20170141227
Pub Dt:
05/18/2017
Title:
METHODS OF FORMING PMOS FINFET DEVICES AND MULTIPLE NMOS FINFET DEVICES WITH DIFFERENT PERFORMANCE CHARACTERISTICS
32
Patent #:
9740101
Issue Dt:
08/22/2017
Application #:
14940857
Filing Dt:
11/13/2015
Publication #:
US20170139324
Pub Dt:
05/18/2017
Title:
ADDITIONS OF ORGANIC SPECIES TO FACILITATE CROSSLINKER REMOVAL DURING PSPI CURE
33
Patent #:
9966182
Issue Dt:
05/08/2018
Application #:
14942311
Filing Dt:
11/16/2015
Publication #:
US20170140865
Pub Dt:
05/18/2017
Title:
MULTI-FREQUENCY INDUCTORS WITH LOW-K DIELECTRIC AREA
34
Patent #:
9412616
Issue Dt:
08/09/2016
Application #:
14942448
Filing Dt:
11/16/2015
Title:
METHODS OF FORMING SINGLE AND DOUBLE DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS
35
Patent #:
9798244
Issue Dt:
10/24/2017
Application #:
14943086
Filing Dt:
11/17/2015
Publication #:
US20170139330
Pub Dt:
05/18/2017
Title:
METHODS, APPARATUS, AND SYSTEMS FOR MINIMIZING DEFECTIVITY IN TOP-COAT-FREE LITHOGRAPHY AND IMPROVING RETICLE CD UNIFORMITY
36
Patent #:
NONE
Issue Dt:
Application #:
14943522
Filing Dt:
11/17/2015
Publication #:
US20160071928
Pub Dt:
03/10/2016
Title:
METHODS OF FORMING GATE STRUCTURES FOR FINFET DEVICES AND THE RESULTING SEMICONDUCTOR PRODUCTS
37
Patent #:
9484306
Issue Dt:
11/01/2016
Application #:
14943663
Filing Dt:
11/17/2015
Title:
MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT
38
Patent #:
9502308
Issue Dt:
11/22/2016
Application #:
14944659
Filing Dt:
11/18/2015
Title:
METHODS FOR FORMING TRANSISTOR DEVICES WITH DIFFERENT SOURCE/DRAIN CONTACT LINERS AND THE RESULTING DEVICES
39
Patent #:
9484459
Issue Dt:
11/01/2016
Application #:
14944833
Filing Dt:
11/18/2015
Publication #:
US20160071978
Pub Dt:
03/10/2016
Title:
PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL ON THE BASIS OF A SEED LAYER
40
Patent #:
10191108
Issue Dt:
01/29/2019
Application #:
14945520
Filing Dt:
11/19/2015
Publication #:
US20170146592
Pub Dt:
05/25/2017
Title:
ON-CHIP SENSOR FOR MONITORING ACTIVE CIRCUITS ON INTEGRATED CIRCUIT (IC) CHIPS
41
Patent #:
9607973
Issue Dt:
03/28/2017
Application #:
14946162
Filing Dt:
11/19/2015
Title:
METHOD FOR ESTABLISHING INTERCONNECTS IN PACKAGES USING THIN INTERPOSERS
42
Patent #:
9553061
Issue Dt:
01/24/2017
Application #:
14946208
Filing Dt:
11/19/2015
Title:
WIRING BOND PAD STRUCTURES
43
Patent #:
NONE
Issue Dt:
Application #:
14947259
Filing Dt:
11/20/2015
Publication #:
US20160079168
Pub Dt:
03/17/2016
Title:
INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS
44
Patent #:
9679807
Issue Dt:
06/13/2017
Application #:
14948214
Filing Dt:
11/20/2015
Publication #:
US20170148669
Pub Dt:
05/25/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR MOL INTERCONNECTS WITHOUT TITANIUM LINER
45
Patent #:
9368453
Issue Dt:
06/14/2016
Application #:
14948476
Filing Dt:
11/23/2015
Publication #:
US20160079180
Pub Dt:
03/17/2016
Title:
OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION
46
Patent #:
9590028
Issue Dt:
03/07/2017
Application #:
14948587
Filing Dt:
11/23/2015
Publication #:
US20160079342
Pub Dt:
03/17/2016
Title:
METHOD AND DEVICE FOR AN INTEGRATED TRENCH CAPACITOR
47
Patent #:
NONE
Issue Dt:
Application #:
14948977
Filing Dt:
11/23/2015
Publication #:
US20160079397
Pub Dt:
03/17/2016
Title:
PARTIAL FIN ON OXIDE FOR IMPROVED ELECTRICAL ISOLATION OF RAISED ACTIVE REGIONS
48
Patent #:
9606604
Issue Dt:
03/28/2017
Application #:
14951544
Filing Dt:
11/25/2015
Title:
ENERGY EFFICIENT HIGH-SPEED LINK AND METHOD TO MAXIMIZE ENERGY SAVINGS ON THE ENERGY EFFICIENT HIGH-SPEED LINK
49
Patent #:
9535807
Issue Dt:
01/03/2017
Application #:
14951815
Filing Dt:
11/25/2015
Publication #:
US20160077939
Pub Dt:
03/17/2016
Title:
RECOVERING FROM UNCORRECTED MEMORY ERRORS
50
Patent #:
9660050
Issue Dt:
05/23/2017
Application #:
14952549
Filing Dt:
11/25/2015
Publication #:
US20170148894
Pub Dt:
05/25/2017
Title:
REPLACEMENT LOW-K SPACER
51
Patent #:
9767300
Issue Dt:
09/19/2017
Application #:
14953426
Filing Dt:
11/30/2015
Publication #:
US20160085983
Pub Dt:
03/24/2016
Title:
MANAGING RESTRICTED TAGGED CONTENT ELEMENTS WITHIN A PUBLISHED MESSAGE
52
Patent #:
9825094
Issue Dt:
11/21/2017
Application #:
14953702
Filing Dt:
11/30/2015
Publication #:
US20170054005
Pub Dt:
02/23/2017
Title:
FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS
53
Patent #:
9741847
Issue Dt:
08/22/2017
Application #:
14953874
Filing Dt:
11/30/2015
Publication #:
US20170154994
Pub Dt:
06/01/2017
Title:
METHODS OF FORMING A CONTACT STRUCTURE FOR A VERTICAL CHANNEL SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
54
Patent #:
9520392
Issue Dt:
12/13/2016
Application #:
14954050
Filing Dt:
11/30/2015
Title:
SEMICONDUCTOR DEVICE INCLUDING FINFET AND FIN VARACTOR
55
Patent #:
NONE
Issue Dt:
Application #:
14954053
Filing Dt:
11/30/2015
Publication #:
US20170154763
Pub Dt:
06/01/2017
Title:
MASS SPECTROMETRY SYSTEM AND METHOD FOR CONTAMINANT IDENTIFICATION IN SEMICONDUCTOR FABRICATION
56
Patent #:
NONE
Issue Dt:
Application #:
14954112
Filing Dt:
11/30/2015
Publication #:
US20170154816
Pub Dt:
06/01/2017
Title:
AMORPHOUS METAL INTERCONNECTIONS BY SUBTRACTIVE ETCH
57
Patent #:
NONE
Issue Dt:
Application #:
14954151
Filing Dt:
11/30/2015
Publication #:
US20170154687
Pub Dt:
06/01/2017
Title:
SRAM-LIKE EBI STRUCTURE DESIGN AND IMPLEMENTATION TO CAPTURE MOSFET SOURCE-DRAIN LEAKAGE EARILER
58
Patent #:
9761720
Issue Dt:
09/12/2017
Application #:
14954166
Filing Dt:
11/30/2015
Publication #:
US20170154995
Pub Dt:
06/01/2017
Title:
REPLACEMENT BODY FINFET FOR IMPROVED JUNCTION PROFILE WITH GATE SELF-ALIGNED JUNCTIONS
59
Patent #:
9466567
Issue Dt:
10/11/2016
Application #:
14957842
Filing Dt:
12/03/2015
Publication #:
US20160086886
Pub Dt:
03/24/2016
Title:
NANOWIRE COMPATIBLE E-FUSE
60
Patent #:
9728506
Issue Dt:
08/08/2017
Application #:
14957860
Filing Dt:
12/03/2015
Publication #:
US20170162508
Pub Dt:
06/08/2017
Title:
STRAIN ENGINEERING DEVICES USING PARTIAL DEPTH FILMS IN THROUGH-SUBSTRATE VIAS
61
Patent #:
NONE
Issue Dt:
Application #:
14958150
Filing Dt:
12/03/2015
Publication #:
US20170162557
Pub Dt:
06/08/2017
Title:
TRENCH BASED CHARGE PUMP DEVICE
62
Patent #:
NONE
Issue Dt:
Application #:
14958224
Filing Dt:
12/03/2015
Publication #:
US20170162430
Pub Dt:
06/08/2017
Title:
METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AIR GAPS AND INTEGRATED CIRCUITS PRODUCED FROM SUCH METHODS
63
Patent #:
9653566
Issue Dt:
05/16/2017
Application #:
14958345
Filing Dt:
12/03/2015
Publication #:
US20160087073
Pub Dt:
03/24/2016
Title:
BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION
64
Patent #:
NONE
Issue Dt:
Application #:
14958491
Filing Dt:
12/03/2015
Publication #:
US20160082566
Pub Dt:
03/24/2016
Title:
WAFER SLIP DETECTION DURING CMP PROCESSING
65
Patent #:
9859382
Issue Dt:
01/02/2018
Application #:
14959825
Filing Dt:
12/04/2015
Publication #:
US20170162656
Pub Dt:
06/08/2017
Title:
INTEGRATED CMOS WAFERS
66
Patent #:
9425108
Issue Dt:
08/23/2016
Application #:
14960378
Filing Dt:
12/05/2015
Title:
METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
67
Patent #:
9590074
Issue Dt:
03/07/2017
Application #:
14960380
Filing Dt:
12/05/2015
Title:
METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
68
Patent #:
NONE
Issue Dt:
Application #:
14961566
Filing Dt:
12/07/2015
Publication #:
US20160086952
Pub Dt:
03/24/2016
Title:
PREVENTING EPI DAMAGE FOR CAP NITRIDE STRIP SCHEME IN A FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET) DEVICE
69
Patent #:
9773867
Issue Dt:
09/26/2017
Application #:
14962015
Filing Dt:
12/08/2015
Publication #:
US20160093692
Pub Dt:
03/31/2016
Title:
FINFET SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES
70
Patent #:
9704971
Issue Dt:
07/11/2017
Application #:
14963397
Filing Dt:
12/09/2015
Publication #:
US20170170291
Pub Dt:
06/15/2017
Title:
EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES
71
Patent #:
NONE
Issue Dt:
Application #:
14963683
Filing Dt:
12/09/2015
Publication #:
US20160093739
Pub Dt:
03/31/2016
Title:
FINFET SEMICONDUCTOR DEVICE WITH ISOLATED CHANNEL REGIONS
72
Patent #:
9461128
Issue Dt:
10/04/2016
Application #:
14963789
Filing Dt:
12/09/2015
Publication #:
US20160093704
Pub Dt:
03/31/2016
Title:
METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS
73
Patent #:
NONE
Issue Dt:
Application #:
14964228
Filing Dt:
12/09/2015
Publication #:
US20170170048
Pub Dt:
06/15/2017
Title:
WAFER HANDLER FOR INFRARED LASER RELEASE
74
Patent #:
9589850
Issue Dt:
03/07/2017
Application #:
14964746
Filing Dt:
12/10/2015
Title:
METHOD FOR CONTROLLED RECESSING OF MATERIALS IN CAVITIES IN IC DEVICES
75
Patent #:
9570397
Issue Dt:
02/14/2017
Application #:
14964786
Filing Dt:
12/10/2015
Title:
LOCAL INTERCONNECT STRUCTURE INCLUDING NON-ERODED CONTACT VIA TRENCHES
76
Patent #:
NONE
Issue Dt:
Application #:
14964813
Filing Dt:
12/10/2015
Publication #:
US20170169155
Pub Dt:
06/15/2017
Title:
METHOD TO ADJUST ALLEY GAP BETWEEN LARGE BLOCKS FOR FLOORPLAN OPTIMIZATION
77
Patent #:
9520396
Issue Dt:
12/13/2016
Application #:
14965193
Filing Dt:
12/10/2015
Publication #:
US20160111422
Pub Dt:
04/21/2016
Title:
METHOD FOR MAKING HIGH VOLTAGE INTEGRATED CIRCUIT DEVICES IN A FIN-TYPE PROCESS AND RESULTING DEVICES
78
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Filing Dt:
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Title:
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Issue Dt:
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Filing Dt:
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Pub Dt:
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Title:
WAVEGUIDE STRUCTURES USED IN PHONOTICS CHIP PACKAGING
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Issue Dt:
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Filing Dt:
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Title:
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Patent #:
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Filing Dt:
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Pub Dt:
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Title:
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Title:
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Filing Dt:
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Title:
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Title:
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Title:
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Issue Dt:
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Title:
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Filing Dt:
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Pub Dt:
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Title:
PATTERNED MAGNETIC SHIELDS FOR INDUCTORS AND TRANSFORMERS
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Title:
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Title:
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Title:
SEMICONDUCTOR STRUCTURE HAVING SILICON GERMANIUM FINS AND METHOD OF FABRICATING SAME
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Title:
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Filing Dt:
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Title:
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Title:
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Title:
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Title:
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Title:
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Publication #:
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Pub Dt:
04/28/2016
Title:
REPLACEMENT GATE STRUCTURES FOR TRANSISTOR DEVICES
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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