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Patent #:
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Issue Dt:
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10/23/2018
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Application #:
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15213665
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Filing Dt:
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07/19/2016
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Publication #:
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Pub Dt:
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01/25/2018
| | | | |
Title:
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METHODS OF DETECTING FAULTS IN REAL-TIME FOR SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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12/10/2019
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15214585
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Filing Dt:
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07/20/2016
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Publication #:
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Pub Dt:
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01/25/2018
| | | | |
Title:
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LITHOGRAPHIC PATTERNING TO FORM FINE PITCH FEATURES
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Patent #:
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Issue Dt:
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06/13/2017
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15214854
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07/20/2016
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Title:
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FIN-TYPE FIELD-EFFECT TRANSISTORS WITH STRAINED CHANNELS
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05/16/2017
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15215043
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Filing Dt:
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07/20/2016
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Title:
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METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING TRIGGER-VOLTAGE TUNABLE CASCODE TRANSISTORS
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10/24/2017
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15215674
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Filing Dt:
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07/21/2016
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Publication #:
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Pub Dt:
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11/24/2016
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Title:
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PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS
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Patent #:
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08/21/2018
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15217643
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Filing Dt:
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07/22/2016
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Publication #:
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Pub Dt:
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01/25/2018
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Title:
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SEMICONDUCTOR WAFERS WITH REDUCED BOW AND WARPAGE
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01/22/2019
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15218241
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07/25/2016
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Pub Dt:
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01/25/2018
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Title:
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SYSTEMS AND METHODS FOR SENSING PROCESS PARAMETERS DURING SEMICONDUCTOR DEVICE FABRICATION
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Patent #:
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07/11/2017
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15218318
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Filing Dt:
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07/25/2016
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Title:
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FIN-BASED RF DIODES
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Patent #:
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08/28/2018
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15219370
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07/26/2016
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02/01/2018
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Title:
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PREVENTING BRIDGE FORMATION BETWEEN REPLACEMENT GATE AND SOURCE/DRAIN REGION THROUGH STI STRUCTURE
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08/01/2017
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15219378
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Filing Dt:
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07/26/2016
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Title:
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MIDDLE OF THE LINE (MOL) METAL CONTACTS
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Patent #:
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07/03/2018
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15219403
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07/26/2016
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Pub Dt:
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02/01/2018
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Title:
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METHODS OF FORMING IC PRODUCTS COMPRISING A NANO-SHEET DEVICE AND A TRANSISTOR DEVICE HAVING FIRST AND SECOND REPLACEMENT GATE STRUCTURES
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12/19/2017
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15219917
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07/26/2016
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Title:
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METHODS OF FORMING FIN CUT REGIONS BY OXIDIZING FIN PORTIONS
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08/22/2017
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15219967
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Filing Dt:
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07/26/2016
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Title:
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HIGHER 'K' GATE DIELECTRIC CAP FOR REPLACEMENT METAL GATE (RMG) FINFET DEVICES
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Issue Dt:
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06/12/2018
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15220764
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07/27/2016
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02/01/2018
| | | | |
Title:
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INTERCONNECT STRUCTURE HAVING POWER RAIL STRUCTURE AND RELATED METHOD
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Patent #:
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09/18/2018
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15221647
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07/28/2016
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02/01/2018
| | | | |
Title:
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IC STRUCTURE WITH INTERFACE LINER AND METHODS OF FORMING SAME
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Patent #:
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02/20/2018
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15222096
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07/28/2016
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Publication #:
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Pub Dt:
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02/01/2018
| | | | |
Title:
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STRUCTURE AND METHOD TO MEASURE FOCUS-DEPENDENT PATTERN SHIFT IN INTEGRATED CIRCUIT IMAGING
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Patent #:
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03/17/2020
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15222261
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07/28/2016
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Pub Dt:
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04/13/2017
| | | | |
Title:
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FORMING REPLACEMENT LOW-K SPACER IN TIGHT PITCH FIN FIELD EFFECT TRANSISTORS
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Patent #:
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03/17/2020
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15223882
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Filing Dt:
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07/29/2016
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Pub Dt:
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11/17/2016
| | | | |
Title:
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SYSTEM AND METHOD FOR MONITORING WAFER HANDLING AND A WAFER HANDLING MACHINE
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05/09/2017
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15224091
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Filing Dt:
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07/29/2016
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Title:
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METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES BY PERFORMING PLASMA NITRIDATION PROCESS ON FIN ENDS
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Patent #:
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NONE
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15224139
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Filing Dt:
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07/29/2016
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Publication #:
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Pub Dt:
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02/01/2018
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR REDUCING DOPANT CONCENTRATIONS IN CHANNEL REGIONS OF FINFET DEVICES
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06/26/2018
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15225152
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08/01/2016
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Pub Dt:
|
02/01/2018
| | | | |
Title:
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METHODS OF FORMING AN AIR-GAP SPACER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15225994
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Filing Dt:
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08/02/2016
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Publication #:
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Pub Dt:
|
02/08/2018
| | | | |
Title:
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METHOD FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE USING A NITRIDE LINER AND A DIFFUSIONLESS ANNEAL
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Patent #:
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Issue Dt:
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05/16/2017
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Application #:
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15226165
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Filing Dt:
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08/02/2016
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Title:
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METHODS OF FORMING DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES
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Patent #:
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Issue Dt:
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02/20/2018
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Application #:
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15226575
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Filing Dt:
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08/02/2016
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Publication #:
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Pub Dt:
|
02/08/2018
| | | | |
Title:
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CO-INTEGRATION OF SELF-ALIGNED AND NON-SELF ALIGNED HETEROJUNCTION BIPOLAR TRANSISTORS
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Patent #:
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Issue Dt:
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07/02/2019
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Application #:
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15226867
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Filing Dt:
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08/02/2016
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Publication #:
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Pub Dt:
|
02/08/2018
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVING UNIDIRECTIONAL LAYOUT USING SELF-ALIGNED DOUBLE PATTERNING
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Patent #:
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Issue Dt:
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01/30/2018
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Application #:
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15227081
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Filing Dt:
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08/03/2016
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Publication #:
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Pub Dt:
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03/02/2017
| | | | |
Title:
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PHOTODETECTOR METHODS AND PHOTODETECTOR STRUCTURES
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Patent #:
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Issue Dt:
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01/01/2019
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Application #:
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15227142
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Filing Dt:
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08/03/2016
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Publication #:
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Pub Dt:
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02/16/2017
| | | | |
Title:
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FORMING A CONTACT FOR A TALL FIN TRANSISTOR
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Patent #:
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Issue Dt:
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05/08/2018
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Application #:
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15227330
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Filing Dt:
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08/03/2016
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Publication #:
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Pub Dt:
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02/08/2018
| | | | |
Title:
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MULTIPLE-STEP EPITAXIAL GROWTH S/D REGIONS FOR NMOS FINFET
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Patent #:
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Issue Dt:
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03/13/2018
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Application #:
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15228317
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Filing Dt:
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08/04/2016
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Publication #:
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Pub Dt:
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02/08/2018
| | | | |
Title:
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METHODS OF FORMING A THROUGH-SUBSTRATE-VIA (TSV) AND A METALLIZATION LAYER AFTER FORMATION OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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07/24/2018
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15228772
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Filing Dt:
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08/04/2016
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Publication #:
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Pub Dt:
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02/09/2017
| | | | |
Title:
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MEASUREMENT SYSTEM AND METHOD FOR MEASURING IN THIN FILMS
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Issue Dt:
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11/21/2017
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15229292
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Filing Dt:
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08/05/2016
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Title:
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METHODS OF FORMING A HIGH-K CONTACT LINER TO IMPROVE EFFECTIVE VIA SEPARATION DISTANCE AND THE RESULTING DEVICES
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05/08/2018
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15229431
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08/05/2016
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Publication #:
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Pub Dt:
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02/08/2018
| | | | |
Title:
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FINFET DEVICE AND METHOD OF MANUFACTURING
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Issue Dt:
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05/08/2018
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Application #:
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15231105
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Filing Dt:
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08/08/2016
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Publication #:
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Pub Dt:
|
02/08/2018
| | | | |
Title:
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SEMICONDUCTOR-ON-INSULATOR WAFER, SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR, AND METHODS FOR THE FORMATION AND OPERATION THEREOF
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Patent #:
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Issue Dt:
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01/09/2018
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Application #:
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15231840
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Filing Dt:
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08/09/2016
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Title:
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NON-PLANAR MONOLITHIC HYBRID OPTOELECTRONIC STRUCTURES AND METHODS
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Patent #:
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Issue Dt:
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08/28/2018
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Application #:
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15232090
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Filing Dt:
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08/09/2016
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Publication #:
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Pub Dt:
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02/15/2018
| | | | |
Title:
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AIR GAP SPACER IMPLANT FOR NZG RELIABILITY FIX
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Issue Dt:
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07/18/2017
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Application #:
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15232164
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Filing Dt:
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08/09/2016
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Title:
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STRUCTURE AND METHOD FOR CMP-FREE III-V ISOLATION
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Issue Dt:
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11/21/2017
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15232174
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Filing Dt:
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08/09/2016
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Title:
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STACKED VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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02/07/2017
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Application #:
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15232246
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Filing Dt:
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08/09/2016
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Publication #:
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Pub Dt:
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12/15/2016
| | | | |
Title:
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SPACER CHAMFERING GATE STACK SCHEME
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Patent #:
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Issue Dt:
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10/03/2017
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Application #:
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15232300
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Filing Dt:
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08/09/2016
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Publication #:
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Pub Dt:
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12/15/2016
| | | | |
Title:
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SPACER CHAMFERING GATE STACK SCHEME
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Patent #:
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Issue Dt:
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09/19/2017
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15232873
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Filing Dt:
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08/10/2016
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Title:
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SEMICONDUCTOR STRUCTURE WITH A DOPANT IMPLANT REGION HAVING A LINEARLY GRADED CONDUCTIVITY LEVEL AND METHOD OF FORMING THE STRUCTURE
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Patent #:
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Issue Dt:
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01/16/2018
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15232906
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Filing Dt:
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08/10/2016
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Title:
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FLASH MEMORY DEVICE
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Patent #:
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NONE
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Application #:
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15233229
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Filing Dt:
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08/10/2016
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Publication #:
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Pub Dt:
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02/15/2018
| | | | |
Title:
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DEEP TRENCH CAPACITORS WITH A DIFFUSION PAD
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NONE
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15233232
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Filing Dt:
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08/10/2016
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Publication #:
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Pub Dt:
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02/15/2018
| | | | |
Title:
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AUTOMATED FULL-CHIP DESIGN SPACE SAMPLING USING UNSUPERVISED MACHINE LEARNING
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Issue Dt:
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09/26/2017
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15233315
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08/10/2016
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Publication #:
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Pub Dt:
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05/04/2017
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Title:
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ETCH STOP FOR AIRGAP PROTECTION
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Patent #:
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NONE
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Application #:
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15233445
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Filing Dt:
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08/10/2016
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Publication #:
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Pub Dt:
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02/15/2018
| | | | |
Title:
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METHOD TO TUNE CONTACT CD AND REDUCE MASK COUNT BY TILTED ION BEAM
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Patent #:
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Issue Dt:
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02/23/2021
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15233454
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Filing Dt:
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08/10/2016
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Pub Dt:
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02/15/2018
| | | | |
Title:
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RECHARGEABLE WAFER CARRIER SYSTEMS
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Issue Dt:
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05/15/2018
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Application #:
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15234066
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Filing Dt:
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08/11/2016
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Pub Dt:
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02/15/2018
| | | | |
Title:
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SEMICONDUCTOR DEVICE COMPRISING A FLOATING GATE FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/27/2018
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15234078
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Filing Dt:
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08/11/2016
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Pub Dt:
|
02/15/2018
| | | | |
Title:
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DUAL EXPOSURE PATTERNING OF A PHOTOMASK TO PRINT A CONTACT, A VIA OR A CURVILINEAR SHAPE ON AN INTEGRATED CIRCUIT
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Patent #:
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NONE
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15234361
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Filing Dt:
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08/11/2016
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Publication #:
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Pub Dt:
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11/23/2017
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD
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Issue Dt:
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05/15/2018
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15234762
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Filing Dt:
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08/11/2016
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Publication #:
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Pub Dt:
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02/15/2018
| | | | |
Title:
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PREVENTING SHORTING BETWEEN SOURCE AND/OR DRAIN CONTACTS AND GATE
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Patent #:
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Issue Dt:
|
12/05/2017
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Application #:
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15235256
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Filing Dt:
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08/12/2016
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Title:
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COMPENSATION OF TEMPERATURE EFFECTS IN SEMICONDUCTOR DEVICE STRUCTURES
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Patent #:
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Issue Dt:
|
07/11/2017
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Application #:
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15235892
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Filing Dt:
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08/12/2016
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Title:
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ADVANCED SELF-ALIGNED PATTERNING PROCESS WITH SIT SPACER AS A FINAL DIELECTRIC ETCH HARDMASK
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Patent #:
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Issue Dt:
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11/21/2017
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Application #:
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15236608
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Filing Dt:
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08/15/2016
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Title:
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INTEGRATED CIRCUIT STRUCTURE WITH INSULATED MEMORY DEVICE AND RELATED METHODS
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Patent #:
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Issue Dt:
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04/17/2018
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Application #:
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15237066
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Filing Dt:
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08/15/2016
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Publication #:
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Pub Dt:
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02/15/2018
| | | | |
Title:
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IC STRUCTURE INTEGRITY SENSOR HAVING INTERDIGITATED CONDUCTIVE ELEMENTS
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Patent #:
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Issue Dt:
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09/25/2018
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Application #:
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15237794
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Filing Dt:
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08/16/2016
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Publication #:
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Pub Dt:
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02/22/2018
| | | | |
Title:
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NVM DEVICE IN SOI TECHNOLOGY AND METHOD OF FABRICATING AN ACCORDING DEVICE
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Patent #:
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Issue Dt:
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08/21/2018
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Application #:
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15238023
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Filing Dt:
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08/16/2016
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Publication #:
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Pub Dt:
|
12/08/2016
| | | | |
Title:
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FERROELECTRIC FINFET
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Patent #:
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Issue Dt:
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02/27/2018
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Application #:
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15238107
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Filing Dt:
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08/16/2016
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Publication #:
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Pub Dt:
|
02/22/2018
| | | | |
Title:
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ASSIST CUTS DISPOSED IN DUMMY LINES TO IMPROVE METAL SIGNAL CUTS IN ACTIVE LINES OF A SEMICONDUCTOR STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15238760
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Filing Dt:
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08/17/2016
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Publication #:
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|
Pub Dt:
|
02/22/2018
| | | | |
Title:
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TEXTURING OF SILICON SURFACE WITH DIRECT-SELF ASSEMBLY PATTERNING
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|
Patent #:
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NONE
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Issue Dt:
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Application #:
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15238884
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Filing Dt:
|
08/17/2016
|
Publication #:
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Pub Dt:
|
12/08/2016
| | | | |
Title:
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LOCAL THINNING OF SEMICONDUCTOR FINS
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Patent #:
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Issue Dt:
|
04/24/2018
|
Application #:
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15239072
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Filing Dt:
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08/17/2016
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Publication #:
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Pub Dt:
|
02/22/2018
| | | | |
Title:
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ADJUSTING OF PATTERNS IN DESIGN LAYOUT FOR OPTICAL PROXIMITY CORRECTION
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Patent #:
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Issue Dt:
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12/18/2018
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Application #:
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15239178
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Filing Dt:
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08/17/2016
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Publication #:
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|
Pub Dt:
|
12/08/2016
| | | | |
Title:
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VIA FORMATION USING SIDEWALL IMAGE TRANFER PROCESS TO DEFINE LATERAL DIMENSION
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Patent #:
|
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Issue Dt:
|
09/26/2017
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Application #:
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15242643
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Filing Dt:
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08/22/2016
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Title:
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INTEGRATED CIRCUITS WITH PELTIER COOLING PROVIDED BY BACK-END WIRING
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15242689
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Filing Dt:
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08/22/2016
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Publication #:
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Pub Dt:
|
02/22/2018
| | | | |
Title:
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METHOD OF FORMING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
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Patent #:
|
|
Issue Dt:
|
08/22/2017
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Application #:
|
15242951
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Filing Dt:
|
08/22/2016
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Title:
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CONTACTS FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR
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Patent #:
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|
Issue Dt:
|
01/01/2019
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Application #:
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15244067
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Filing Dt:
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08/23/2016
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Publication #:
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Pub Dt:
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02/23/2017
| | | | |
Title:
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FORMING A GATE CONTACT IN THE ACTIVE AREA
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Patent #:
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|
Issue Dt:
|
09/26/2017
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Application #:
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15245634
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Filing Dt:
|
08/24/2016
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Title:
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DEVICES AND METHODS OF FORMING VFET WITH SELF-ALIGNED REPLACEMENT METAL GATES ALIGNED TO TOP SPACER POST TOP SOURCE DRAIN EPI
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|
|
Patent #:
|
|
Issue Dt:
|
08/07/2018
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Application #:
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15247513
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Filing Dt:
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08/25/2016
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Publication #:
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Pub Dt:
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12/22/2016
| | | | |
Title:
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THROUGH SILICON VIA DEVICE HAVING LOW STRESS, THIN FILM GAPS AND METHODS FOR FORMING THE SAME
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|
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Patent #:
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|
Issue Dt:
|
12/12/2017
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Application #:
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15248367
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Filing Dt:
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08/26/2016
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Title:
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INTEGRATED CIRCUIT STRUCTURE WITHOUT GATE CONTACT AND METHOD OF FORMING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
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Application #:
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15248889
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Filing Dt:
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08/26/2016
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Publication #:
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Pub Dt:
|
03/01/2018
| | | | |
Title:
|
DEVICES WITH CONTACT-TO-GATE SHORTING THROUGH CONDUCTIVE PATHS BETWEEN FINS AND FABRICATION METHODS
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|
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Patent #:
|
|
Issue Dt:
|
02/05/2019
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Application #:
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15249700
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Filing Dt:
|
08/29/2016
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Publication #:
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|
Pub Dt:
|
03/01/2018
| | | | |
Title:
|
POST ZERO VIA LAYER KEEP OUT ZONE OVER THROUGH SILICON VIA REDUCING BEOL PUMPING EFFECTS
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|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
15251435
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Filing Dt:
|
08/30/2016
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Title:
|
ALMOST DEFECT-FREE ACTIVE CHANNEL REGION
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|
|
Patent #:
|
|
Issue Dt:
|
06/13/2017
|
Application #:
|
15251632
|
Filing Dt:
|
08/30/2016
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Title:
|
ESD DEVICE FOR A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
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15251804
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Filing Dt:
|
08/30/2016
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Publication #:
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|
Pub Dt:
|
06/15/2017
| | | | |
Title:
|
LOCAL INTERCONNECT STRUCTURE INCLUDING NON-ERODED CONTACT VIA TRENCHES
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|
|
Patent #:
|
|
Issue Dt:
|
01/31/2017
|
Application #:
|
15252315
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Filing Dt:
|
08/31/2016
|
Publication #:
|
|
Pub Dt:
|
12/22/2016
| | | | |
Title:
|
DUAL CHANNEL FINFET WITH RELAXED PFET REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2017
|
Application #:
|
15252586
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Filing Dt:
|
08/31/2016
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Publication #:
|
|
Pub Dt:
|
02/09/2017
| | | | |
Title:
|
METHOD FOR FORMING FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2019
|
Application #:
|
15252995
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Filing Dt:
|
08/31/2016
|
Publication #:
|
|
Pub Dt:
|
03/01/2018
| | | | |
Title:
|
SEMICONDUCTOR DEVICE STRUCTURE WITH SELF-ALIGNED CAPACITOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2018
|
Application #:
|
15253097
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Filing Dt:
|
08/31/2016
|
Publication #:
|
|
Pub Dt:
|
03/01/2018
| | | | |
Title:
|
MULTIPLE PATTERNING PROCESS FOR FORMING PILLAR MASK ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2017
|
Application #:
|
15254096
|
Filing Dt:
|
09/01/2016
|
Publication #:
|
|
Pub Dt:
|
05/18/2017
| | | | |
Title:
|
MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2018
|
Application #:
|
15255237
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Filing Dt:
|
09/02/2016
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
Title:
|
FORMING EDGE ETCH PROTECTION USING DUAL LAYER OF POSITIVE-NEGATIVE TONE RESISTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2017
|
Application #:
|
15255628
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Filing Dt:
|
09/02/2016
|
Publication #:
|
|
Pub Dt:
|
12/22/2016
| | | | |
Title:
|
RECESSING RMG METAL GATE STACK FOR FORMING SELF-ALIGNED CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15256027
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Filing Dt:
|
09/02/2016
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
Title:
|
METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFORMANCE AND HCI OPTIMIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
15257245
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Filing Dt:
|
09/06/2016
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
Title:
|
METHOD INCLUDING A FORMATION OF A DIFFUSION BARRIER AND SEMICONDUCTOR STRUCTURE INCLUDING A DIFFUSION BARRIER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2018
|
Application #:
|
15258333
|
Filing Dt:
|
09/07/2016
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
Title:
|
SOURCE/DRAIN PARASITIC CAPACITANCE REDUCTION IN FINFET-BASED SEMICONDUCTOR STRUCTURE HAVING TUCKED FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2018
|
Application #:
|
15258597
|
Filing Dt:
|
09/07/2016
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
Title:
|
METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2018
|
Application #:
|
15259268
|
Filing Dt:
|
09/08/2016
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
Title:
|
PUNCHTHROUGH STOP LAYERS FOR FIN-TYPE FIELD-EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2018
|
Application #:
|
15259472
|
Filing Dt:
|
09/08/2016
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
Title:
|
SELECTIVE SAC CAPPING ON FIN FIELD EFFECT TRANSISTOR STRUCTURES AND RELATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2017
|
Application #:
|
15263551
|
Filing Dt:
|
09/13/2016
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S)
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2017
|
Application #:
|
15263817
|
Filing Dt:
|
09/13/2016
|
Title:
|
MULTI-CHIP MODULES WITH VERTICALLY ALIGNED GRATING COUPLERS FOR TRANSMISSION OF LIGHT SIGNALS BETWEEN OPTICAL WAVEGUIDES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
15264885
|
Filing Dt:
|
09/14/2016
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
LATERAL BICMOS REPLACEMENT METAL GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2018
|
Application #:
|
15264957
|
Filing Dt:
|
09/14/2016
|
Publication #:
|
|
Pub Dt:
|
03/15/2018
| | | | |
Title:
|
BACKSIDE SPACER STRUCTURES FOR IMPROVED THERMAL PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2017
|
Application #:
|
15266092
|
Filing Dt:
|
09/15/2016
|
Title:
|
CONTACT FORMATION FOR STACKED FINFETs
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2017
|
Application #:
|
15266201
|
Filing Dt:
|
09/15/2016
|
Title:
|
WORD LINE VOLTAGE GENERATOR FOR PROGRAMMABLE MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2017
|
Application #:
|
15266439
|
Filing Dt:
|
09/15/2016
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
EMBEDDED METAL-INSULATOR-METAL CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2018
|
Application #:
|
15267887
|
Filing Dt:
|
09/16/2016
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15268751
|
Filing Dt:
|
09/19/2016
|
Publication #:
|
|
Pub Dt:
|
03/22/2018
| | | | |
Title:
|
METHODS OF FORMING BOTTOM AND TOP SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2019
|
Application #:
|
15268796
|
Filing Dt:
|
09/19/2016
|
Publication #:
|
|
Pub Dt:
|
03/22/2018
| | | | |
Title:
|
METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15269023
|
Filing Dt:
|
09/19/2016
|
Publication #:
|
|
Pub Dt:
|
03/22/2018
| | | | |
Title:
|
FDSOI CHANNEL CONTROL BY IMPLANTED HIGH-K BURIED OXIDE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15269138
|
Filing Dt:
|
09/19/2016
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
SELF-ALIGNED VIA PROCESS FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15270598
|
Filing Dt:
|
09/20/2016
|
Publication #:
|
|
Pub Dt:
|
03/22/2018
| | | | |
Title:
|
PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) USING BACK-BIAS COMPENSATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15271058
|
Filing Dt:
|
09/20/2016
|
Publication #:
|
|
Pub Dt:
|
03/22/2018
| | | | |
Title:
|
METHOD, APPARATUS, AND SYSTEM FOR A SEMICONDUCTOR DEVICE HAVING NOVEL ELECTROSTATIC DISCHARGE (ESD) PROTECTION SCHEME AND CIRCUIT
|
|