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Reel/Frame:	056987/0001			Pages:	1045
		Recorded:	05/12/2021
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 18026
Page 163 of 181
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Patent #:	9818640	Issue Dt:	11/14/2017	Application #:	15271475	Filing Dt:	09/21/2016
Title:	APPARATUS AND METHOD OF FORMING SELF-ALIGNED CUTS IN A NON-MANDREL LINE OF AN ARRAY OF METAL LINES

Patent #:	9818641	Issue Dt:	11/14/2017	Application #:	15271497	Filing Dt:	09/21/2016
Title:	APPARATUS AND METHOD OF FORMING SELF-ALIGNED CUTS IN MANDREL AND A NON-MANDREL LINES OF AN ARRAY OF METAL LINES

Patent #:	9978608	Issue Dt:	05/22/2018	Application #:	15271511	Filing Dt:	09/21/2016
Publication #:	US20180082852	Pub Dt:	03/22/2018
Title:	FIN PATTERNING FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR

Patent #:	9786545	Issue Dt:	10/10/2017	Application #:	15271519	Filing Dt:	09/21/2016
Title:	METHOD OF FORMING ANA REGIONS IN AN INTEGRATED CIRCUIT

Patent #:	9923046	Issue Dt:	03/20/2018	Application #:	15271730	Filing Dt:	09/21/2016
Publication #:	US20180083089	Pub Dt:	03/22/2018
Title:	SEMICONDUCTOR DEVICE RESISTOR STRUCTURE

Patent #:	9853115	Issue Dt:	12/26/2017	Application #:	15272919	Filing Dt:	09/22/2016
Publication #:	US20170125535	Pub Dt:	05/04/2017
Title:	HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

Patent #:	9748351	Issue Dt:	08/29/2017	Application #:	15273777	Filing Dt:	09/23/2016
Publication #:	US20170012105	Pub Dt:	01/12/2017
Title:	PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE

Patent #:	10749031	Issue Dt:	08/18/2020	Application #:	15273778	Filing Dt:	09/23/2016
Publication #:	US20170012130	Pub Dt:	01/12/2017
Title:	LARGE AREA CONTACTS FOR SMALL TRANSISTORS

Patent #:	9960086	Issue Dt:	05/01/2018	Application #:	15274974	Filing Dt:	09/23/2016
Publication #:	US20180090391	Pub Dt:	03/29/2018
Title:	METHODS, APPARATUS AND SYSTEM FOR SELF-ALIGNED RETROGRADE WELL DOPING FOR FINFET DEVICES

Patent #:	10069015	Issue Dt:	09/04/2018	Application #:	15276372	Filing Dt:	09/26/2016
Publication #:	US20180090624	Pub Dt:	03/29/2018
Title:	Width Adjustment of Stacked Nanowires

Patent #:	NONE	Issue Dt:		Application #:	15276840	Filing Dt:	09/27/2016
Publication #:	US20180089354	Pub Dt:	03/29/2018
Title:	METHOD TO REDUCE HOT SPOTS AND RECOVER VT/AREA ON INTEGRATED CIRCUIT CHIPS USING SLEW WINDOW SHIFT

Patent #:	10283584	Issue Dt:	05/07/2019	Application #:	15277583	Filing Dt:	09/27/2016
Publication #:	US20180090558	Pub Dt:	03/29/2018
Title:	CAPACITIVE STRUCTURE IN A SEMICONDUCTOR DEVICE HAVING REDUCED CAPACITANCE VARIABILITY

Patent #:	9786607	Issue Dt:	10/10/2017	Application #:	15277732	Filing Dt:	09/27/2016
Publication #:	US20170018459	Pub Dt:	01/19/2017
Title:	INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER

Patent #:	10055535	Issue Dt:	08/21/2018	Application #:	15277796	Filing Dt:	09/27/2016
Publication #:	US20180089357	Pub Dt:	03/29/2018
Title:	METHOD, SYSTEM AND PROGRAM PRODUCT FOR IDENTIFYING ANOMALIES IN INTEGRATED CIRCUIT DESIGN LAYOUTS

Patent #:	9799746	Issue Dt:	10/24/2017	Application #:	15278925	Filing Dt:	09/28/2016
Publication #:	US20170077258	Pub Dt:	03/16/2017
Title:	PREVENTING LEAKAGE INSIDE AIR-GAP SPACER DURING CONTACT FORMATION

Patent #:	10141229	Issue Dt:	11/27/2018	Application #:	15279559	Filing Dt:	09/29/2016
Publication #:	US20180090386	Pub Dt:	03/29/2018
Title:	PROCESS FOR FORMING SEMICONDUCTOR LAYERS OF DIFFERENT THICKNESS IN FDSOI TECHNOLOGIES

Patent #:	9831131	Issue Dt:	11/28/2017	Application #:	15279732	Filing Dt:	09/29/2016
Title:	METHOD FOR FORMING NANOWIRES INCLUDING MULTIPLE INTEGRATED DEVICES WITH ALTERNATE CHANNEL MATERIALS

Patent #:	10199480	Issue Dt:	02/05/2019	Application #:	15280451	Filing Dt:	09/29/2016
Publication #:	US20180090598	Pub Dt:	03/29/2018
Title:	CONTROLLING SELF-ALIGNED GATE LENGTH IN VERTICAL TRANSISTOR REPLACEMENT GATE FLOW

Patent #:	9685537	Issue Dt:	06/20/2017	Application #:	15280521	Filing Dt:	09/29/2016
Title:	GATE LENGTH CONTROL FOR VERTICAL TRANSISTORS AND INTEGRATION WITH REPLACEMENT GATE FLOW

Patent #:	10042973	Issue Dt:	08/07/2018	Application #:	15281183	Filing Dt:	09/30/2016
Publication #:	US20180096093	Pub Dt:	04/05/2018
Title:	EXPANSION OF ALLOWED DESIGN RULE SPACE BY WAIVING BENIGN GEOMETRIES

Patent #:	9882025	Issue Dt:	01/30/2018	Application #:	15281227	Filing Dt:	09/30/2016
Title:	METHODS OF SIMULTANEOUSLY FORMING BOTTOM AND TOP SPACERS ON A VERTICAL TRANSISTOR DEVICE

Patent #:	9991155	Issue Dt:	06/05/2018	Application #:	15281418	Filing Dt:	09/30/2016
Publication #:	US20180096884	Pub Dt:	04/05/2018
Title:	LOCAL TRAP-RICH ISOLATION

Patent #:	9953876	Issue Dt:	04/24/2018	Application #:	15282211	Filing Dt:	09/30/2016
Publication #:	US20180096894	Pub Dt:	04/05/2018
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	9864132	Issue Dt:	01/09/2018	Application #:	15282320	Filing Dt:	09/30/2016
Title:	SILICON WAVEGUIDE DEVICES IN INTEGRATED PHOTONICS

Patent #:	9837553	Issue Dt:	12/05/2017	Application #:	15282415	Filing Dt:	09/30/2016
Title:	VERTICAL FIELD EFFECT TRANSISTOR

Patent #:	9601335	Issue Dt:	03/21/2017	Application #:	15282836	Filing Dt:	09/30/2016
Publication #:	US20170033196	Pub Dt:	02/02/2017
Title:	TRENCH FORMATION FOR DIELECTRIC FILLED CUT REGION

Patent #:	9698230	Issue Dt:	07/04/2017	Application #:	15283951	Filing Dt:	10/03/2016
Publication #:	US20170141198	Pub Dt:	05/18/2017
Title:	MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT

Patent #:	9953879	Issue Dt:	04/24/2018	Application #:	15284110	Filing Dt:	10/03/2016
Publication #:	US20180096895	Pub Dt:	04/05/2018
Title:	PREVENTING OXIDATION DEFECTS IN STRAIN-RELAXED FINS BY REDUCING LOCAL GAP FILL VOIDS

Patent #:	10153162	Issue Dt:	12/11/2018	Application #:	15284773	Filing Dt:	10/04/2016
Publication #:	US20180096839	Pub Dt:	04/05/2018
Title:	SHRINK PROCESS AWARE ASSIST FEATURES

Patent #:	10079173	Issue Dt:	09/18/2018	Application #:	15285092	Filing Dt:	10/04/2016
Publication #:	US20180096932	Pub Dt:	04/05/2018
Title:	METHODS OF FORMING METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING PRODUCTS

Patent #:	10049944	Issue Dt:	08/14/2018	Application #:	15285978	Filing Dt:	10/05/2016
Publication #:	US20180096899	Pub Dt:	04/05/2018
Title:	METHOD OF MANUFACTURING SELECTIVE NANOSTRUCTURES INTO FINFET PROCESS FLOW

Patent #:	9812365	Issue Dt:	11/07/2017	Application #:	15286117	Filing Dt:	10/05/2016
Title:	METHODS OF CUTTING GATE STRUCTURES ON TRANSISTOR DEVICES

Patent #:	10096595	Issue Dt:	10/09/2018	Application #:	15286196	Filing Dt:	10/05/2016
Publication #:	US20170125403	Pub Dt:	05/04/2017
Title:	ANTENNA DIODE CIRCUIT FOR MANUFACTURING OF SEMICONDUCTOR DEVICES

Patent #:	9793395	Issue Dt:	10/17/2017	Application #:	15287134	Filing Dt:	10/06/2016
Title:	VERTICAL VACUUM CHANNEL TRANSISTOR

Patent #:	10062612	Issue Dt:	08/28/2018	Application #:	15288503	Filing Dt:	10/07/2016
Publication #:	US20180102291	Pub Dt:	04/12/2018
Title:	METHOD AND SYSTEM FOR CONSTRUCTING FINFET DEVICES HAVING A SUPER STEEP RETROGRADE WELL

Patent #:	9812368	Issue Dt:	11/07/2017	Application #:	15289158	Filing Dt:	10/08/2016
Publication #:	US20170162451	Pub Dt:	06/08/2017
Title:	METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES

Patent #:	9825044	Issue Dt:	11/21/2017	Application #:	15289161	Filing Dt:	10/08/2016
Publication #:	US20170162584	Pub Dt:	06/08/2017
Title:	METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES

Patent #:	10147714	Issue Dt:	12/04/2018	Application #:	15289401	Filing Dt:	10/10/2016
Publication #:	US20180102354	Pub Dt:	04/12/2018
Title:	METHOD, APPARATUS, AND SYSTEM FOR TWO-DIMENSIONAL POWER RAIL TO ENABLE SCALING OF A STANDARD CELL

Patent #:	9711447	Issue Dt:	07/18/2017	Application #:	15290277	Filing Dt:	10/11/2016
Title:	SELF-ALIGNED LITHOGRAPHIC PATTERNING WITH VARIABLE SPACINGS

Patent #:	NONE	Issue Dt:		Application #:	15290907	Filing Dt:	10/11/2016
Publication #:	US20180102315	Pub Dt:	04/12/2018
Title:	SURFACE AREA-DEPENDENT SEMICONDUCTOR DEVICE WITH INCREASED SURFACE AREA

Patent #:	NONE	Issue Dt:		Application #:	15291275	Filing Dt:	10/12/2016
Publication #:	US20180102318	Pub Dt:	04/12/2018
Title:	COMPOUND RESISTOR STRUCTURE FOR SEMICONDUCTOR DEVICE

Patent #:	9911619	Issue Dt:	03/06/2018	Application #:	15291446	Filing Dt:	10/12/2016
Title:	FIN CUT WITH ALTERNATING TWO COLOR FIN HARDMASK

Patent #:	10211090	Issue Dt:	02/19/2019	Application #:	15291561	Filing Dt:	10/12/2016
Publication #:	US20180102422	Pub Dt:	04/12/2018
Title:	TRANSISTOR WITH AN AIRGAP FOR REDUCED BASE-EMITTER CAPACITANCE AND METHOD OF FORMING THE TRANSISTOR

Patent #:	9911657	Issue Dt:	03/06/2018	Application #:	15291750	Filing Dt:	10/12/2016
Publication #:	US20170154821	Pub Dt:	06/01/2017
Title:	SEMICONDUCTOR DEVICE INCLUDING FINFET AND FIN VARACTOR

Patent #:	9960207	Issue Dt:	05/01/2018	Application #:	15292445	Filing Dt:	10/13/2016
Publication #:	US20180108706	Pub Dt:	04/19/2018
Title:	SPIN-SELECTIVE ELECTRON RELAY

Patent #:	10083958	Issue Dt:	09/25/2018	Application #:	15292488	Filing Dt:	10/13/2016
Publication #:	US20180108651	Pub Dt:	04/19/2018
Title:	DEEP TRENCH METAL-INSULATOR-METAL CAPACITORS

Patent #:	NONE	Issue Dt:		Application #:	15292552	Filing Dt:	10/13/2016
Publication #:	US20180108642	Pub Dt:	04/19/2018
Title:	INTERPOSER HEATER FOR HIGH BANDWIDTH MEMORY APPLICATIONS

Patent #:	NONE	Issue Dt:		Application #:	15292808	Filing Dt:	10/13/2016
Publication #:	US20180108732	Pub Dt:	04/19/2018
Title:	NOTCHED FIN STRUCTURES AND METHODS OF MANUFACTURE

Patent #:	NONE	Issue Dt:		Application #:	15293461	Filing Dt:	10/14/2016
Publication #:	US20180108654	Pub Dt:	04/19/2018
Title:	FINFET DEVICE WITH LOW RESISTANCE FINS

Patent #:	9947590	Issue Dt:	04/17/2018	Application #:	15294228	Filing Dt:	10/14/2016
Publication #:	US20180108571	Pub Dt:	04/19/2018
Title:	METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING METAL LINE JUMPING OVER MOL FEATURES IN A STANDARD CELL

Patent #:	9893718	Issue Dt:	02/13/2018	Application #:	15295299	Filing Dt:	10/17/2016
Title:	TRANSMISSION DRIVER IMPEDANCE CALIBRATION CIRCUIT

Patent #:	9947789	Issue Dt:	04/17/2018	Application #:	15295338	Filing Dt:	10/17/2016
Publication #:	US20180108776	Pub Dt:	04/19/2018
Title:	VERTICAL TRANSISTORS STRESSED FROM VARIOUS DIRECTIONS

Patent #:	NONE	Issue Dt:		Application #:	15296770	Filing Dt:	10/18/2016
Publication #:	US20170040274	Pub Dt:	02/09/2017
Title:	BOND PAD STRUCTURE FOR LOW TEMPERATURE FLIP CHIP BONDING

Patent #:	10002965	Issue Dt:	06/19/2018	Application #:	15298648	Filing Dt:	10/20/2016
Publication #:	US20170125578	Pub Dt:	05/04/2017
Title:	FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH DUAL STRAINED CHANNELS WITH SOLID PHASE DOPING

Patent #:	10718806	Issue Dt:	07/21/2020	Application #:	15299824	Filing Dt:	10/21/2016
Publication #:	US20180113166	Pub Dt:	04/26/2018
Title:	HIGH SPEED AND HIGH PRECISION CHARACTERIZATION OF VTSAT AND VTLIN OF FET ARRAYS

Patent #:	10957588	Issue Dt:	03/23/2021	Application #:	15333874	Filing Dt:	10/25/2016
Publication #:	US20170062331	Pub Dt:	03/02/2017
Title:	CHAMFERLESS VIA STRUCTURES

Patent #:	10468310	Issue Dt:	11/05/2019	Application #:	15334964	Filing Dt:	10/26/2016
Publication #:	US20180114730	Pub Dt:	04/26/2018
Title:	SPACER INTEGRATION SCHEME FOR NFET AND PFET DEVICES

Patent #:	RE47630	Issue Dt:	10/01/2019	Application #:	15335313	Filing Dt:	10/26/2016
Title:	SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM

Patent #:	10056408	Issue Dt:	08/21/2018	Application #:	15335549	Filing Dt:	10/27/2016
Publication #:	US20170047350	Pub Dt:	02/16/2017
Title:	STRUCTURE AND METHOD TO FORM A FINFET DEVICE

Patent #:	9679805	Issue Dt:	06/13/2017	Application #:	15336589	Filing Dt:	10/27/2016
Publication #:	US20170047247	Pub Dt:	02/16/2017
Title:	SELF-ALIGNED BACK END OF LINE CUT

Patent #:	9905707	Issue Dt:	02/27/2018	Application #:	15337026	Filing Dt:	10/28/2016
Title:	MOS CAPACITIVE STRUCTURE OF REDUCED CAPACITANCE VARIABILITY

Patent #:	10177241	Issue Dt:	01/08/2019	Application #:	15337254	Filing Dt:	10/28/2016
Publication #:	US20180122919	Pub Dt:	05/03/2018
Title:	METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE THE ACTIVE REGION AND AN AIR GAP ADJACENT THE GATE OF THE TRANSISTOR

Patent #:	9972721	Issue Dt:	05/15/2018	Application #:	15337368	Filing Dt:	10/28/2016
Publication #:	US20180122956	Pub Dt:	05/03/2018
Title:	THICK FDSOI SOURCE-DRAIN IMPROVEMENT

Patent #:	9842845	Issue Dt:	12/12/2017	Application #:	15337441	Filing Dt:	10/28/2016
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	9831124	Issue Dt:	11/28/2017	Application #:	15338070	Filing Dt:	10/28/2016
Title:	INTERCONNECT STRUCTURES

Patent #:	10181468	Issue Dt:	01/15/2019	Application #:	15338512	Filing Dt:	10/31/2016
Publication #:	US20180122795	Pub Dt:	05/03/2018
Title:	MEMORY CELL WITH ASYMMETRICAL TRANSISTOR, ASYMMETRICAL TRANSISTOR AND METHOD OF FORMING

Patent #:	10439031	Issue Dt:	10/08/2019	Application #:	15338925	Filing Dt:	10/31/2016
Publication #:	US20180122913	Pub Dt:	05/03/2018
Title:	INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND ELECTRICAL FUSES

Patent #:	10446399	Issue Dt:	10/15/2019	Application #:	15339497	Filing Dt:	10/31/2016
Publication #:	US20180122644	Pub Dt:	05/03/2018
Title:	HARD MASK LAYER TO REDUCE LOSS OF ISOLATION MATERIAL DURING DUMMY GATE REMOVAL

Patent #:	NONE	Issue Dt:		Application #:	15340181	Filing Dt:	11/01/2016
Publication #:	US20170047248	Pub Dt:	02/16/2017
Title:	FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES

Patent #:	NONE	Issue Dt:		Application #:	15340491	Filing Dt:	11/01/2016
Publication #:	US20170053982	Pub Dt:	02/23/2017
Title:	SERIES RESISTANCE REDUCTION IN VERTICALLY STACKED SILICON NANOWIRE TRANSISTORS

Patent #:	9806078	Issue Dt:	10/31/2017	Application #:	15341240	Filing Dt:	11/02/2016
Title:	FINFET SPACER FORMATION ON GATE SIDEWALLS, BETWEEN THE CHANNEL AND SOURCE/DRAIN REGIONS

Patent #:	9853117	Issue Dt:	12/26/2017	Application #:	15342396	Filing Dt:	11/03/2016
Publication #:	US20170077099	Pub Dt:	03/16/2017
Title:	SPACER CHAMFERING GATE STACK SCHEME

Patent #:	9793157	Issue Dt:	10/17/2017	Application #:	15342440	Filing Dt:	11/03/2016
Publication #:	US20170125284	Pub Dt:	05/04/2017
Title:	ETCH STOP FOR AIRGAP PROTECTION

Patent #:	9876010	Issue Dt:	01/23/2018	Application #:	15342464	Filing Dt:	11/03/2016
Title:	RESISTOR DISPOSED DIRECTLY UPON A SAC CAP OF A GATE STRUCTURE OF A SEMICONDUCTOR STRUCTURE

Patent #:	9773781	Issue Dt:	09/26/2017	Application #:	15342498	Filing Dt:	11/03/2016
Title:	RESISTOR AND CAPACITOR DISPOSED DIRECTLY UPON A SAC CAP OF A GATE STRUCTURE OF A SEMICONDUCTOR STRUCTURE

Patent #:	9842741	Issue Dt:	12/12/2017	Application #:	15342794	Filing Dt:	11/03/2016
Publication #:	US20170076954	Pub Dt:	03/16/2017
Title:	REMOVAL OF SEMICONDUCTOR GROWTH DEFECTS

Patent #:	9929057	Issue Dt:	03/27/2018	Application #:	15342801	Filing Dt:	11/03/2016
Publication #:	US20170076987	Pub Dt:	03/16/2017
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	10164104	Issue Dt:	12/25/2018	Application #:	15343590	Filing Dt:	11/04/2016
Publication #:	US20180130899	Pub Dt:	05/10/2018
Title:	METHOD TO FORM AIR-GAP SPACERS AND AIR-GAP SPACER-CONTAINING STRUCTURES

Patent #:	10115807	Issue Dt:	10/30/2018	Application #:	15343821	Filing Dt:	11/04/2016
Publication #:	US20170141214	Pub Dt:	05/18/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR IMPROVED PERFORMANCE USING TALL FINS IN FINFET DEVICES

Patent #:	9847347	Issue Dt:	12/19/2017	Application #:	15344856	Filing Dt:	11/07/2016
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AT A SEMICONDUCTOR-ON-INSULATOR REGION AND A SECOND TRANSISTOR AT A BULK REGION AND METHOD FOR THE FORMATION THEREOF

Patent #:	9978836	Issue Dt:	05/22/2018	Application #:	15344862	Filing Dt:	11/07/2016
Publication #:	US20180130878	Pub Dt:	05/10/2018
Title:	NANOSTRUCTURE FIELD-EFFECT TRANSISTORS WITH ENHANCED MOBILITY SOURCE/DRAIN REGIONS

Patent #:	10002932	Issue Dt:	06/19/2018	Application #:	15345137	Filing Dt:	11/07/2016
Publication #:	US20180130889	Pub Dt:	05/10/2018
Title:	SELF-ALIGNED CONTACT PROTECTION USING REINFORCED GATE CAP AND SPACER PORTIONS

Patent #:	10256204	Issue Dt:	04/09/2019	Application #:	15345608	Filing Dt:	11/08/2016
Publication #:	US20180130733	Pub Dt:	05/10/2018
Title:	SEPARATION OF INTEGRATED CIRCUIT STRUCTURE FROM ADJACENT CHIP

Patent #:	9984932	Issue Dt:	05/29/2018	Application #:	15345612	Filing Dt:	11/08/2016
Publication #:	US20180130711	Pub Dt:	05/10/2018
Title:	SEMICONDUCTOR FIN LOOP FOR USE WITH DIFFUSION BREAK

Patent #:	9966456	Issue Dt:	05/08/2018	Application #:	15345644	Filing Dt:	11/08/2016
Publication #:	US20180130895	Pub Dt:	05/10/2018
Title:	METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE

Patent #:	NONE	Issue Dt:		Application #:	15345858	Filing Dt:	11/08/2016
Publication #:	US20180130702	Pub Dt:	05/10/2018
Title:	ENCAPSULATION OF COBALT METALLIZATION

Patent #:	10262892	Issue Dt:	04/16/2019	Application #:	15345882	Filing Dt:	11/08/2016
Publication #:	US20180130699	Pub Dt:	05/10/2018
Title:	SKIP VIA STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	15346504	Filing Dt:	11/08/2016
Publication #:	US20170300608	Pub Dt:	10/19/2017
Title:	METHOD, SYSTEM AND PROGRAM PRODUCT FOR SADP-FRIENDLY INTERCONNECT STRUCTURE TRACK GENERATION

Patent #:	10043708	Issue Dt:	08/07/2018	Application #:	15347119	Filing Dt:	11/09/2016
Publication #:	US20180130703	Pub Dt:	05/10/2018
Title:	STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS

Patent #:	9875936	Issue Dt:	01/23/2018	Application #:	15348109	Filing Dt:	11/10/2016
Title:	SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH

Patent #:	NONE	Issue Dt:		Application #:	15348356	Filing Dt:	11/10/2016
Publication #:	US20180130891	Pub Dt:	05/10/2018
Title:	GATE STRUCTURES

Patent #:	9842762	Issue Dt:	12/12/2017	Application #:	15349306	Filing Dt:	11/11/2016
Title:	METHOD OF MANUFACTURING A SEMICONDUCTOR WAFER HAVING AN SOI CONFIGURATION

Patent #:	9818876	Issue Dt:	11/14/2017	Application #:	15349358	Filing Dt:	11/11/2016
Title:	METHOD FOR FABRICATING A FINFET METALLIZATION ARCHITECTURE USING A SELF-ALIGNED CONTACT ETCH

Patent #:	9847416	Issue Dt:	12/19/2017	Application #:	15351597	Filing Dt:	11/15/2016
Title:	PERFORMANCE-ENHANCED VERTICAL DEVICE AND METHOD OF FORMING THEREOF

Patent #:	NONE	Issue Dt:		Application #:	15351678	Filing Dt:	11/15/2016
Publication #:	US20180138209	Pub Dt:	05/17/2018
Title:	SEMICONDUCTOR SUBSTRATE WITH METALLIC DOPED BURIED OXIDE

Patent #:	9972494	Issue Dt:	05/15/2018	Application #:	15351747	Filing Dt:	11/15/2016
Publication #:	US20180138046	Pub Dt:	05/17/2018
Title:	METHOD AND STRUCTURE TO CONTROL CHANNEL LENGTH IN VERTICAL FET DEVICE

Patent #:	NONE	Issue Dt:		Application #:	15351750	Filing Dt:	11/15/2016
Publication #:	US20180138123	Pub Dt:	05/17/2018
Title:	INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

Patent #:	NONE	Issue Dt:		Application #:	15351753	Filing Dt:	11/15/2016
Publication #:	US20170062609	Pub Dt:	03/02/2017
Title:	HIGH VOLTAGE FINFET STRUCTURE WITH SHAPED DRIFT REGION

Patent #:	10446653	Issue Dt:	10/15/2019	Application #:	15351893	Filing Dt:	11/15/2016
Publication #:	US20180138279	Pub Dt:	05/17/2018
Title:	TRANSISTOR-BASED SEMICONDUCTOR DEVICE WITH AIR-GAP SPACERS AND GATE CONTACT OVER ACTIVE AREA

100

Patent #:	9865473	Issue Dt:	01/09/2018	Application #:	15352139	Filing Dt:	11/15/2016
Title:	METHODS OF FORMING SEMICONDUCTOR DEVICES USING SEMI-BIDIRECTIONAL PATTERNING AND ISLANDS

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

440 STONE BREAK ROAD EXTENSION

MALTA, NEW YORK 12020

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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