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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 164 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
9893086
Issue Dt:
02/13/2018
Application #:
15352654
Filing Dt:
11/16/2016
Title:
CONTACT PUNCH THROUGH MITIGATION IN SOI SUBSTRATE
2
Patent #:
NONE
Issue Dt:
Application #:
15352963
Filing Dt:
11/16/2016
Publication #:
US20180138177
Pub Dt:
05/17/2018
Title:
FORMATION OF BAND-EDGE CONTACTS
3
Patent #:
9917162
Issue Dt:
03/13/2018
Application #:
15353352
Filing Dt:
11/16/2016
Publication #:
US20170288030
Pub Dt:
10/05/2017
Title:
FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH
4
Patent #:
NONE
Issue Dt:
Application #:
15353771
Filing Dt:
11/17/2016
Publication #:
US20180138285
Pub Dt:
05/17/2018
Title:
METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE WITH SILICIDE REIGON
5
Patent #:
NONE
Issue Dt:
Application #:
15354047
Filing Dt:
11/17/2016
Publication #:
US20180138307
Pub Dt:
05/17/2018
Title:
TUNNEL FINFET WITH SELF-ALIGNED GATE
6
Patent #:
10115738
Issue Dt:
10/30/2018
Application #:
15354205
Filing Dt:
11/17/2016
Publication #:
US20180138203
Pub Dt:
05/17/2018
Title:
SELF-ALIGNED BACK-PLANE AND WELL CONTACTS FOR FULLY DEPLETED SILICON ON INSULATOR DEVICE
7
Patent #:
9941162
Issue Dt:
04/10/2018
Application #:
15354212
Filing Dt:
11/17/2016
Title:
SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS
8
Patent #:
10079248
Issue Dt:
09/18/2018
Application #:
15355231
Filing Dt:
11/18/2016
Publication #:
US20180145088
Pub Dt:
05/24/2018
Title:
FIELD-EFFECT TRANSISTORS WITH A BURIED BODY CONTACT
9
Patent #:
10553353
Issue Dt:
02/04/2020
Application #:
15355584
Filing Dt:
11/18/2016
Publication #:
US20180144857
Pub Dt:
05/24/2018
Title:
Parallel Stacked Inductor for High-Q and High Current Handling and Method of Making the Same
10
Patent #:
10090202
Issue Dt:
10/02/2018
Application #:
15357287
Filing Dt:
11/21/2016
Publication #:
US20170125299
Pub Dt:
05/04/2017
Title:
SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
11
Patent #:
10056292
Issue Dt:
08/21/2018
Application #:
15359037
Filing Dt:
11/22/2016
Publication #:
US20180144979
Pub Dt:
05/24/2018
Title:
SELF-ALIGNED LITHOGRAPHIC PATTERNING
12
Patent #:
10056291
Issue Dt:
08/21/2018
Application #:
15360255
Filing Dt:
11/23/2016
Publication #:
US20180144976
Pub Dt:
05/24/2018
Title:
POST SPACER SELF-ALIGNED CUTS
13
Patent #:
10153361
Issue Dt:
12/11/2018
Application #:
15360295
Filing Dt:
11/23/2016
Publication #:
US20180145160
Pub Dt:
05/24/2018
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR DEVICE INTEGRATION SCHEMES ON A SAME WAFER
14
Patent #:
9825032
Issue Dt:
11/21/2017
Application #:
15360537
Filing Dt:
11/23/2016
Title:
METAL LAYER ROUTING LEVEL FOR VERTICAL FET SRAM AND LOGIC CELL SCALING
15
Patent #:
10008582
Issue Dt:
06/26/2018
Application #:
15361790
Filing Dt:
11/28/2016
Publication #:
US20180151689
Pub Dt:
05/31/2018
Title:
SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS
16
Patent #:
10121706
Issue Dt:
11/06/2018
Application #:
15361809
Filing Dt:
11/28/2016
Publication #:
US20180151449
Pub Dt:
05/31/2018
Title:
SEMICONDUCTOR STRUCTURE INCLUDING TWO-DIMENSIONAL AND THREE-DIMENSIONAL BONDING MATERIALS
17
Patent #:
9935012
Issue Dt:
04/03/2018
Application #:
15361824
Filing Dt:
11/28/2016
Title:
METHODS FOR FORMING DIFFERENT SHAPES IN DIFFERENT REGIONS OF THE SAME LAYER
18
Patent #:
9882024
Issue Dt:
01/30/2018
Application #:
15361994
Filing Dt:
11/28/2016
Publication #:
US20170077266
Pub Dt:
03/16/2017
Title:
EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS
19
Patent #:
9852986
Issue Dt:
12/26/2017
Application #:
15362035
Filing Dt:
11/28/2016
Title:
METHOD OF PATTERNING PILLARS TO FORM VARIABLE CONTINUITY CUTS IN INTERCONNECTION LINES OF AN INTEGRATED CIRCUIT
20
Patent #:
9899324
Issue Dt:
02/20/2018
Application #:
15362499
Filing Dt:
11/28/2016
Title:
STRUCTURE AND METHOD OF CONDUCTIVE BUS BAR FOR RESISTIVE SEED SUBSTRATE PLATING
21
Patent #:
NONE
Issue Dt:
Application #:
15363267
Filing Dt:
11/29/2016
Publication #:
US20180151461
Pub Dt:
05/31/2018
Title:
STIFFENER FOR FAN-OUT WAFER LEVEL PACKAGING AND METHOD OF MANUFACTURING
22
Patent #:
9947769
Issue Dt:
04/17/2018
Application #:
15363461
Filing Dt:
11/29/2016
Title:
MULTIPLE-LAYER SPACERS FOR FIELD-EFFECT TRANSISTORS
23
Patent #:
9922929
Issue Dt:
03/20/2018
Application #:
15363513
Filing Dt:
11/29/2016
Title:
SELF ALIGNED INTERCONNECT STRUCTURES
24
Patent #:
10002940
Issue Dt:
06/19/2018
Application #:
15363563
Filing Dt:
11/29/2016
Publication #:
US20170077259
Pub Dt:
03/16/2017
Title:
SPACER CHAMFERING GATE STACK SCHEME
25
Patent #:
9929020
Issue Dt:
03/27/2018
Application #:
15363596
Filing Dt:
11/29/2016
Publication #:
US20170092507
Pub Dt:
03/30/2017
Title:
METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME
26
Patent #:
10475660
Issue Dt:
11/12/2019
Application #:
15363607
Filing Dt:
11/29/2016
Publication #:
US20170092721
Pub Dt:
03/30/2017
Title:
METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME
27
Patent #:
10079242
Issue Dt:
09/18/2018
Application #:
15366425
Filing Dt:
12/01/2016
Publication #:
US20180158835
Pub Dt:
06/07/2018
Title:
LOGIC AND FLASH FIELD-EFFECT TRANSISTORS
28
Patent #:
9805988
Issue Dt:
10/31/2017
Application #:
15366514
Filing Dt:
12/01/2016
Title:
METHOD OF FORMING SEMICONDUCTOR STRUCTURE INCLUDING SUSPENDED SEMICONDUCTOR LAYER AND RESULTING STRUCTURE
29
Patent #:
10062445
Issue Dt:
08/28/2018
Application #:
15367815
Filing Dt:
12/02/2016
Publication #:
US20180158532
Pub Dt:
06/07/2018
Title:
PARALLEL PROGRAMMING OF ONE TIME PROGRAMMABLE MEMORY ARRAY FOR REDUCED TEST TIME
30
Patent #:
10014234
Issue Dt:
07/03/2018
Application #:
15367888
Filing Dt:
12/02/2016
Publication #:
US20180158745
Pub Dt:
06/07/2018
Title:
SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL INCLUDING LONG VIA LINES
31
Patent #:
9761491
Issue Dt:
09/12/2017
Application #:
15370404
Filing Dt:
12/06/2016
Title:
SELF-ALIGNED DEEP CONTACT FOR VERTICAL FET
32
Patent #:
NONE
Issue Dt:
Application #:
15370555
Filing Dt:
12/06/2016
Publication #:
US20180158821
Pub Dt:
06/07/2018
Title:
GATE STRUCTURES WITH LOW RESISTANCE
33
Patent #:
10497610
Issue Dt:
12/03/2019
Application #:
15370585
Filing Dt:
12/06/2016
Publication #:
US20180158723
Pub Dt:
06/07/2018
Title:
DUAL PHOTORESIST APPROACH TO LITHOGRAPHIC PATTERNING FOR PITCH REDUCTION
34
Patent #:
10643790
Issue Dt:
05/05/2020
Application #:
15370757
Filing Dt:
12/06/2016
Publication #:
US20170084390
Pub Dt:
03/23/2017
Title:
Manufacturing Method for 3D Multipath Inductor
35
Patent #:
9875939
Issue Dt:
01/23/2018
Application #:
15373129
Filing Dt:
12/08/2016
Title:
METHODS OF FORMING UNIFORM AND PITCH INDEPENDENT FIN RECESS
36
Patent #:
9899321
Issue Dt:
02/20/2018
Application #:
15373691
Filing Dt:
12/09/2016
Title:
METHODS OF FORMING A GATE CONTACT FOR A SEMICONDUCTOR DEVICE ABOVE THE ACTIVE REGION
37
Patent #:
10062617
Issue Dt:
08/28/2018
Application #:
15373852
Filing Dt:
12/09/2016
Publication #:
US20170256462
Pub Dt:
09/07/2017
Title:
METHOD AND STRUCTURE FOR SRB ELASTIC RELAXATION
38
Patent #:
NONE
Issue Dt:
Application #:
15373898
Filing Dt:
12/09/2016
Publication #:
US20180166402
Pub Dt:
06/14/2018
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING AN INTEGRATED EFUSE HAVING DIELECTRIC LAYERS OF DIFFERENTIAL THICKNESS
39
Patent #:
10068918
Issue Dt:
09/04/2018
Application #:
15375890
Filing Dt:
12/12/2016
Publication #:
US20170104005
Pub Dt:
04/13/2017
Title:
CONTACTING SOI SUBSTRATES
40
Patent #:
9847290
Issue Dt:
12/19/2017
Application #:
15375924
Filing Dt:
12/12/2016
Title:
THROUGH-SILICON VIA WITH IMPROVED SUBSTRATE CONTACT FOR REDUCED THROUGH-SILICON VIA (TSV) CAPACITANCE VARIABILITY
41
Patent #:
10319627
Issue Dt:
06/11/2019
Application #:
15376831
Filing Dt:
12/13/2016
Publication #:
US20180166319
Pub Dt:
06/14/2018
Title:
AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS
42
Patent #:
9859120
Issue Dt:
01/02/2018
Application #:
15377125
Filing Dt:
12/13/2016
Title:
METHOD OF MAKING SELF-ALIGNED CONTINUITY CUTS IN MANDREL AND NON-MANDREL METAL LINES
43
Patent #:
NONE
Issue Dt:
Application #:
15377473
Filing Dt:
12/13/2016
Publication #:
US20170092585
Pub Dt:
03/30/2017
Title:
SELF-ALIGNED GATE TIE-DOWN CONTACTS WITH SELECTIVE ETCH STOP LINER
44
Patent #:
NONE
Issue Dt:
Application #:
15377496
Filing Dt:
12/13/2016
Publication #:
US20180166356
Pub Dt:
06/14/2018
Title:
FAN-OUT CIRCUIT PACKAGING WITH INTEGRATED LID
45
Patent #:
9773680
Issue Dt:
09/26/2017
Application #:
15377503
Filing Dt:
12/13/2016
Title:
ADVANCED METHOD FOR SCALED SRAM WITH FLEXIBLE ACTIVE PITCH
46
Patent #:
10038413
Issue Dt:
07/31/2018
Application #:
15377580
Filing Dt:
12/13/2016
Publication #:
US20180167038
Pub Dt:
06/14/2018
Title:
FULLY DEPLETED SILICON ON INSULATOR POWER AMPLIFIER
47
Patent #:
10043753
Issue Dt:
08/07/2018
Application #:
15377592
Filing Dt:
12/13/2016
Publication #:
US20180166383
Pub Dt:
06/14/2018
Title:
AIRGAPS TO ISOLATE METALLIZATION FEATURES
48
Patent #:
10296698
Issue Dt:
05/21/2019
Application #:
15378122
Filing Dt:
12/14/2016
Publication #:
US20180165402
Pub Dt:
06/14/2018
Title:
FORMING MULTI-SIZED THROUGH-SILICON-VIA (TSV) STRUCTURES
49
Patent #:
9780197
Issue Dt:
10/03/2017
Application #:
15378596
Filing Dt:
12/14/2016
Title:
METHOD OF CONTROLLING VFET CHANNEL LENGTH
50
Patent #:
10424664
Issue Dt:
09/24/2019
Application #:
15378990
Filing Dt:
12/14/2016
Publication #:
US20180166566
Pub Dt:
06/14/2018
Title:
POLY GATE EXTENSION SOURCE TO BODY CONTACT
51
Patent #:
10043703
Issue Dt:
08/07/2018
Application #:
15379605
Filing Dt:
12/15/2016
Publication #:
US20180174894
Pub Dt:
06/21/2018
Title:
APPARATUS AND METHOD FOR FORMING INTERCONNECTION LINES HAVING VARIABLE PITCH AND VARIABLE WIDTHS
52
Patent #:
9812351
Issue Dt:
11/07/2017
Application #:
15379645
Filing Dt:
12/15/2016
Title:
INTERCONNECTION CELLS HAVING VARIABLE WIDTH METAL LINES AND FULLY-SELF ALIGNED CONTINUITY CUTS
53
Patent #:
10002786
Issue Dt:
06/19/2018
Application #:
15379707
Filing Dt:
12/15/2016
Publication #:
US20180174895
Pub Dt:
06/21/2018
Title:
INTERCONNECTION CELLS HAVING VARIABLE WIDTH METAL LINES AND FULLY-SELF ALIGNED VARIABLE LENGTH CONTINUITY CUTS
54
Patent #:
9887127
Issue Dt:
02/06/2018
Application #:
15379740
Filing Dt:
12/15/2016
Title:
INTERCONNECTION LINES HAVING VARIABLE WIDTHS AND PARTIALLY SELF-ALIGNED CONTINUITY CUTS
55
Patent #:
10128151
Issue Dt:
11/13/2018
Application #:
15381826
Filing Dt:
12/16/2016
Publication #:
US20180174965
Pub Dt:
06/21/2018
Title:
DEVICES AND METHODS OF COBALT FILL METALLIZATION
56
Patent #:
10014397
Issue Dt:
07/03/2018
Application #:
15383171
Filing Dt:
12/19/2016
Publication #:
US20180175180
Pub Dt:
06/21/2018
Title:
BIPOLAR JUNCTION TRANSISTORS WITH A COMBINED VERTICAL-LATERAL ARCHITECTURE
57
Patent #:
9916982
Issue Dt:
03/13/2018
Application #:
15383461
Filing Dt:
12/19/2016
Title:
DIELECTRIC PRESERVATION IN A REPLACEMENT GATE PROCESS
58
Patent #:
NONE
Issue Dt:
Application #:
15384706
Filing Dt:
12/20/2016
Publication #:
US20180175209
Pub Dt:
06/21/2018
Title:
SEMICONDUCTOR STRUCTURE INCLUDING ONE OR MORE NONVOLATILE MEMORY CELLS AND METHOD FOR THE FORMATION THEREOF
59
Patent #:
10026883
Issue Dt:
07/17/2018
Application #:
15385068
Filing Dt:
12/20/2016
Publication #:
US20180175266
Pub Dt:
06/21/2018
Title:
WAFER BOND INTERCONNECT STRUCTURES
60
Patent #:
9953831
Issue Dt:
04/24/2018
Application #:
15385949
Filing Dt:
12/21/2016
Title:
DEVICE STRUCTURES WITH MULTIPLE NITRIDED LAYERS
61
Patent #:
10446442
Issue Dt:
10/15/2019
Application #:
15386097
Filing Dt:
12/21/2016
Publication #:
US20180174948
Pub Dt:
06/21/2018
Title:
INTEGRATED CIRCUIT CHIP WITH MOLDING COMPOUND HANDLER SUBSTRATE AND METHOD
62
Patent #:
10062711
Issue Dt:
08/28/2018
Application #:
15386507
Filing Dt:
12/21/2016
Publication #:
US20180175064
Pub Dt:
06/21/2018
Title:
WAFERS AND DEVICE STRUCTURES WITH BODY CONTACTS
63
Patent #:
10109599
Issue Dt:
10/23/2018
Application #:
15387120
Filing Dt:
12/21/2016
Publication #:
US20180174982
Pub Dt:
06/21/2018
Title:
INTEGRATED CIRCUIT STRUCTURE WITH CONTINUOUS METAL CRACK STOP
64
Patent #:
9929157
Issue Dt:
03/27/2018
Application #:
15387933
Filing Dt:
12/22/2016
Title:
TALL SINGLE-FIN FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS
65
Patent #:
9972495
Issue Dt:
05/15/2018
Application #:
15387984
Filing Dt:
12/22/2016
Title:
LOW-K DIELECTRIC SPACER FOR A GATE CUT
66
Patent #:
10068815
Issue Dt:
09/04/2018
Application #:
15388136
Filing Dt:
12/22/2016
Publication #:
US20180182677
Pub Dt:
06/28/2018
Title:
TEST STRUCTURE FOR TESTING VIA RESISTANCE AND METHOD
67
Patent #:
9929048
Issue Dt:
03/27/2018
Application #:
15388400
Filing Dt:
12/22/2016
Title:
MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT
68
Patent #:
10020260
Issue Dt:
07/10/2018
Application #:
15388530
Filing Dt:
12/22/2016
Publication #:
US20180182708
Pub Dt:
06/28/2018
Title:
CORROSION AND/OR ETCH PROTECTION LAYER FOR CONTACTS AND INTERCONNECT METALLIZATION INTEGRATION
69
Patent #:
9941301
Issue Dt:
04/10/2018
Application #:
15388772
Filing Dt:
12/22/2016
Title:
FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK EXPOSED REGIONS
70
Patent #:
10347546
Issue Dt:
07/09/2019
Application #:
15389632
Filing Dt:
12/23/2016
Publication #:
US20180182675
Pub Dt:
06/28/2018
Title:
INTEGRATED CIRCUIT STRUCTURE INCLUDING POWER RAIL AND TAPPING WIRE WITH METHOD OF FORMING SAME
71
Patent #:
10014409
Issue Dt:
07/03/2018
Application #:
15393400
Filing Dt:
12/29/2016
Publication #:
US20180190817
Pub Dt:
07/05/2018
Title:
METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FINFET DEVICE
72
Patent #:
NONE
Issue Dt:
Application #:
15393488
Filing Dt:
12/29/2016
Publication #:
US20180190546
Pub Dt:
07/05/2018
Title:
METHOD FOR FORMING REPLACEMENT METAL GATE AND RELATED DEVICE
73
Patent #:
9824748
Issue Dt:
11/21/2017
Application #:
15395036
Filing Dt:
12/30/2016
Title:
SRAM BITCELL STRUCTURES FACILITATING BIASING OF PULL-UP TRANSISTORS
74
Patent #:
9935201
Issue Dt:
04/03/2018
Application #:
15396743
Filing Dt:
01/02/2017
Publication #:
US20170110583
Pub Dt:
04/20/2017
Title:
HIGH DOPED III-V SOURCE/DRAIN JUNCTIONS FOR FIELD EFFECT TRANSISTORS
75
Patent #:
9799661
Issue Dt:
10/24/2017
Application #:
15397004
Filing Dt:
01/03/2017
Title:
SRAM BITCELL STRUCTURES FACILITATING BIASING OF PULL-DOWN TRANSISTORS
76
Patent #:
9734897
Issue Dt:
08/15/2017
Application #:
15397021
Filing Dt:
01/03/2017
Title:
SRAM BITCELL STRUCTURES FACILITATING BIASING OF PASS GATE TRANSISTORS
77
Patent #:
NONE
Issue Dt:
Application #:
15397967
Filing Dt:
01/04/2017
Publication #:
US20180190792
Pub Dt:
07/05/2018
Title:
METHOD OF FORMING SEMICONDUCTOR STRUCTURE AND RESULTING STRUCTURE
78
Patent #:
9917103
Issue Dt:
03/13/2018
Application #:
15397978
Filing Dt:
01/04/2017
Title:
DIFFUSION BREAK FORMING AFTER SOURCE/DRAIN FORMING AND RELATED IC STRUCTURE
79
Patent #:
9799748
Issue Dt:
10/24/2017
Application #:
15398335
Filing Dt:
01/04/2017
Title:
METHOD OF FORMING INNER SPACERS ON A NANO-SHEET/WIRE DEVICE
80
Patent #:
10347622
Issue Dt:
07/09/2019
Application #:
15398946
Filing Dt:
01/05/2017
Publication #:
US20180190644
Pub Dt:
07/05/2018
Title:
SILICON-CONTROLLED RECTIFIERS HAVING A CATHODE COUPLED BY A CONTACT WITH A DIODE TRIGGER
81
Patent #:
10204861
Issue Dt:
02/12/2019
Application #:
15399200
Filing Dt:
01/05/2017
Publication #:
US20180190588
Pub Dt:
07/05/2018
Title:
Structure with Local Contact for Shorting a Gate Electrode to a Source/Drain Region
82
Patent #:
9893157
Issue Dt:
02/13/2018
Application #:
15401281
Filing Dt:
01/09/2017
Title:
STRUCTURES WITH CONTACT TRENCHES AND ISOLATION TRENCHES
83
Patent #:
10157927
Issue Dt:
12/18/2018
Application #:
15404754
Filing Dt:
01/12/2017
Publication #:
US20180197867
Pub Dt:
07/12/2018
Title:
SEMICONDUCTOR MEMORY DEVICES HAVING AN UNDERCUT SOURCE/DRAIN REGION
84
Patent #:
NONE
Issue Dt:
Application #:
15405026
Filing Dt:
01/12/2017
Publication #:
US20180197734
Pub Dt:
07/12/2018
Title:
BUFFER LAYER TO INHIBIT WORMHOLES IN SEMICONDUCTOR FABRICATION
85
Patent #:
10146132
Issue Dt:
12/04/2018
Application #:
15405448
Filing Dt:
01/13/2017
Publication #:
US20180203359
Pub Dt:
07/19/2018
Title:
MOBILE DISPENSE DEVICE FOR CHEMICALS USED IN MICRO-PROCESSING
86
Patent #:
10056481
Issue Dt:
08/21/2018
Application #:
15405495
Filing Dt:
01/13/2017
Publication #:
US20180204944
Pub Dt:
07/19/2018
Title:
SEMICONDUCTOR DEVICE STRUCTURE
87
Patent #:
9812324
Issue Dt:
11/07/2017
Application #:
15405789
Filing Dt:
01/13/2017
Title:
METHODS TO CONTROL FIN TIP PLACEMENT
88
Patent #:
NONE
Issue Dt:
Application #:
15407407
Filing Dt:
01/17/2017
Publication #:
US20180204929
Pub Dt:
07/19/2018
Title:
METAL GATE FORMATION USING AN ENERGY REMOVAL FILM
89
Patent #:
NONE
Issue Dt:
Application #:
15407872
Filing Dt:
01/17/2017
Publication #:
US20170125288
Pub Dt:
05/04/2017
Title:
ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS
90
Patent #:
10224330
Issue Dt:
03/05/2019
Application #:
15407960
Filing Dt:
01/17/2017
Publication #:
US20180204840
Pub Dt:
07/19/2018
Title:
SELF-ALIGNED JUNCTION STRUCTURES
91
Patent #:
10026824
Issue Dt:
07/17/2018
Application #:
15408540
Filing Dt:
01/18/2017
Publication #:
US20180204927
Pub Dt:
07/19/2018
Title:
AIR-GAP GATE SIDEWALL SPACER AND METHOD
92
Patent #:
10290574
Issue Dt:
05/14/2019
Application #:
15408883
Filing Dt:
01/18/2017
Publication #:
US20180204796
Pub Dt:
07/19/2018
Title:
EMBEDDED METAL-INSULATOR-METAL (MIM) DECOUPLING CAPACITOR IN MONOLITIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) STRUCTURE
93
Patent #:
9870942
Issue Dt:
01/16/2018
Application #:
15410032
Filing Dt:
01/19/2017
Title:
METHOD OF FORMING MANDREL AND NON-MANDREL METAL LINES HAVING VARIABLE WIDTHS
94
Patent #:
10026818
Issue Dt:
07/17/2018
Application #:
15410159
Filing Dt:
01/19/2017
Publication #:
US20180204920
Pub Dt:
07/19/2018
Title:
FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD
95
Patent #:
9905476
Issue Dt:
02/27/2018
Application #:
15412598
Filing Dt:
01/23/2017
Publication #:
US20170133278
Pub Dt:
05/11/2017
Title:
ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs
96
Patent #:
10032668
Issue Dt:
07/24/2018
Application #:
15412784
Filing Dt:
01/23/2017
Publication #:
US20170133268
Pub Dt:
05/11/2017
Title:
CHAMFERLESS VIA STRUCTURES
97
Patent #:
10109524
Issue Dt:
10/23/2018
Application #:
15413710
Filing Dt:
01/24/2017
Publication #:
US20180211873
Pub Dt:
07/26/2018
Title:
RECESSING OF LINER AND CONDUCTOR FOR VIA FORMATION
98
Patent #:
9911604
Issue Dt:
03/06/2018
Application #:
15413823
Filing Dt:
01/24/2017
Title:
SIDEWALL SPACER PATTERN FORMATION METHOD
99
Patent #:
9865543
Issue Dt:
01/09/2018
Application #:
15416152
Filing Dt:
01/26/2017
Title:
STRUCTURE AND METHOD FOR INHIBITING COBALT DIFFUSION
100
Patent #:
10153201
Issue Dt:
12/11/2018
Application #:
15417848
Filing Dt:
01/27/2017
Publication #:
US20170133265
Pub Dt:
05/11/2017
Title:
ADVANCED MOSFET CONTACT STRUCTURE TO REDUCE METAL-SEMICONDUCTOR INTERFACE RESISTANCE
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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