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Reel/Frame:	056987/0001			Pages:	1045
		Recorded:	05/12/2021
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 18026
Page 165 of 181
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Patent #:	10242946	Issue Dt:	03/26/2019	Application #:	15418001	Filing Dt:	01/27/2017
Publication #:	US20180218981	Pub Dt:	08/02/2018
Title:	CIRCUIT DESIGN HAVING ALIGNED POWER STAPLES

Patent #:	9971859	Issue Dt:	05/15/2018	Application #:	15418015	Filing Dt:	01/27/2017
Publication #:	US20170147726	Pub Dt:	05/25/2017
Title:	MODELING LOCALIZED TEMPERATURE CHANGES ON AN INTEGRATED CIRCUIT CHIP USING THERMAL POTENTIAL THEORY

Patent #:	10283505	Issue Dt:	05/07/2019	Application #:	15418996	Filing Dt:	01/30/2017
Publication #:	US20170141110	Pub Dt:	05/18/2017
Title:	DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME

Patent #:	10008415	Issue Dt:	06/26/2018	Application #:	15419346	Filing Dt:	01/30/2017
Publication #:	US20170140994	Pub Dt:	05/18/2017
Title:	GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS

Patent #:	10103119	Issue Dt:	10/16/2018	Application #:	15420362	Filing Dt:	01/31/2017
Publication #:	US20180218991	Pub Dt:	08/02/2018
Title:	METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE

Patent #:	9728456	Issue Dt:	08/08/2017	Application #:	15420467	Filing Dt:	01/31/2017
Publication #:	US20170140984	Pub Dt:	05/18/2017
Title:	INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER

Patent #:	10185312	Issue Dt:	01/22/2019	Application #:	15420749	Filing Dt:	01/31/2017
Publication #:	US20180217584	Pub Dt:	08/02/2018
Title:	INSITU TOOL HEALTH AND RECIPE QUALITY MONITORING ON A CDSEM

Patent #:	10002797	Issue Dt:	06/19/2018	Application #:	15420794	Filing Dt:	01/31/2017
Title:	CHIP INTEGRATION INCLUDING VERTICAL FIELD-EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS

Patent #:	9893063	Issue Dt:	02/13/2018	Application #:	15420967	Filing Dt:	01/31/2017
Publication #:	US20170141109	Pub Dt:	05/18/2017
Title:	SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS

Patent #:	10332834	Issue Dt:	06/25/2019	Application #:	15421698	Filing Dt:	02/01/2017
Publication #:	US20170141031	Pub Dt:	05/18/2017
Title:	SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF

Patent #:	10170309	Issue Dt:	01/01/2019	Application #:	15422689	Filing Dt:	02/15/2017
Publication #:	US20180233361	Pub Dt:	08/16/2018
Title:	DUMMY PATTERN ADDITION TO IMPROVE CD UNIFORMITY

Patent #:	9997403	Issue Dt:	06/12/2018	Application #:	15422923	Filing Dt:	02/02/2017
Publication #:	US20170243784	Pub Dt:	08/24/2017
Title:	METAL LAYER TIP TO TIP SHORT

Patent #:	10083952	Issue Dt:	09/25/2018	Application #:	15423006	Filing Dt:	02/02/2017
Publication #:	US20180219006	Pub Dt:	08/02/2018
Title:	DIODE-TRIGGERED SCHOTTKY SILICON-CONTROLLED RECTIFIER FOR FIN-FET ELECTROSTATIC DISCHARGE CONTROL

Patent #:	10068804	Issue Dt:	09/04/2018	Application #:	15423326	Filing Dt:	02/02/2017
Publication #:	US20180218947	Pub Dt:	08/02/2018
Title:	METHODS, APPARATUS AND SYSTEM FOR PROVIDING ADJUSTABLE FIN HEIGHT FOR A FINFET DEVICE

Patent #:	9761662	Issue Dt:	09/12/2017	Application #:	15423647	Filing Dt:	02/03/2017
Title:	ACTIVE AREA SHAPES REDUCING DEVICE SIZE

Patent #:	9911823	Issue Dt:	03/06/2018	Application #:	15423945	Filing Dt:	02/03/2017
Publication #:	US20170148895	Pub Dt:	05/25/2017
Title:	POC PROCESS FLOW FOR CONFORMAL RECESS FILL

Patent #:	10468149	Issue Dt:	11/05/2019	Application #:	15424200	Filing Dt:	02/03/2017
Publication #:	US20180226166	Pub Dt:	08/09/2018
Title:	EXTREME ULTRAVIOLET MIRRORS AND MASKS WITH IMPROVED REFLECTIVITY

Patent #:	10170617	Issue Dt:	01/01/2019	Application #:	15424379	Filing Dt:	02/03/2017
Publication #:	US20180226505	Pub Dt:	08/09/2018
Title:	VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

Patent #:	9831248	Issue Dt:	11/28/2017	Application #:	15425366	Filing Dt:	02/06/2017
Title:	EMBEDDED DRAM CELLS HAVING CAPACITORS WITHIN TRENCH SILICIDE TRENCHES OF A SEMICONDUCTOR STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	15425384	Filing Dt:	02/06/2017
Publication #:	US20180226292	Pub Dt:	08/09/2018
Title:	TRENCH ISOLATION FORMATION FROM THE SUBSTRATE BACK SIDE USING LAYER TRANSFER

Patent #:	10181420	Issue Dt:	01/15/2019	Application #:	15425478	Filing Dt:	02/06/2017
Publication #:	US20180226294	Pub Dt:	08/09/2018
Title:	DEVICES WITH CHAMFER-LESS VIAS MULTI-PATTERNING AND METHODS FOR FORMING CHAMFER-LESS VIAS

Patent #:	9935003	Issue Dt:	04/03/2018	Application #:	15426573	Filing Dt:	02/07/2017
Publication #:	US20170148668	Pub Dt:	05/25/2017
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	10079300	Issue Dt:	09/18/2018	Application #:	15426728	Filing Dt:	02/07/2017
Publication #:	US20170148919	Pub Dt:	05/25/2017
Title:	SEMICONDUCTOR CIRCUIT ELEMENT

Patent #:	10964687	Issue Dt:	03/30/2021	Application #:	15427128	Filing Dt:	02/08/2017
Publication #:	US20180226394	Pub Dt:	08/09/2018
Title:	FINFET ESD DEVICE WITH SCHOTTKY DIODE

Patent #:	10002835	Issue Dt:	06/19/2018	Application #:	15427156	Filing Dt:	02/08/2017
Publication #:	US20170148737	Pub Dt:	05/25/2017
Title:	STRUCTURE FOR ESTABLISHING INTERCONNECTS IN PACKAGES USING THIN INTERPOSERS

Patent #:	10964796	Issue Dt:	03/30/2021	Application #:	15427182	Filing Dt:	02/08/2017
Publication #:	US20180226347	Pub Dt:	08/09/2018
Title:	Heterojunction Bipolar Transistors With Stress Material For Improved Mobility

Patent #:	10163900	Issue Dt:	12/25/2018	Application #:	15427403	Filing Dt:	02/08/2017
Publication #:	US20180226402	Pub Dt:	08/09/2018
Title:	INTEGRATION OF VERTICAL FIELD-EFFECT TRANSISTORS AND SADDLE FIN-TYPE FIELD EFFECT TRANSISTORS

Patent #:	9947793	Issue Dt:	04/17/2018	Application #:	15427594	Filing Dt:	02/08/2017
Title:	VERTICAL PILLAR-TYPE FIELD EFFECT TRANSISTOR AND METHOD

Patent #:	10424657	Issue Dt:	09/24/2019	Application #:	15428312	Filing Dt:	02/09/2017
Publication #:	US20170154977	Pub Dt:	06/01/2017
Title:	TRI-GATE FINFET DEVICE

Patent #:	10360334	Issue Dt:	07/23/2019	Application #:	15428449	Filing Dt:	02/09/2017
Publication #:	US20180225406	Pub Dt:	08/09/2018
Title:	CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO STRAIN RELAXATION IN STANDARD CELL LIBRARY

Patent #:	9899319	Issue Dt:	02/20/2018	Application #:	15428604	Filing Dt:	02/09/2017
Publication #:	US20170154846	Pub Dt:	06/01/2017
Title:	RAISED E-FUSE

Patent #:	10020307	Issue Dt:	07/10/2018	Application #:	15429502	Filing Dt:	02/10/2017
Title:	INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME

Patent #:	10199265	Issue Dt:	02/05/2019	Application #:	15430039	Filing Dt:	02/10/2017
Publication #:	US20180233404	Pub Dt:	08/16/2018
Title:	VARIABLE SPACE MANDREL CUT FOR SELF ALIGNED DOUBLE PATTERNING

Patent #:	9953727	Issue Dt:	04/24/2018	Application #:	15430170	Filing Dt:	02/10/2017
Title:	CIRCUIT AND METHOD FOR DETECTING TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) SHORTS AND SIGNAL-MARGIN TESTING

Patent #:	11557420	Issue Dt:	01/17/2023	Application #:	15430596	Filing Dt:	02/13/2017
Publication #:	US20170154722	Pub Dt:	06/01/2017
Title:	COUPLING INDUCTORS IN AN IC DEVICE USING INTERCONNECTING ELEMENTS WITH SOLDER CAPS AND RESULTING DEVICES

Patent #:	10056469	Issue Dt:	08/21/2018	Application #:	15430647	Filing Dt:	02/13/2017
Publication #:	US20180233579	Pub Dt:	08/16/2018
Title:	GATE CUT INTEGRATION AND RELATED DEVICE

Patent #:	9812453	Issue Dt:	11/07/2017	Application #:	15431334	Filing Dt:	02/13/2017
Title:	SELF-ALIGNED SACRIFICIAL EPITAXIAL CAPPING FOR TRENCH SILICIDE

Patent #:	9865570	Issue Dt:	01/09/2018	Application #:	15431915	Filing Dt:	02/14/2017
Title:	INTEGRATED CIRCUIT PACKAGE WITH THERMALLY CONDUCTIVE PILLAR

Patent #:	10453751	Issue Dt:	10/22/2019	Application #:	15432016	Filing Dt:	02/14/2017
Publication #:	US20180261510	Pub Dt:	09/13/2018
Title:	TONE INVERSION METHOD AND STRUCTURE FOR SELECTIVE CONTACT VIA PATTERNING

Patent #:	10128352	Issue Dt:	11/13/2018	Application #:	15432372	Filing Dt:	02/14/2017
Publication #:	US20170162438	Pub Dt:	06/08/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	NONE	Issue Dt:		Application #:	15432710	Filing Dt:	02/14/2017
Publication #:	US20180233580	Pub Dt:	08/16/2018
Title:	SEMICONDUCTOR STRUCTURE WITH GATE HEIGHT SCALING

Patent #:	10573534	Issue Dt:	02/25/2020	Application #:	15433099	Filing Dt:	02/15/2017
Publication #:	US20170236721	Pub Dt:	08/17/2017
Title:	RAPID HEATING PROCESS IN THE PRODUCTION OF SEMICONDUCTOR COMPONENTS

Patent #:	10658494	Issue Dt:	05/19/2020	Application #:	15433141	Filing Dt:	02/15/2017
Publication #:	US20180233583	Pub Dt:	08/16/2018
Title:	TRANSISTORS AND METHODS OF FORMING TRANSISTORS USING VERTICAL NANOWIRES

Patent #:	10249535	Issue Dt:	04/02/2019	Application #:	15433188	Filing Dt:	02/15/2017
Publication #:	US20180233412	Pub Dt:	08/16/2018
Title:	FORMING TS CUT FOR ZERO OR NEGATIVE TS EXTENSION AND RESULTING DEVICE

Patent #:	NONE	Issue Dt:		Application #:	15433330	Filing Dt:	02/15/2017
Publication #:	US20170162688	Pub Dt:	06/08/2017
Title:	METAL GATE STRUCTURE AND METHOD OF FORMATION

Patent #:	9847390	Issue Dt:	12/19/2017	Application #:	15434205	Filing Dt:	02/16/2017
Title:	SELF-ALIGNED WRAP-AROUND CONTACTS FOR NANOSHEET DEVICES

Patent #:	9935018	Issue Dt:	04/03/2018	Application #:	15436281	Filing Dt:	02/17/2017
Title:	METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH DIFFERENT EFFECTIVE GATE LENGTHS

Patent #:	10290698	Issue Dt:	05/14/2019	Application #:	15437057	Filing Dt:	02/20/2017
Publication #:	US20170162647	Pub Dt:	06/08/2017
Title:	SUBSTRATE RESISTOR WITH OVERLYING GATE STRUCTURE

Patent #:	9805972	Issue Dt:	10/31/2017	Application #:	15437065	Filing Dt:	02/20/2017
Title:	SKIP VIA STRUCTURES

Patent #:	10026687	Issue Dt:	07/17/2018	Application #:	15437100	Filing Dt:	02/20/2017
Title:	METAL INTERCONNECTS FOR SUPER (SKIP) VIA INTEGRATION

Patent #:	10115810	Issue Dt:	10/30/2018	Application #:	15437168	Filing Dt:	02/20/2017
Publication #:	US20180240897	Pub Dt:	08/23/2018
Title:	HETEROJUNCTION BIPOLAR TRANSISTOR WITH A THICKENED EXTRINSIC BASE

Patent #:	9947545	Issue Dt:	04/17/2018	Application #:	15437837	Filing Dt:	02/21/2017
Publication #:	US20170243748	Pub Dt:	08/24/2017
Title:	METHODS FOR GATE FORMATION IN CIRCUIT STRUCTURES

Patent #:	10170585	Issue Dt:	01/01/2019	Application #:	15437840	Filing Dt:	02/21/2017
Publication #:	US20180240889	Pub Dt:	08/23/2018
Title:	SEMICONDUCTOR DEVICES HAVING EQUAL THICKNESS GATE SPACERS

Patent #:	10181522	Issue Dt:	01/15/2019	Application #:	15437846	Filing Dt:	02/21/2017
Publication #:	US20180240885	Pub Dt:	08/23/2018
Title:	SIMPLIFIED GATE TO SOURCE/DRAIN REGION CONNECTIONS

Patent #:	10347531	Issue Dt:	07/09/2019	Application #:	15438828	Filing Dt:	02/22/2017
Publication #:	US20180240703	Pub Dt:	08/23/2018
Title:	MIDDLE OF THE LINE (MOL) CONTACT FORMATION METHOD AND STRUCTURE

Patent #:	9929148	Issue Dt:	03/27/2018	Application #:	15439444	Filing Dt:	02/22/2017
Title:	SEMICONDUCTOR DEVICE INCLUDING BURIED CAPACITIVE STRUCTURES AND A METHOD OF FORMING THE SAME

Patent #:	9905472	Issue Dt:	02/27/2018	Application #:	15440072	Filing Dt:	02/23/2017
Title:	SILICON NITRIDE CESL REMOVAL WITHOUT GATE CAP HEIGHT LOSS AND RESULTING DEVICE

Patent #:	10191107	Issue Dt:	01/29/2019	Application #:	15440791	Filing Dt:	02/23/2017
Publication #:	US20180238958	Pub Dt:	08/23/2018
Title:	RANKING DEFECTS WITH YIELD IMPACTS

Patent #:	9806221	Issue Dt:	10/31/2017	Application #:	15441345	Filing Dt:	02/24/2017
Publication #:	US20170162743	Pub Dt:	06/08/2017
Title:	Germanium Photodetector with SOI Doping Source

Patent #:	10263013	Issue Dt:	04/16/2019	Application #:	15441711	Filing Dt:	02/24/2017
Publication #:	US20180247956	Pub Dt:	08/30/2018
Title:	METHOD OF FORMING AN INTEGRATED CIRCUIT (IC) WITH SHALLOW TRENCH ISOLATION (STI) REGIONS AND THE RESULTING IC STRUCTURE

Patent #:	10062748	Issue Dt:	08/28/2018	Application #:	15443276	Filing Dt:	02/27/2017
Publication #:	US20180248001	Pub Dt:	08/30/2018
Title:	SEGMENTED GUARD-RING AND CHIP EDGE SEALS

Patent #:	9991131	Issue Dt:	06/05/2018	Application #:	15443335	Filing Dt:	02/27/2017
Title:	DUAL MANDRELS TO ENABLE VARIABLE FIN PITCH

Patent #:	10062692	Issue Dt:	08/28/2018	Application #:	15443381	Filing Dt:	02/27/2017
Publication #:	US20180247936	Pub Dt:	08/30/2018
Title:	FIELD EFFECT TRANSISTORS WITH REDUCED PARASITIC RESISTANCES AND METHOD

Patent #:	9899259	Issue Dt:	02/20/2018	Application #:	15443523	Filing Dt:	02/27/2017
Publication #:	US20170170070	Pub Dt:	06/15/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	10229999	Issue Dt:	03/12/2019	Application #:	15445392	Filing Dt:	02/28/2017
Publication #:	US20180248046	Pub Dt:	08/30/2018
Title:	METHODS OF FORMING UPPER SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE

Patent #:	9935168	Issue Dt:	04/03/2018	Application #:	15445481	Filing Dt:	02/28/2017
Publication #:	US20170170266	Pub Dt:	06/15/2017
Title:	GATE CONTACT WITH VERTICAL ISOLATION FROM SOURCE-DRAIN

Patent #:	NONE	Issue Dt:		Application #:	15446109	Filing Dt:	03/01/2017
Publication #:	US20180254239	Pub Dt:	09/06/2018
Title:	FORMING METAL CAP LAYER OVER THROUGH-GLASS-VIAS (TGVs)

Patent #:	10109722	Issue Dt:	10/23/2018	Application #:	15447210	Filing Dt:	03/02/2017
Publication #:	US20180254331	Pub Dt:	09/06/2018
Title:	ETCH-RESISTANT SPACER FORMATION ON GATE STRUCTURE

Patent #:	9831317	Issue Dt:	11/28/2017	Application #:	15447639	Filing Dt:	03/02/2017
Title:	BURIED CONTACT STRUCTURES FOR A VERTICAL FIELD-EFFECT TRANSISTOR

Patent #:	9899257	Issue Dt:	02/20/2018	Application #:	15448873	Filing Dt:	03/03/2017
Title:	ETCH STOP LINER FOR CONTACT PUNCH THROUGH MITIGATION IN SOI SUBSTRATE

Patent #:	10249726	Issue Dt:	04/02/2019	Application #:	15451565	Filing Dt:	03/07/2017
Publication #:	US20170179246	Pub Dt:	06/22/2017
Title:	METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	10074571	Issue Dt:	09/11/2018	Application #:	15451869	Filing Dt:	03/07/2017
Publication #:	US20180261512	Pub Dt:	09/13/2018
Title:	DEVICE WITH DECREASED PITCH CONTACT TO ACTIVE REGIONS

Patent #:	10109636	Issue Dt:	10/23/2018	Application #:	15453124	Filing Dt:	03/08/2017
Publication #:	US20180261604	Pub Dt:	09/13/2018
Title:	ACTIVE CONTACT AND GATE CONTACT INTERCONNECT FOR MITIGATING ADJACENT GATE ELECTRODE SHORTAGES

Patent #:	10157832	Issue Dt:	12/18/2018	Application #:	15453133	Filing Dt:	03/08/2017
Publication #:	US20180261536	Pub Dt:	09/13/2018
Title:	INTERGRATED CIRCUIT STRUCTURE INCLUDING VIA INTERCONNECT STRUCTURE ABUTTING LATERAL ENDS OF METAL LINES AND METHODS OF FORMING SAME

Patent #:	9865681	Issue Dt:	01/09/2018	Application #:	15453170	Filing Dt:	03/08/2017
Title:	NANOWIRE TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

Patent #:	9923082	Issue Dt:	03/20/2018	Application #:	15453939	Filing Dt:	03/09/2017
Publication #:	US20170179257	Pub Dt:	06/22/2017
Title:	JUNCTION BUTTING STRUCTURE USING NONUNIFORM TRENCH SHAPE

Patent #:	10546785	Issue Dt:	01/28/2020	Application #:	15454445	Filing Dt:	03/09/2017
Publication #:	US20180261507	Pub Dt:	09/13/2018
Title:	METHOD TO RECESS COBALT FOR GATE METAL APPLICATION

Patent #:	10020386	Issue Dt:	07/10/2018	Application #:	15454511	Filing Dt:	03/09/2017
Title:	HIGH-VOLTAGE AND ANALOG BIPOLAR DEVICES

Patent #:	10177041	Issue Dt:	01/08/2019	Application #:	15455203	Filing Dt:	03/10/2017
Publication #:	US20180261514	Pub Dt:	09/13/2018
Title:	FIN-TYPE FIELD EFFECT TRANSISTORS (FINFETS) WITH REPLACEMENT METAL GATES AND METHODS

Patent #:	10242982	Issue Dt:	03/26/2019	Application #:	15455313	Filing Dt:	03/10/2017
Publication #:	US20180261595	Pub Dt:	09/13/2018
Title:	METHOD FOR FORMING A PROTECTION DEVICE HAVING AN INNER CONTACT SPACER AND THE RESULTING DEVICES

Patent #:	9793294	Issue Dt:	10/17/2017	Application #:	15455588	Filing Dt:	03/10/2017
Title:	JUNCTION FORMATION WITH REDUCED CEFF FOR 22NM FDSOI DEVICES

Patent #:	9905694	Issue Dt:	02/27/2018	Application #:	15457017	Filing Dt:	03/13/2017
Publication #:	US20180026137	Pub Dt:	01/25/2018
Title:	FIN-TYPE FIELD-EFFECT TRANSISTORS WITH STRAINED CHANNELS

Patent #:	10163633	Issue Dt:	12/25/2018	Application #:	15457200	Filing Dt:	03/13/2017
Publication #:	US20180261457	Pub Dt:	09/13/2018
Title:	NON-MANDREL CUT FORMATION

Patent #:	10103224	Issue Dt:	10/16/2018	Application #:	15457384	Filing Dt:	03/13/2017
Publication #:	US20170288015	Pub Dt:	10/05/2017
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A TRENCH CAPPING LAYER

Patent #:	9891039	Issue Dt:	02/13/2018	Application #:	15458124	Filing Dt:	03/14/2017
Title:	METHOD AND DEVICE FOR MEASURING PLATING RING ASSEMBLY DIMENSIONS

Patent #:	10002827	Issue Dt:	06/19/2018	Application #:	15458140	Filing Dt:	03/14/2017
Publication #:	US20170186687	Pub Dt:	06/29/2017
Title:	METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER AND IN ADJACENT INTERCONNECTING LAYERS OF AN IC DEVICE

Patent #:	9997695	Issue Dt:	06/12/2018	Application #:	15458316	Filing Dt:	03/14/2017
Publication #:	US20170222126	Pub Dt:	08/03/2017
Title:	METHODS TO UTILIZE PIEZOELECTRIC MATERIALS AS GATE DIELECTRIC IN HIGH FREQUENCY RBTs IN AN IC DEVICE

Patent #:	10236363	Issue Dt:	03/19/2019	Application #:	15458457	Filing Dt:	03/14/2017
Publication #:	US20180269312	Pub Dt:	09/20/2018
Title:	VERTICAL FIELD-EFFECT TRANSISTORS WITH CONTROLLED DIMENSIONS

Patent #:	10340352	Issue Dt:	07/02/2019	Application #:	15458482	Filing Dt:	03/14/2017
Publication #:	US20180269295	Pub Dt:	09/20/2018
Title:	FIELD-EFFECT TRANSISTORS WITH A T-SHAPED GATE ELECTRODE

Patent #:	10770440	Issue Dt:	09/08/2020	Application #:	15459336	Filing Dt:	03/15/2017
Publication #:	US20180269191	Pub Dt:	09/20/2018
Title:	MICRO-LED DISPLAY ASSEMBLY

Patent #:	9871096	Issue Dt:	01/16/2018	Application #:	15459450	Filing Dt:	03/15/2017
Publication #:	US20170250243	Pub Dt:	08/31/2017
Title:	SERIAL CAPACITOR DEVICE WITH MIDDLE ELECTRODE CONTACT

Patent #:	10079597	Issue Dt:	09/18/2018	Application #:	15459867	Filing Dt:	03/15/2017
Publication #:	US20180269868	Pub Dt:	09/20/2018
Title:	CIRCUIT TUNING SCHEME FOR FDSOI

Patent #:	NONE	Issue Dt:		Application #:	15460976	Filing Dt:	03/16/2017
Publication #:	US20170186688	Pub Dt:	06/29/2017
Title:	METHODS AND DEVICES FOR METAL FILLING PROCESSES

Patent #:	10068835	Issue Dt:	09/04/2018	Application #:	15461538	Filing Dt:	03/17/2017
Publication #:	US20170186669	Pub Dt:	06/29/2017
Title:	PROCESS FLOW FOR A COMBINED CA AND TSV OXIDE DEPOSITION

Patent #:	10283608	Issue Dt:	05/07/2019	Application #:	15461634	Filing Dt:	03/17/2017
Publication #:	US20180269297	Pub Dt:	09/20/2018
Title:	LOW RESISTANCE CONTACTS TO SOURCE OR DRAIN REGION OF TRANSISTOR

Patent #:	9985135	Issue Dt:	05/29/2018	Application #:	15462644	Filing Dt:	03/17/2017
Publication #:	US20170194499	Pub Dt:	07/06/2017
Title:	REPLACEMENT LOW-K SPACER

Patent #:	NONE	Issue Dt:		Application #:	15463011	Filing Dt:	03/20/2017
Publication #:	US20180269273	Pub Dt:	09/20/2018
Title:	INTERCONNECT STRUCTURES FOR A METAL-INSULATOR-METAL CAPACITOR

Patent #:	10033383	Issue Dt:	07/24/2018	Application #:	15463316	Filing Dt:	03/20/2017
Title:	PROGRAMMABLE LOGIC ELEMENTS AND METHODS OF OPERATING THE SAME

Patent #:	9966128	Issue Dt:	05/08/2018	Application #:	15463394	Filing Dt:	03/20/2017
Title:	STORAGE STRUCTURE WITH NON-VOLATILE STORAGE CAPABILITY AND A METHOD OF OPERATING THE SAME

100

Patent #:	10147783	Issue Dt:	12/04/2018	Application #:	15463465	Filing Dt:	03/20/2017
Publication #:	US20180269275	Pub Dt:	09/20/2018
Title:	ON-CHIP CAPACITORS WITH FLOATING ISLANDS

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

440 STONE BREAK ROAD EXTENSION

MALTA, NEW YORK 12020

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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