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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 168 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
10062647
Issue Dt:
08/28/2018
Application #:
15646325
Filing Dt:
07/11/2017
Publication #:
US20170309573
Pub Dt:
10/26/2017
Title:
INTERCONNECT STRUCTURE HAVING TUNGSTEN CONTACT COPPER WIRING
2
Patent #:
10121665
Issue Dt:
11/06/2018
Application #:
15646570
Filing Dt:
07/11/2017
Publication #:
US20170316944
Pub Dt:
11/02/2017
Title:
SHORT-CHANNEL NFET DEVICE
3
Patent #:
10485111
Issue Dt:
11/19/2019
Application #:
15647400
Filing Dt:
07/12/2017
Publication #:
US20190021176
Pub Dt:
01/17/2019
Title:
VIA AND SKIP VIA STRUCTURES
4
Patent #:
10319827
Issue Dt:
06/11/2019
Application #:
15647403
Filing Dt:
07/12/2017
Publication #:
US20190019876
Pub Dt:
01/17/2019
Title:
HIGH VOLTAGE TRANSISTOR USING BURIED INSULATING LAYER AS GATE DIELECTRIC
5
Patent #:
10026655
Issue Dt:
07/17/2018
Application #:
15647453
Filing Dt:
07/12/2017
Publication #:
US20170316985
Pub Dt:
11/02/2017
Title:
DUAL LINER CMOS INTEGRATION METHODS FOR FINFET DEVICES
6
Patent #:
10340146
Issue Dt:
07/02/2019
Application #:
15647495
Filing Dt:
07/12/2017
Publication #:
US20190019682
Pub Dt:
01/17/2019
Title:
RELIABILITY CAPS FOR HIGH-K DIELECTRIC ANNEALS
7
Patent #:
10181421
Issue Dt:
01/15/2019
Application #:
15647977
Filing Dt:
07/12/2017
Publication #:
US20190019726
Pub Dt:
01/17/2019
Title:
LINER RECESS FOR FULLY ALIGNED VIA
8
Patent #:
10090227
Issue Dt:
10/02/2018
Application #:
15648602
Filing Dt:
07/13/2017
Title:
BACK BIASING IN SOI FET TECHNOLOGY
9
Patent #:
10157996
Issue Dt:
12/18/2018
Application #:
15648889
Filing Dt:
07/13/2017
Publication #:
US20170345914
Pub Dt:
11/30/2017
Title:
METHODS FOR FORMING INTEGRATED CIRCUITS THAT INCLUDE A DUMMY GATE STRUCTURE
10
Patent #:
10297672
Issue Dt:
05/21/2019
Application #:
15649227
Filing Dt:
07/13/2017
Publication #:
US20190019880
Pub Dt:
01/17/2019
Title:
TRIPLE GATE TECHNOLOGY FOR 14 NANOMETER AND ONWARDS
11
Patent #:
NONE
Issue Dt:
Application #:
15649294
Filing Dt:
07/13/2017
Publication #:
US20190019862
Pub Dt:
01/17/2019
Title:
COALESCED FIN TO REDUCE FIN BENDING
12
Patent #:
10193011
Issue Dt:
01/29/2019
Application #:
15650427
Filing Dt:
07/14/2017
Publication #:
US20190019915
Pub Dt:
01/17/2019
Title:
METHOD OF MANUFACTURING A 3 COLOR LED INTEGRATED SI CMOS DRIVER WAFER USING DIE TO WAFER BONDING APPROACH
13
Patent #:
9991352
Issue Dt:
06/05/2018
Application #:
15651282
Filing Dt:
07/17/2017
Title:
METHODS OF FORMING A NANO-SHEET TRANSISTOR DEVICE WITH A THICKER GATE STACK AND THE RESULTING DEVICE
14
Patent #:
9984936
Issue Dt:
05/29/2018
Application #:
15651621
Filing Dt:
07/17/2017
Title:
METHODS OF FORMING AN ISOLATED NANO-SHEET TRANSISTOR DEVICE AND THE RESULTING DEVICE
15
Patent #:
10199220
Issue Dt:
02/05/2019
Application #:
15652413
Filing Dt:
07/18/2017
Publication #:
US20180190483
Pub Dt:
07/05/2018
Title:
SEMICONDUCTOR STRUCTURE HAVING INSULATOR PILLARS AND SEMICONDUCTOR MATERIAL ON SUBSTRATE
16
Patent #:
10217660
Issue Dt:
02/26/2019
Application #:
15652585
Filing Dt:
07/18/2017
Publication #:
US20190027400
Pub Dt:
01/24/2019
Title:
TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A LATE MANUFACTURING STAGE
17
Patent #:
10147659
Issue Dt:
12/04/2018
Application #:
15652661
Filing Dt:
07/18/2017
Title:
METHOD AND STRUCTURE FOR PROCESS LIMITING YIELD TESTING
18
Patent #:
10249710
Issue Dt:
04/02/2019
Application #:
15652873
Filing Dt:
07/18/2017
Publication #:
US20170317169
Pub Dt:
11/02/2017
Title:
METHODS, APPARATUS, AND SYSTEM FOR IMPROVED NANOWIRE/NANOSHEET SPACERS
19
Patent #:
10103238
Issue Dt:
10/16/2018
Application #:
15652890
Filing Dt:
07/18/2017
Title:
NANOSHEET FIELD-EFFECT TRANSISTOR WITH FULL DIELECTRIC ISOLATION
20
Patent #:
10115633
Issue Dt:
10/30/2018
Application #:
15653127
Filing Dt:
07/18/2017
Publication #:
US20170352591
Pub Dt:
12/07/2017
Title:
METHOD FOR PRODUCING SELF-ALIGNED LINE END VIAS AND RELATED DEVICE
21
Patent #:
10530589
Issue Dt:
01/07/2020
Application #:
15653497
Filing Dt:
07/18/2017
Publication #:
US20170324569
Pub Dt:
11/09/2017
Title:
Method, Apparatus and System for Security Application for Integrated Circuit Devices
22
Patent #:
NONE
Issue Dt:
Application #:
15653594
Filing Dt:
07/19/2017
Publication #:
US20190027370
Pub Dt:
01/24/2019
Title:
SHAPED CAVITY FOR EPITAXIAL SEMICONDUCTOR GROWTH
23
Patent #:
10535674
Issue Dt:
01/14/2020
Application #:
15653661
Filing Dt:
07/19/2017
Publication #:
US20170317097
Pub Dt:
11/02/2017
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE
24
Patent #:
10211315
Issue Dt:
02/19/2019
Application #:
15654165
Filing Dt:
07/19/2017
Publication #:
US20190027586
Pub Dt:
01/24/2019
Title:
Vertical Field-Effect Transistor having a Dielectric Spacer between a Gate Electrode Edge and a Self-Aligned Source/Drain Contact
25
Patent #:
10083971
Issue Dt:
09/25/2018
Application #:
15654190
Filing Dt:
07/19/2017
Title:
Vertical SRAM Structure with Cross-Coupling Contacts Penetrating through Common Gates to Bottom S/D Metal Contacts
26
Patent #:
10741668
Issue Dt:
08/11/2020
Application #:
15654234
Filing Dt:
07/19/2017
Publication #:
US20190027578
Pub Dt:
01/24/2019
Title:
SHORT CHANNEL AND LONG CHANNEL DEVICES
27
Patent #:
10008491
Issue Dt:
06/26/2018
Application #:
15655274
Filing Dt:
07/20/2017
Title:
LOW CAPACITANCE ELECTROSTATIC DISCHARGE (ESD) DEVICES
28
Patent #:
10186599
Issue Dt:
01/22/2019
Application #:
15655547
Filing Dt:
07/20/2017
Publication #:
US20190027580
Pub Dt:
01/24/2019
Title:
Forming Self-Aligned Contact with Spacer First
29
Patent #:
10403734
Issue Dt:
09/03/2019
Application #:
15656542
Filing Dt:
07/21/2017
Publication #:
US20190027575
Pub Dt:
01/24/2019
Title:
SEMICONDUCTOR DEVICE WITH REDUCED GATE HEIGHT BUDGET
30
Patent #:
NONE
Issue Dt:
Application #:
15656574
Filing Dt:
07/21/2017
Publication #:
US20190027556
Pub Dt:
01/24/2019
Title:
SHALLOW TRENCH ISOLATION (STI) GAP FILL
31
Patent #:
10643912
Issue Dt:
05/05/2020
Application #:
15657312
Filing Dt:
07/24/2017
Publication #:
US20190027413
Pub Dt:
01/24/2019
Title:
CHIP PACKAGE INTERACTION (CPI) BACK-END-OF-LINE (BEOL) MONITORING STRUCTURE AND METHOD
32
Patent #:
10256152
Issue Dt:
04/09/2019
Application #:
15657373
Filing Dt:
07/24/2017
Publication #:
US20190027601
Pub Dt:
01/24/2019
Title:
FINFET DEVICE COMPRISING A PIEZOELECTRIC LINER FOR GENERATING A SURFACE CHARGE AND METHODS OF MAKING SUCH A DEVICE
33
Patent #:
9991363
Issue Dt:
06/05/2018
Application #:
15657594
Filing Dt:
07/24/2017
Title:
CONTACT ETCH STOP LAYER WITH SACRIFICIAL POLYSILICON LAYER
34
Patent #:
9947804
Issue Dt:
04/17/2018
Application #:
15657659
Filing Dt:
07/24/2017
Title:
METHODS OF FORMING NANOSHEET TRANSISTOR WITH DIELECTRIC ISOLATION OF SOURCE-DRAIN REGIONS AND RELATED STRUCTURE
35
Patent #:
10103083
Issue Dt:
10/16/2018
Application #:
15658438
Filing Dt:
07/25/2017
Publication #:
US20180053707
Pub Dt:
02/22/2018
Title:
INTEGRATED CIRCUITS WITH PELTIER COOLING PROVIDED BY BACK-END WIRING
36
Patent #:
10504790
Issue Dt:
12/10/2019
Application #:
15658524
Filing Dt:
07/25/2017
Publication #:
US20190035692
Pub Dt:
01/31/2019
Title:
METHODS OF FORMING CONDUCTIVE SPACERS FOR GATE CONTACTS AND THE RESULTING DEVICE
37
Patent #:
10157774
Issue Dt:
12/18/2018
Application #:
15658570
Filing Dt:
07/25/2017
Title:
CONTACT SCHEME FOR LANDING ON DIFFERENT CONTACT AREA LEVELS
38
Patent #:
10090402
Issue Dt:
10/02/2018
Application #:
15658835
Filing Dt:
07/25/2017
Title:
METHODS OF FORMING FIELD EFFECT TRANSISTORS (FETS) WITH GATE CUT ISOLATION REGIONS BETWEEN REPLACEMENT METAL GATES
39
Patent #:
NONE
Issue Dt:
Application #:
15658943
Filing Dt:
07/25/2017
Publication #:
US20190035888
Pub Dt:
01/31/2019
Title:
NANOSHEET FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE/DRAIN ISOLATION
40
Patent #:
10109620
Issue Dt:
10/23/2018
Application #:
15660577
Filing Dt:
07/26/2017
Title:
METHOD FOR REDUCING SWITCH ON STATE RESISTANCE OF SWITCHED-CAPACITOR CHARGE PUMP USING SELF-GENERATED SWITCHING BACK-GATE BIAS VOLTAGE
41
Patent #:
10262942
Issue Dt:
04/16/2019
Application #:
15661029
Filing Dt:
07/27/2017
Publication #:
US20190035739
Pub Dt:
01/31/2019
Title:
METHOD OF FORMING COBALT CONTACT MODULE AND COBALT CONTACT MODULE FORMED THEREBY
42
Patent #:
10134739
Issue Dt:
11/20/2018
Application #:
15661058
Filing Dt:
07/27/2017
Title:
MEMORY ARRAY WITH BURIED BITLINES BELOW VERTICAL FIELD EFFECT TRANSISTORS OF MEMORY CELLS AND A METHOD OF FORMING THE MEMORY ARRAY
43
Patent #:
9960226
Issue Dt:
05/01/2018
Application #:
15661504
Filing Dt:
07/27/2017
Publication #:
US20170323937
Pub Dt:
11/09/2017
Title:
HIGH DENSITY CAPACITOR STRUCTURE AND METHOD
44
Patent #:
10068859
Issue Dt:
09/04/2018
Application #:
15662334
Filing Dt:
07/28/2017
Title:
CRACK TRAPPING IN SEMICONDUCTOR DEVICE STRUCTURES
45
Patent #:
10461196
Issue Dt:
10/29/2019
Application #:
15662526
Filing Dt:
07/28/2017
Publication #:
US20190035938
Pub Dt:
01/31/2019
Title:
CONTROL OF LENGTH IN GATE REGION DURING PROCESSING OF VFET STRUCTURES
46
Patent #:
10418380
Issue Dt:
09/17/2019
Application #:
15664061
Filing Dt:
07/31/2017
Publication #:
US20190035815
Pub Dt:
01/31/2019
Title:
HIGH-VOLTAGE TRANSISTOR DEVICE WITH THICK GATE INSULATION LAYERS
47
Patent #:
10367084
Issue Dt:
07/30/2019
Application #:
15664418
Filing Dt:
07/31/2017
Publication #:
US20190035919
Pub Dt:
01/31/2019
Title:
CASCODE HETEROJUNCTION BIPOLAR TRANSISTORS
48
Patent #:
9984919
Issue Dt:
05/29/2018
Application #:
15664584
Filing Dt:
07/31/2017
Title:
INVERTED DAMASCENE INTERCONNECT STRUCTURES
49
Patent #:
10192746
Issue Dt:
01/29/2019
Application #:
15665183
Filing Dt:
07/31/2017
Publication #:
US20190035633
Pub Dt:
01/31/2019
Title:
STI INNER SPACER TO MITIGATE SDB LOADING
50
Patent #:
10083967
Issue Dt:
09/25/2018
Application #:
15665979
Filing Dt:
08/01/2017
Publication #:
US20170358581
Pub Dt:
12/14/2017
Title:
NON-VOLATILE MEMORY DEVICE EMPLOYING A DEEP TRENCH CAPACITOR
51
Patent #:
10224251
Issue Dt:
03/05/2019
Application #:
15667017
Filing Dt:
08/02/2017
Publication #:
US20190043764
Pub Dt:
02/07/2019
Title:
SEMICONDUCTOR DEVICES AND MANUFACTURING TECHNIQUES FOR REDUCED ASPECT RATIO OF NEIGHBORING GATE ELECTRODE LINES
52
Patent #:
10319642
Issue Dt:
06/11/2019
Application #:
15667305
Filing Dt:
08/02/2017
Publication #:
US20180012812
Pub Dt:
01/11/2018
Title:
HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRUCTURES FOR MIXED SIGNAL CIRCUITS FABRICATION
53
Patent #:
10204984
Issue Dt:
02/12/2019
Application #:
15667376
Filing Dt:
08/02/2017
Publication #:
US20190043944
Pub Dt:
02/07/2019
Title:
METHODS, APPARATUS AND SYSTEM FOR FORMING INCREASED SURFACE REGIONS WITHIN EPI STRUCTURES FOR IMPROVED TRENCH SILICIDE
54
Patent #:
NONE
Issue Dt:
Application #:
15667755
Filing Dt:
08/03/2017
Publication #:
US20190043963
Pub Dt:
02/07/2019
Title:
TRANSISTOR ELEMENT WITH GATE ELECTRODE OF REDUCED HEIGHT AND RAISED DRAIN AND SOURCE REGIONS AND METHOD OF FABRICATING THE SAME
55
Patent #:
10043893
Issue Dt:
08/07/2018
Application #:
15668012
Filing Dt:
08/03/2017
Title:
POST GATE SILICON GERMANIUM CHANNEL CONDENSATION AND METHOD FOR PRODUCING THE SAME
56
Patent #:
10297504
Issue Dt:
05/21/2019
Application #:
15670366
Filing Dt:
08/07/2017
Publication #:
US20190043758
Pub Dt:
02/07/2019
Title:
METHODS OF FORMING A GATE STRUCTURE-TO-SOURCE/DRAIN CONDUCTIVE CONTACT AND THE RESULTING DEVICES
57
Patent #:
10199259
Issue Dt:
02/05/2019
Application #:
15670465
Filing Dt:
08/07/2017
Publication #:
US20190043752
Pub Dt:
02/07/2019
Title:
TECHNIQUE FOR DEFINING ACTIVE REGIONS OF SEMICONDUCTOR DEVICES WITH REDUCED LITHOGRAPHY EFFORT
58
Patent #:
10163955
Issue Dt:
12/25/2018
Application #:
15671223
Filing Dt:
08/08/2017
Publication #:
US20170358619
Pub Dt:
12/14/2017
Title:
PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS
59
Patent #:
10497803
Issue Dt:
12/03/2019
Application #:
15671590
Filing Dt:
08/08/2017
Publication #:
US20190051747
Pub Dt:
02/14/2019
Title:
FULLY DEPLETED SILICON ON INSULATOR (FDSOI) LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) FOR HIGH FREQUENCY APPLICATIONS
60
Patent #:
10230000
Issue Dt:
03/12/2019
Application #:
15671605
Filing Dt:
08/08/2017
Publication #:
US20190051757
Pub Dt:
02/14/2019
Title:
VERTICAL-TRANSPORT TRANSISTORS WITH SELF-ALIGNED CONTACTS
61
Patent #:
10128334
Issue Dt:
11/13/2018
Application #:
15672336
Filing Dt:
08/09/2017
Title:
FIELD EFFECT TRANSISTOR HAVING AN AIR-GAP GATE SIDEWALL SPACER AND METHOD
62
Patent #:
10176995
Issue Dt:
01/08/2019
Application #:
15673232
Filing Dt:
08/09/2017
Title:
METHODS, APPARATUS AND SYSTEM FOR GATE CUT PROCESS USING A STRESS MATERIAL IN A FINFET DEVICE
63
Patent #:
NONE
Issue Dt:
Application #:
15673519
Filing Dt:
08/10/2017
Publication #:
US20190051565
Pub Dt:
02/14/2019
Title:
CMOS DEVICES AND MANUFACTURING METHOD THEREOF
64
Patent #:
10319731
Issue Dt:
06/11/2019
Application #:
15673548
Filing Dt:
08/10/2017
Publication #:
US20190051659
Pub Dt:
02/14/2019
Title:
INTEGRATED CIRCUIT STRUCTURE HAVING VFET AND EMBEDDED MEMORY STRUCTURE AND METHOD OF FORMING SAME
65
Patent #:
NONE
Issue Dt:
Application #:
15674763
Filing Dt:
08/11/2017
Publication #:
US20180012760
Pub Dt:
01/11/2018
Title:
DEVICES AND METHODS OF FORMING SADP ON SRAM AND SAQP ON LOGIC
66
Patent #:
NONE
Issue Dt:
Application #:
15674859
Filing Dt:
08/11/2017
Publication #:
US20170365721
Pub Dt:
12/21/2017
Title:
DIODES AND FABRICATION METHODS THEREOF
67
Patent #:
10374090
Issue Dt:
08/06/2019
Application #:
15675970
Filing Dt:
08/14/2017
Publication #:
US20170345934
Pub Dt:
11/30/2017
Title:
REPLACEMENT BODY FINFET FOR IMPROVED JUNCTION PROFILE WITH GATE SELF-ALIGNED JUNCTIONS
68
Patent #:
11309220
Issue Dt:
04/19/2022
Application #:
15676005
Filing Dt:
08/14/2017
Publication #:
US20190051563
Pub Dt:
02/14/2019
Title:
METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF A VERTICAL TRANSISTOR
69
Patent #:
10068987
Issue Dt:
09/04/2018
Application #:
15676219
Filing Dt:
08/14/2017
Title:
VERTICAL FIELD EFFECT TRANSISTOR (VFET) HAVING A SELF-ALIGNED GATE/GATE EXTENSION STRUCTURE AND METHOD
70
Patent #:
10050125
Issue Dt:
08/14/2018
Application #:
15676300
Filing Dt:
08/14/2017
Title:
VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH AN ETCHED-THROUGH SOURCE/DRAIN CAVITY
71
Patent #:
10163933
Issue Dt:
12/25/2018
Application #:
15676529
Filing Dt:
08/14/2017
Title:
FERRO-FET DEVICE WITH BURIED BUFFER/FERROELECTRIC LAYER STACK
72
Patent #:
10134580
Issue Dt:
11/20/2018
Application #:
15677693
Filing Dt:
08/15/2017
Title:
METALLIZATION LEVELS AND METHODS OF MAKING THEREOF
73
Patent #:
10714616
Issue Dt:
07/14/2020
Application #:
15678206
Filing Dt:
08/16/2017
Publication #:
US20180012988
Pub Dt:
01/11/2018
Title:
FINFET HAVING A GATE STRUCTURE IN A TRENCH FEATURE IN A BENT FIN
74
Patent #:
10388562
Issue Dt:
08/20/2019
Application #:
15678229
Filing Dt:
08/16/2017
Publication #:
US20190057899
Pub Dt:
02/21/2019
Title:
COMPOSITE CONTACT ETCH STOP LAYER
75
Patent #:
NONE
Issue Dt:
Application #:
15678385
Filing Dt:
08/16/2017
Publication #:
US20190058082
Pub Dt:
02/21/2019
Title:
UNIFORM SEMICONDUCTOR NANOWIRE AND NANOSHEET LIGHT EMITTING DIODES
76
Patent #:
10163864
Issue Dt:
12/25/2018
Application #:
15678642
Filing Dt:
08/16/2017
Title:
VERTICALLY STACKED WAFERS AND METHODS OF FORMING SAME
77
Patent #:
9960077
Issue Dt:
05/01/2018
Application #:
15679848
Filing Dt:
08/17/2017
Title:
ULTRA-SCALE GATE CUT PILLAR WITH OVERLAY IMMUNITY AND METHOD FOR PRODUCING THE SAME
78
Patent #:
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Title:
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Pub Dt:
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Title:
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Title:
OVERLAY MARK STRUCTURES
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
GATE CUT METHOD FOR REPLACEMENT METAL GATE
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Title:
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Title:
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Title:
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Title:
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Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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