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Patent #:
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|
Issue Dt:
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05/21/2019
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Application #:
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15689711
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Filing Dt:
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08/29/2017
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Publication #:
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|
Pub Dt:
|
04/05/2018
| | | | |
Title:
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COMPOSITE ISOLATION STRUCTURES FOR A FIN-TYPE FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
|
12/03/2019
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Application #:
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15689934
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Filing Dt:
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08/29/2017
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Publication #:
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|
Pub Dt:
|
02/28/2019
| | | | |
Title:
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SRAM STRUCTURE WITH ALTERNATE GATE PITCHES
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Patent #:
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Issue Dt:
|
01/28/2020
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Application #:
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15690398
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Filing Dt:
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08/30/2017
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Publication #:
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|
Pub Dt:
|
02/28/2019
| | | | |
Title:
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SEAL RING STRUCTURE OF INTEGRATED CIRCUIT AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
|
02/11/2020
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Application #:
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15690828
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Filing Dt:
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08/30/2017
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Publication #:
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Pub Dt:
|
12/21/2017
| | | | |
Title:
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BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
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Patent #:
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Issue Dt:
|
12/17/2019
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Application #:
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15692136
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Filing Dt:
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08/31/2017
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Publication #:
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Pub Dt:
|
02/28/2019
| | | | |
Title:
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III-V LASERS WITH ON-CHIP INTEGRATION
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Patent #:
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Issue Dt:
|
07/31/2018
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Application #:
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15692666
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Filing Dt:
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08/31/2017
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Publication #:
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Pub Dt:
|
01/04/2018
| | | | |
Title:
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DEVICE LAYER TRANSFER WITH A PRESERVED HANDLE WAFER SECTION
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Patent #:
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Issue Dt:
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10/23/2018
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Application #:
|
15692816
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Filing Dt:
|
08/31/2017
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Title:
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THERMAL OXIDE EQUIVALENT LOW TEMPERATURE ALD OXIDE FOR DUAL PURPOSE GATE OXIDE AND METHOD FOR PRODUCING THE SAME
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Patent #:
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Issue Dt:
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09/10/2019
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Application #:
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15693537
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Filing Dt:
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09/01/2017
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Publication #:
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Pub Dt:
|
03/07/2019
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH AIRGAP SPACER FOR TRANSISTOR AND RELATED METHOD
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Patent #:
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Issue Dt:
|
03/26/2019
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Application #:
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15693938
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Filing Dt:
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09/01/2017
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Publication #:
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Pub Dt:
|
04/12/2018
| | | | |
Title:
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VERTICAL VACUUM CHANNEL TRANSISTOR
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|
Patent #:
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Issue Dt:
|
10/01/2019
|
Application #:
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15693952
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Filing Dt:
|
09/01/2017
|
Publication #:
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|
Pub Dt:
|
04/12/2018
| | | | |
Title:
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VERTICAL VACUUM CHANNEL TRANSISTOR
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Patent #:
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Issue Dt:
|
10/23/2018
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Application #:
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15694109
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Filing Dt:
|
09/01/2017
|
Publication #:
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|
Pub Dt:
|
09/06/2018
| | | | |
Title:
|
BURIED CONTACT STRUCTURES FOR A VERTICAL FIELD-EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
|
05/14/2019
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Application #:
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15695229
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Filing Dt:
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09/05/2017
|
Publication #:
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|
Pub Dt:
|
03/07/2019
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURE, GATE ALL-AROUND INTEGRATED CIRCUIT STRUCTURE AND METHODS OF FORMING SAME
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Patent #:
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|
Issue Dt:
|
05/12/2020
|
Application #:
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15695391
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Filing Dt:
|
09/05/2017
|
Publication #:
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|
Pub Dt:
|
03/07/2019
| | | | |
Title:
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TECHNIQUE FOR DECOUPLING PLASMA ANTENNAE FROM ACTUAL CIRCUITRY
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Patent #:
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Issue Dt:
|
01/14/2020
|
Application #:
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15695457
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Filing Dt:
|
09/05/2017
|
Publication #:
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Pub Dt:
|
12/21/2017
| | | | |
Title:
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LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY
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|
Patent #:
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|
Issue Dt:
|
08/27/2019
|
Application #:
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15696505
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Filing Dt:
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09/06/2017
|
Publication #:
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|
Pub Dt:
|
03/07/2019
| | | | |
Title:
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SEMICONDUCTOR FABRICATION DESIGN RULE LOOPHOLE CHECKING FOR DESIGN FOR MANUFACTURABILITY OPTIMIZATION
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Patent #:
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|
Issue Dt:
|
09/04/2018
|
Application #:
|
15697661
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Filing Dt:
|
09/07/2017
|
Title:
|
MULTIPLE FIN HEIGHTS WITH DIELECTRIC ISOLATION
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|
Patent #:
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|
Issue Dt:
|
10/08/2019
|
Application #:
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15698027
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Filing Dt:
|
09/07/2017
|
Publication #:
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|
Pub Dt:
|
03/07/2019
| | | | |
Title:
|
ARC-RESISTANT CRACKSTOP
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
15698775
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Filing Dt:
|
09/08/2017
|
Publication #:
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|
Pub Dt:
|
03/14/2019
| | | | |
Title:
|
DUAL DEVELOPING METHODS FOR LITHOGRAPHY PATTERNING
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|
Patent #:
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|
Issue Dt:
|
08/14/2018
|
Application #:
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15698793
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Filing Dt:
|
09/08/2017
|
Publication #:
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|
Pub Dt:
|
12/28/2017
| | | | |
Title:
|
CONTACT LINE HAVING INSULATING SPACER THEREIN AND METHOD OF FORMING SAME
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|
Patent #:
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|
Issue Dt:
|
06/09/2020
|
Application #:
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15699094
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Filing Dt:
|
09/08/2017
|
Publication #:
|
|
Pub Dt:
|
03/14/2019
| | | | |
Title:
|
STRUCTURE, METHOD AND SYSTEM FOR MEASURING RIE LAG DEPTH
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|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15699322
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Filing Dt:
|
09/08/2017
|
Publication #:
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|
Pub Dt:
|
12/28/2017
| | | | |
Title:
|
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15701480
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Filing Dt:
|
09/12/2017
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
Title:
|
METHOD OF FORMING AN INTEGRATED CIRCUIT WITH DUAL DAMASCENE INTERCONNECTS HAVING HYBRID METALLIZATION AND THE RESULTING STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
05/05/2020
|
Application #:
|
15701672
|
Filing Dt:
|
09/12/2017
|
Publication #:
|
|
Pub Dt:
|
03/14/2019
| | | | |
Title:
|
HYBRID CASCODE CONSTRUCTIONS WITH MULTIPLE TRANSISTOR TYPES
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
15701678
|
Filing Dt:
|
09/12/2017
|
Publication #:
|
|
Pub Dt:
|
03/14/2019
| | | | |
Title:
|
CONTACT TO SOURCE/DRAIN REGIONS AND METHOD OF FORMING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
05/14/2019
|
Application #:
|
15702243
|
Filing Dt:
|
09/12/2017
|
Publication #:
|
|
Pub Dt:
|
03/14/2019
| | | | |
Title:
|
VNW SRAM WITH TRINITY CROSS-COUPLE PD/PU CONTACT AND METHOD FOR PRODUCING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
15702278
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Filing Dt:
|
09/12/2017
|
Publication #:
|
|
Pub Dt:
|
03/14/2019
| | | | |
Title:
|
METHODS, APPARATUS AND SYSTEM FOR FORMING SIGMA SHAPED SOURCE/DRAIN LATTICE
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|
Patent #:
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|
Issue Dt:
|
10/23/2018
|
Application #:
|
15702316
|
Filing Dt:
|
09/12/2017
|
Title:
|
CRACKSTOP STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
11/10/2020
|
Application #:
|
15703220
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Filing Dt:
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09/13/2017
|
Publication #:
|
|
Pub Dt:
|
03/14/2019
| | | | |
Title:
|
SWITCH WITH LOCAL SILICON ON INSULATOR (SOI) AND DEEP TRENCH ISOLATION
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
15703221
|
Filing Dt:
|
09/13/2017
|
Publication #:
|
|
Pub Dt:
|
03/14/2019
| | | | |
Title:
|
NANOSHEET TRANSISTOR WITH IMPROVED INNER SPACER
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|
Patent #:
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|
Issue Dt:
|
07/02/2019
|
Application #:
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15703484
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Filing Dt:
|
09/13/2017
|
Publication #:
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|
Pub Dt:
|
01/04/2018
| | | | |
Title:
|
TUNNELING FIELD EFFECT TRANSISTOR
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
15703601
|
Filing Dt:
|
09/13/2017
|
Publication #:
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|
Pub Dt:
|
01/04/2018
| | | | |
Title:
|
METHODS FOR FORMING MASK LAYERS USING A FLOWABLE CARBON-CONTAINING SILICON DIOXIDE MATERIAL
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|
Patent #:
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|
Issue Dt:
|
07/30/2019
|
Application #:
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15704598
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Filing Dt:
|
09/14/2017
|
Publication #:
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|
Pub Dt:
|
01/11/2018
| | | | |
Title:
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STABLE AND RELIABLE FINFET SRAM WITH IMPROVED BETA RATIO
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|
Patent #:
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|
Issue Dt:
|
05/14/2019
|
Application #:
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15704982
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Filing Dt:
|
09/14/2017
|
Publication #:
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|
Pub Dt:
|
03/14/2019
| | | | |
Title:
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NANOWIRE FORMATION METHODS
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
15705429
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Filing Dt:
|
09/15/2017
|
Publication #:
|
|
Pub Dt:
|
03/21/2019
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURE INCLUDING DEEP N-WELL SELF-ALIGNED WITH STI AND METHOD OF FORMING SAME
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|
Patent #:
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|
Issue Dt:
|
06/04/2019
|
Application #:
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15705888
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Filing Dt:
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09/15/2017
|
Publication #:
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|
Pub Dt:
|
03/21/2019
| | | | |
Title:
|
METHOD OF FORMING VERTICAL FINFET DEVICE HAVING SELF-ALIGNED CONTACTS
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|
Patent #:
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|
Issue Dt:
|
05/07/2019
|
Application #:
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15705956
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Filing Dt:
|
09/15/2017
|
Publication #:
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|
Pub Dt:
|
03/21/2019
| | | | |
Title:
|
INTERCONNECTS FORMED BY A METAL REPLACEMENT PROCESS
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|
Patent #:
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|
Issue Dt:
|
07/02/2019
|
Application #:
|
15706048
|
Filing Dt:
|
09/15/2017
|
Publication #:
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|
Pub Dt:
|
03/21/2019
| | | | |
Title:
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STACKED SOI SEMICONDUCTOR DEVICES WITH BACK BIAS MECHANISM
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|
Patent #:
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|
Issue Dt:
|
08/21/2018
|
Application #:
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15708281
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Filing Dt:
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09/19/2017
|
Publication #:
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|
Pub Dt:
|
01/18/2018
| | | | |
Title:
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ELECTROPLATING SYSTEM AND METHOD OF USING ELECTROPLATING SYSTEM FOR CONTROLLING CONCENTRATION OF ORGANIC ADDITIVES IN ELECTROPLATING SOLUTION
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Patent #:
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|
Issue Dt:
|
05/26/2020
|
Application #:
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15708911
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Filing Dt:
|
09/19/2017
|
Publication #:
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|
Pub Dt:
|
01/04/2018
| | | | |
Title:
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METHOD OF CONCURRENTLY FORMING SOURCE/DRAIN AND GATE CONTACTS AND RELATED DEVICE
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|
Patent #:
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|
Issue Dt:
|
05/07/2019
|
Application #:
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15709500
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Filing Dt:
|
09/20/2017
|
Publication #:
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|
Pub Dt:
|
03/21/2019
| | | | |
Title:
|
METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED GATES AND GATE EXTENSIONS AND THE RESULTING STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
08/27/2019
|
Application #:
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15709671
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Filing Dt:
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09/20/2017
|
Publication #:
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|
Pub Dt:
|
03/21/2019
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH RECESSED SOURCE/DRAIN CONTACTS AND A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION
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|
Patent #:
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Issue Dt:
|
01/01/2019
|
Application #:
|
15709704
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Filing Dt:
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09/20/2017
|
Title:
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MEMORY CELL WITH RECESSED SOURCE/DRAIN CONTACTS TO REDUCE CAPACITANCE
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|
Patent #:
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|
Issue Dt:
|
07/30/2019
|
Application #:
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15709956
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Filing Dt:
|
09/20/2017
|
Publication #:
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Pub Dt:
|
03/21/2019
| | | | |
Title:
|
FULLY ALIGNED VIA IN GROUND RULE REGION
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
15711410
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Filing Dt:
|
09/21/2017
|
Publication #:
|
|
Pub Dt:
|
03/21/2019
| | | | |
Title:
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METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL IN SOURCE/DRAIN REGIONS OF A TRANSISTOR DEVICE FORMED ON AN SOI SUBSTRATE
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|
|
Patent #:
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|
Issue Dt:
|
11/06/2018
|
Application #:
|
15711415
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Filing Dt:
|
09/21/2017
|
Title:
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LDMOS FINFET STRUCTURES WITH MULTIPLE GATE STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
12/31/2019
|
Application #:
|
15711674
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Filing Dt:
|
09/21/2017
|
Publication #:
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|
Pub Dt:
|
01/11/2018
| | | | |
Title:
|
DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPACER WIDTHS & DUAL RAISED SOURCE DRAIN EXPITAXIAL SILICON AND TRIPLE-NITRIDE SPACER INTEGRATION ENABLING HIGH-VOLTAGE EG DEVICE ON FDSOI
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
15711714
|
Filing Dt:
|
09/21/2017
|
Publication #:
|
|
Pub Dt:
|
01/11/2018
| | | | |
Title:
|
METHODS, APPARATUS AND SYSTEM FOR PROVIDING NMOS-ONLY MEMORY CELLS
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|
|
Patent #:
|
|
Issue Dt:
|
05/21/2019
|
Application #:
|
15712301
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Filing Dt:
|
09/22/2017
|
Publication #:
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|
Pub Dt:
|
03/28/2019
| | | | |
Title:
|
METHODS OF FORMING A GATE CONTACT STRUCTURE FOR A TRANSISTOR
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|
|
Patent #:
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|
Issue Dt:
|
09/03/2019
|
Application #:
|
15712748
|
Filing Dt:
|
09/22/2017
|
Publication #:
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|
Pub Dt:
|
03/28/2019
| | | | |
Title:
|
FIELD-EFFECT TRANSISTORS WITH FINS FORMED BY A DAMASCENE-LIKE PROCESS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15712996
|
Filing Dt:
|
09/22/2017
|
Publication #:
|
|
Pub Dt:
|
03/28/2019
| | | | |
Title:
|
GATE STACK PROCESSES AND STRUCTURES
|
|
|
Patent #:
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|
Issue Dt:
|
05/07/2019
|
Application #:
|
15713064
|
Filing Dt:
|
09/22/2017
|
Publication #:
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|
Pub Dt:
|
01/11/2018
| | | | |
Title:
|
COMMUNICATING OPTICAL SIGNALS BETWEEN STACKED DIES
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|
Patent #:
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|
Issue Dt:
|
03/26/2019
|
Application #:
|
15713756
|
Filing Dt:
|
09/25/2017
|
Publication #:
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|
Pub Dt:
|
01/11/2018
| | | | |
Title:
|
SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION
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|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
15713843
|
Filing Dt:
|
09/25/2017
|
Title:
|
CRACK-STOP STRUCTURE FOR AN IC PRODUCT AND METHODS OF MAKING SUCH A CRACK-STOP STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
09/04/2018
|
Application #:
|
15715220
|
Filing Dt:
|
09/26/2017
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE INCORPORATING NON-PLANAR FIELD EFFECT TRANSISTORS WITH DIFFERENT CHANNEL REGION HEIGHTS AND METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
09/17/2019
|
Application #:
|
15716287
|
Filing Dt:
|
09/26/2017
|
Publication #:
|
|
Pub Dt:
|
03/28/2019
| | | | |
Title:
|
METHODS, APPARATUS AND SYSTEM FOR STRINGER DEFECT REDUCTION IN A TRENCH CUT REGION OF A FINFET DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
10/09/2018
|
Application #:
|
15717336
|
Filing Dt:
|
09/27/2017
|
Publication #:
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|
Pub Dt:
|
01/18/2018
| | | | |
Title:
|
STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)
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|
|
Patent #:
|
|
Issue Dt:
|
04/30/2019
|
Application #:
|
15718958
|
Filing Dt:
|
09/28/2017
|
Publication #:
|
|
Pub Dt:
|
01/18/2018
| | | | |
Title:
|
COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIGHTS AND METHODS OF MANUFACTURING SAME
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|
|
Patent #:
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|
Issue Dt:
|
08/11/2020
|
Application #:
|
15719014
|
Filing Dt:
|
09/28/2017
|
Publication #:
|
|
Pub Dt:
|
08/16/2018
| | | | |
Title:
|
SELF-ALIGNED SACRIFICIAL EPITAXIAL CAPPING FOR TRENCH SILICIDE
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|
|
Patent #:
|
|
Issue Dt:
|
04/24/2018
|
Application #:
|
15723232
|
Filing Dt:
|
10/03/2017
|
Title:
|
METHOD OF MAKING SELF-ALIGNED CONTINUITY CUTS IN MANDREL AND NON-MANDREL METAL LINES
|
|
|
Patent #:
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|
Issue Dt:
|
05/29/2018
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Application #:
|
15723416
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Filing Dt:
|
10/03/2017
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Title:
|
SILICON LINER FOR STI CMP STOP IN FINFET
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|
|
Patent #:
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|
Issue Dt:
|
04/02/2019
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Application #:
|
15723472
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Filing Dt:
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10/03/2017
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Publication #:
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|
Pub Dt:
|
04/04/2019
| | | | |
Title:
|
METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE LENGTHS AND A RESULTING STRUCTURE
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Patent #:
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|
Issue Dt:
|
07/09/2019
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Application #:
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15724431
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Filing Dt:
|
10/04/2017
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Publication #:
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|
Pub Dt:
|
04/04/2019
| | | | |
Title:
|
INTERCONNECT STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
08/20/2019
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Application #:
|
15724493
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Filing Dt:
|
10/04/2017
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Publication #:
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Pub Dt:
|
02/15/2018
| | | | |
Title:
|
THRU-SILICON-VIA STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
08/21/2018
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Application #:
|
15724563
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Filing Dt:
|
10/04/2017
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Publication #:
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Pub Dt:
|
02/01/2018
| | | | |
Title:
|
PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF
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|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
15725109
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Filing Dt:
|
10/04/2017
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Publication #:
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|
Pub Dt:
|
02/08/2018
| | | | |
Title:
|
OXIDIZING FILLER MATERIAL LINES TO INCREASE WIDTH OF HARD MASK LINES
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
15725524
|
Filing Dt:
|
10/05/2017
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Publication #:
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|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
NON-PLANAR WAVEGUIDE STRUCTURES
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
15726359
|
Filing Dt:
|
10/05/2017
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Publication #:
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|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
Methods, Apparatus and System for Dose Control for Semiconductor Wafer Processing
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
15727040
|
Filing Dt:
|
10/06/2017
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Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
BACK-GATE CONTROLLED VARACTOR
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|
|
Patent #:
|
|
Issue Dt:
|
11/12/2019
|
Application #:
|
15728070
|
Filing Dt:
|
10/09/2017
|
Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
SCALED MEMORY STRUCTURES OR OTHER LOGIC DEVICES WITH MIDDLE OF THE LINE CUTS
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|
|
Patent #:
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|
Issue Dt:
|
02/11/2020
|
Application #:
|
15728445
|
Filing Dt:
|
10/09/2017
|
Publication #:
|
|
Pub Dt:
|
02/01/2018
| | | | |
Title:
|
METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE
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|
|
Patent #:
|
|
Issue Dt:
|
09/04/2018
|
Application #:
|
15728615
|
Filing Dt:
|
10/10/2017
|
Publication #:
|
|
Pub Dt:
|
05/17/2018
| | | | |
Title:
|
METHOD FOR FABRICATING A FINFET METALLIZATION ARCHITECTURE USING A SELF-ALIGNED CONTACT ETCH
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|
|
Patent #:
|
|
Issue Dt:
|
05/14/2019
|
Application #:
|
15728632
|
Filing Dt:
|
10/10/2017
|
Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
METHODS OF FORMING CONDUCTIVE CONTACT STRUCTURES TO SEMICONDUCTOR DEVICES AND THE RESULTING STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
03/03/2020
|
Application #:
|
15728679
|
Filing Dt:
|
10/10/2017
|
Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
TRANSISTOR ELEMENT WITH REDUCED LATERAL ELECTRICAL FIELD
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|
|
Patent #:
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|
Issue Dt:
|
08/21/2018
|
Application #:
|
15729051
|
Filing Dt:
|
10/10/2017
|
Publication #:
|
|
Pub Dt:
|
02/01/2018
| | | | |
Title:
|
METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15729067
|
Filing Dt:
|
10/10/2017
|
Publication #:
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|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
INTEGRATED CIRCUITS INCLUDING A STATIC RANDOM ACCESS MEMORY CELL HAVING ENHANCED READ/WRITE PERFORMANCE, METHODS OF FORMING THE INTEGRATED CIRCUITS, AND METHODS OF OPERATING THE INTEGRATED CIRCUITS
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|
|
Patent #:
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|
Issue Dt:
|
07/03/2018
|
Application #:
|
15729105
|
Filing Dt:
|
10/10/2017
|
Title:
|
INNER SPACER FORMATION FOR NANOSHEET FIELD-EFFECT TRANSISTORS WITH TALL SUSPENSIONS
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|
|
Patent #:
|
|
Issue Dt:
|
07/02/2019
|
Application #:
|
15729774
|
Filing Dt:
|
10/11/2017
|
Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH SUPERIOR CRACK RESISTIVITY IN THE METALLIZATION SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
15729815
|
Filing Dt:
|
10/11/2017
|
Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
ENGINEERING OF FERROELECTRIC MATERIALS IN SEMICONDUCTOR DEVICES BY SURFACE POTENTIAL MODULATION
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|
|
Patent #:
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|
Issue Dt:
|
10/22/2019
|
Application #:
|
15729992
|
Filing Dt:
|
10/11/2017
|
Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
INSULATING INDUCTOR CONDUCTORS WITH AIR GAP USING ENERGY EVAPORATION MATERIAL (EEM)
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|
|
Patent #:
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|
Issue Dt:
|
08/27/2019
|
Application #:
|
15730078
|
Filing Dt:
|
10/11/2017
|
Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
MARGIN TEST FOR MULTIPLE-TIME PROGRAMMABLE MEMORY (MTPM) WITH SPLIT WORDLINES
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|
|
Patent #:
|
|
Issue Dt:
|
04/09/2019
|
Application #:
|
15730107
|
Filing Dt:
|
10/11/2017
|
Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
MARGIN TEST FOR ONE-TIME PROGRAMMABLE MEMORY (OTPM) ARRAY WITH COMMON MODE CURRENT SOURCE
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|
|
Patent #:
|
|
Issue Dt:
|
01/08/2019
|
Application #:
|
15782380
|
Filing Dt:
|
10/12/2017
|
Publication #:
|
|
Pub Dt:
|
02/22/2018
| | | | |
Title:
|
ETCH STOP FOR AIRGAP PROTECTION
|
|
|
Patent #:
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|
Issue Dt:
|
10/15/2019
|
Application #:
|
15783270
|
Filing Dt:
|
10/13/2017
|
Publication #:
|
|
Pub Dt:
|
04/18/2019
| | | | |
Title:
|
NEGATIVE CAPACITANCE INTEGRATION THROUGH A GATE CONTACT
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|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
15783549
|
Filing Dt:
|
10/13/2017
|
Publication #:
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|
Pub Dt:
|
04/18/2019
| | | | |
Title:
|
CUT INSIDE REPLACEMENT METAL GATE TRENCH TO MITIGATE N-P PROXIMITY EFFECT
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|
|
Patent #:
|
|
Issue Dt:
|
10/13/2020
|
Application #:
|
15784408
|
Filing Dt:
|
10/16/2017
|
Publication #:
|
|
Pub Dt:
|
04/18/2019
| | | | |
Title:
|
EXTREME ULTRAVIOLET (EUV) LITHOGRAPHY MASK
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|
|
Patent #:
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|
Issue Dt:
|
03/19/2019
|
Application #:
|
15784445
|
Filing Dt:
|
10/16/2017
|
Title:
|
INTEGRATION OF GATE STRUCTURES AND SPACERS WITH AIR GAPS
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|
|
Patent #:
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|
Issue Dt:
|
11/27/2018
|
Application #:
|
15784500
|
Filing Dt:
|
10/16/2017
|
Title:
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NEGATIVE CAPACITANCE MATCHING IN GATE ELECTRODE STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
10/16/2018
|
Application #:
|
15785631
|
Filing Dt:
|
10/17/2017
|
Title:
|
VERTICAL TRANSISTOR HAVING BURIED CONTACT, AND CONTACTS USING WORK FUNCTION METALS AND SILICIDES
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|
Patent #:
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|
Issue Dt:
|
06/09/2020
|
Application #:
|
15785665
|
Filing Dt:
|
10/17/2017
|
Publication #:
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|
Pub Dt:
|
02/08/2018
| | | | |
Title:
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DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT
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|
Patent #:
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|
Issue Dt:
|
08/21/2018
|
Application #:
|
15786164
|
Filing Dt:
|
10/17/2017
|
Publication #:
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|
Pub Dt:
|
05/24/2018
| | | | |
Title:
|
METAL LAYER ROUTING LEVEL FOR VERTICAL FET SRAM AND LOGIC CELL SCALING
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|
Patent #:
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|
Issue Dt:
|
10/08/2019
|
Application #:
|
15786284
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Filing Dt:
|
10/17/2017
|
Publication #:
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|
Pub Dt:
|
04/18/2019
| | | | |
Title:
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FINS WITH SINGLE DIFFUSION BREAK FACET IMPROVEMENT USING EPITAXIAL INSULATOR
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
15786986
|
Filing Dt:
|
10/18/2017
|
Publication #:
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|
Pub Dt:
|
04/18/2019
| | | | |
Title:
|
ANGLED BEAM INSPECTION SYSTEM FOR SEMICONDUCTOR DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
01/01/2019
|
Application #:
|
15787009
|
Filing Dt:
|
10/18/2017
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE INCORPORATING MULTIPLE GATE-ALL-AROUND FIELD EFFECT TRANSISTORS HAVING DIFFERENT DRIVE CURRENTS AND METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
03/05/2019
|
Application #:
|
15787146
|
Filing Dt:
|
10/18/2017
|
Publication #:
|
|
Pub Dt:
|
02/08/2018
| | | | |
Title:
|
INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
02/19/2019
|
Application #:
|
15787257
|
Filing Dt:
|
10/18/2017
|
Title:
|
ADVANCED STRUCTURE FOR SELF-ALIGNED CONTACT AND METHOD FOR PRODUCING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
09/25/2018
|
Application #:
|
15789108
|
Filing Dt:
|
10/20/2017
|
Title:
|
MEMORY HAVING THERMOELECTRIC HEAT PUMP AND RELATED IC CHIP PACKAGE AND METHOD
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|
|
Patent #:
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|
Issue Dt:
|
12/25/2018
|
Application #:
|
15790216
|
Filing Dt:
|
10/23/2017
|
Title:
|
METHOD OF FORMING GATE-ALL-AROUND (GAA) FINFET AND GAA FINFET FORMED THEREBY
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|
|
Patent #:
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|
Issue Dt:
|
01/08/2019
|
Application #:
|
15790249
|
Filing Dt:
|
10/23/2017
|
Title:
|
INTEGRATION OF AIR GAPS WITH BACK-END-OF-LINE STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
07/17/2018
|
Application #:
|
15790543
|
Filing Dt:
|
10/23/2017
|
Publication #:
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|
Pub Dt:
|
03/15/2018
| | | | |
Title:
|
WORD LINE VOLTAGE GENERATOR FOR CALCULATING OPTIMUM WORD LINE VOLTAGE LEVEL FOR PROGRAMMABLE MEMORY ARRAY
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|
|
Patent #:
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|
Issue Dt:
|
12/25/2018
|
Application #:
|
15790707
|
Filing Dt:
|
10/23/2017
|
Title:
|
TRANSISTOR WITH IMPROVED CHANNEL MOBILITY
|
|