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Patent #:
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Issue Dt:
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12/10/2019
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Application #:
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15897204
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Filing Dt:
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02/15/2018
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Publication #:
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Pub Dt:
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08/15/2019
| | | | |
Title:
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GATE CUT IN REPLACEMENT METAL GATE PROCESS
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Patent #:
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Issue Dt:
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08/11/2020
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Application #:
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15897416
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Filing Dt:
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02/15/2018
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Publication #:
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Pub Dt:
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08/15/2019
| | | | |
Title:
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CONTACT AND INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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07/07/2020
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Application #:
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15897570
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Filing Dt:
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02/15/2018
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Publication #:
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Pub Dt:
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08/15/2019
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH INTERCONNECT TO SOURCE/DRAIN
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Patent #:
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Issue Dt:
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04/30/2019
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Application #:
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15897820
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Filing Dt:
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02/15/2018
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Publication #:
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Pub Dt:
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06/21/2018
| | | | |
Title:
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SYMMETRICAL LATERAL BIPOLAR JUNCTION TRANSISTOR AND USE OF SAME IN CHARACTERIZING AND PROTECTING TRANSISTORS
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Patent #:
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Issue Dt:
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09/10/2019
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Application #:
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15898547
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Filing Dt:
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02/17/2018
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Publication #:
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Pub Dt:
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08/22/2019
| | | | |
Title:
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INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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08/13/2019
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Application #:
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15898555
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Filing Dt:
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02/17/2018
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Publication #:
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Pub Dt:
|
08/22/2019
| | | | |
Title:
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INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES HAVING REDUCED SWITCHING ENERGY BARRIERS FOR DUAL BIT OPERATION AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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11/05/2019
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Application #:
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15898562
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Filing Dt:
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02/17/2018
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Publication #:
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Pub Dt:
|
08/22/2019
| | | | |
Title:
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INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES HAVING REDUCED SWITCHING ENERGY BARRIERS FOR DIFFERENTIAL BIT OPERATION AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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03/31/2020
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Application #:
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15898569
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Filing Dt:
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02/17/2018
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Publication #:
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Pub Dt:
|
08/22/2019
| | | | |
Title:
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MIDDLE OF LINE STRUCTURES
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Patent #:
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Issue Dt:
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02/18/2020
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Application #:
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15898606
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Filing Dt:
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02/18/2018
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Publication #:
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Pub Dt:
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08/22/2019
| | | | |
Title:
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MARK STRUCTURE FOR ALIGNING LAYERS OF INTEGRATED CIRCUIT STRUCTURE AND METHODS OF FORMING SAME
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Patent #:
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Issue Dt:
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05/28/2019
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Application #:
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15898812
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Filing Dt:
|
02/19/2018
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Title:
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METHOD OF FORMING COMPLEMENTARY NANO-SHEET/WIRE TRANSISTOR DEVICES WITH SAME DEPTH CONTACTS
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Patent #:
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Issue Dt:
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05/07/2019
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Application #:
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15899374
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Filing Dt:
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02/20/2018
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Publication #:
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Pub Dt:
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06/21/2018
| | | | |
Title:
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LIGHT EMITTING DIODES (LEDs) WITH INTEGRATED CMOS CIRCUITS
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Patent #:
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Issue Dt:
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02/09/2021
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Application #:
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15899508
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Filing Dt:
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02/20/2018
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Publication #:
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Pub Dt:
|
08/22/2019
| | | | |
Title:
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METHODS OF PERFORMING FIN CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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03/19/2019
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Application #:
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15899685
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Filing Dt:
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02/20/2018
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Publication #:
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Pub Dt:
|
10/18/2018
| | | | |
Title:
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PRE-SPACER SELF-ALIGNED CUT FORMATION
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Patent #:
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Issue Dt:
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11/10/2020
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Application #:
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15899986
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Filing Dt:
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02/20/2018
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Publication #:
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Pub Dt:
|
08/22/2019
| | | | |
Title:
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METHODS AND STRUCTURES FOR A GATE CUT
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Patent #:
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Issue Dt:
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03/19/2019
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Application #:
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15900264
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Filing Dt:
|
02/20/2018
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Title:
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METHODS, APPARATUS AND SYSTEM FOR FORMING WRAP-AROUND CONTACT WITH DUAL SILICIDE
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Patent #:
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Issue Dt:
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08/27/2019
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Application #:
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15901411
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Filing Dt:
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02/21/2018
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Publication #:
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Pub Dt:
|
08/22/2019
| | | | |
Title:
|
DUAL AIRGAP STRUCTURE
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Patent #:
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Issue Dt:
|
08/06/2019
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Application #:
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15901447
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Filing Dt:
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02/21/2018
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Publication #:
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|
Pub Dt:
|
06/28/2018
| | | | |
Title:
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FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH DUAL STRAINED CHANNELS WITH SOLID PHASE DOPING
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Patent #:
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Issue Dt:
|
02/05/2019
|
Application #:
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15901850
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Filing Dt:
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02/21/2018
|
Publication #:
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|
Pub Dt:
|
07/12/2018
| | | | |
Title:
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LEDs WITH THREE COLOR RGB PIXELS FOR DISPLAYS
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Patent #:
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Issue Dt:
|
11/19/2019
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Application #:
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15901979
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Filing Dt:
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02/22/2018
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Publication #:
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Pub Dt:
|
06/28/2018
| | | | |
Title:
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CONTACT USING MULTILAYER LINER
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|
Patent #:
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|
Issue Dt:
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10/02/2018
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Application #:
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15901997
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Filing Dt:
|
02/22/2018
|
Publication #:
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|
Pub Dt:
|
06/28/2018
| | | | |
Title:
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STRUCTURE AND METHOD FOR FULLY DEPLETED SILICON ON INSULATOR STRUCTURE FOR THRESHOLD VOLTAGE MODIFICATION
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Patent #:
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Issue Dt:
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08/04/2020
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Application #:
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15902098
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Filing Dt:
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02/22/2018
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Publication #:
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Pub Dt:
|
08/22/2019
| | | | |
Title:
|
FINFET WITH HIGH-K SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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15902544
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Filing Dt:
|
02/22/2018
|
Publication #:
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|
Pub Dt:
|
08/22/2019
| | | | |
Title:
|
PHOTOLITHOGRAPHY SYSTEM AND METHOD INCORPORATING A PHOTOMASK-PELLICLE APPARATUS WITH AN ANGLED PELLICLE
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Patent #:
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Issue Dt:
|
03/03/2020
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Application #:
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15903203
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Filing Dt:
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02/23/2018
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Publication #:
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Pub Dt:
|
08/29/2019
| | | | |
Title:
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VERTICAL TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL
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Patent #:
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Issue Dt:
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02/18/2020
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Application #:
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15904555
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Filing Dt:
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02/26/2018
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Publication #:
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Pub Dt:
|
08/29/2019
| | | | |
Title:
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INTEGRATED CIRCUIT PRODUCTS WITH GATE STRUCTURES POSITIONED ABOVE ELEVATED ISOLATION STRUCTURES
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Patent #:
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Issue Dt:
|
12/10/2019
|
Application #:
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15904853
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Filing Dt:
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02/26/2018
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Publication #:
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Pub Dt:
|
08/29/2019
| | | | |
Title:
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STRUCTURE AND METHOD TO IMPROVE OVERLAY PERFORMANCE IN SEMICONDUCTOR DEVICES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15904895
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Filing Dt:
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02/26/2018
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Publication #:
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Pub Dt:
|
08/29/2019
| | | | |
Title:
|
RULE CHECK STRUCTURES
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Patent #:
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Issue Dt:
|
10/15/2019
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Application #:
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15904982
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Filing Dt:
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02/26/2018
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Publication #:
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|
Pub Dt:
|
07/05/2018
| | | | |
Title:
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METHOD AND STRUCTURE FOR PROTECTING GATES DURING EPITAXIAL GROWTH
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Patent #:
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Issue Dt:
|
12/18/2018
|
Application #:
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15905134
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Filing Dt:
|
02/26/2018
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Title:
|
WAVEGUIDES WITH MULTIPLE AIRGAPS ARRANGED IN AND OVER A SILICON-ON-INSULATOR SUBSTRATE
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Patent #:
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Issue Dt:
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08/27/2019
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Application #:
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15905165
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Filing Dt:
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02/26/2018
|
Publication #:
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Pub Dt:
|
08/29/2019
| | | | |
Title:
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WAVEGUIDES WITH MULTIPLE-LEVEL AIRGAPS
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Patent #:
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Issue Dt:
|
09/04/2018
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Application #:
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15905621
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Filing Dt:
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02/26/2018
|
Publication #:
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|
Pub Dt:
|
06/28/2018
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING METAL LINE JUMPING OVER MOL FEATURES IN A STANDARD CELL
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Patent #:
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Issue Dt:
|
02/05/2019
|
Application #:
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15906355
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Filing Dt:
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02/27/2018
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Publication #:
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Pub Dt:
|
07/05/2018
| | | | |
Title:
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Nanowire-Based Vertical Memory Cell Array having a Metal Layer Interposed between a Common Back Plate and the Nanowires
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Patent #:
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Issue Dt:
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11/05/2019
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Application #:
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15906368
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Filing Dt:
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02/27/2018
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Publication #:
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|
Pub Dt:
|
08/29/2019
| | | | |
Title:
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MEMS CAPACITIVE PRESSURE SENSORS IN FULLY DEPLETED SEMICONDUCTOR ON INSULATOR (FDSOI)
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Patent #:
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Issue Dt:
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10/27/2020
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Application #:
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15906475
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Filing Dt:
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02/27/2018
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Publication #:
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Pub Dt:
|
08/29/2019
| | | | |
Title:
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ELECTROSTATIC DISCHARGE PROTECTION DEVICE
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Patent #:
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Issue Dt:
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04/28/2020
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Application #:
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15907413
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Filing Dt:
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02/28/2018
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Publication #:
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Pub Dt:
|
08/29/2019
| | | | |
Title:
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METHODS OF MANUFACTURING RF FILTERS
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Patent #:
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Issue Dt:
|
05/14/2019
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Application #:
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15908678
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Filing Dt:
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02/28/2018
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Title:
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METHOD AND APPARATUS FOR USING BACK GATE BIASING FOR POWER AMPLIFIERS FOR MILLIMETER WAVE DEVICES
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Patent #:
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Issue Dt:
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05/05/2020
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Application #:
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15909071
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Filing Dt:
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03/01/2018
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Publication #:
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Pub Dt:
|
09/05/2019
| | | | |
Title:
|
SELF-ALIGNED QUADRUPLE PATTERNING PITCH WALKING SOLUTION
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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15910603
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Filing Dt:
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03/02/2018
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Publication #:
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|
Pub Dt:
|
09/05/2019
| | | | |
Title:
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DEVICE STRUCTURES FORMED WITH A SILICON-ON-INSULATOR SUBSTRATE THAT INCLUDES A TRAP-RICH LAYER
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Patent #:
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Issue Dt:
|
06/09/2020
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Application #:
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15911415
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Filing Dt:
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03/05/2018
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Publication #:
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|
Pub Dt:
|
07/05/2018
| | | | |
Title:
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TRANSISTOR STRUCTURE WITH VARIED GATE CROSS-SECTIONAL AREA
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|
Patent #:
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|
Issue Dt:
|
08/20/2019
|
Application #:
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15911831
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Filing Dt:
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03/05/2018
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Publication #:
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Pub Dt:
|
09/05/2019
| | | | |
Title:
|
STRUCTURES WITH AN AIRGAP AND METHODS OF FORMING SUCH STRUCTURES
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|
Patent #:
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Issue Dt:
|
07/23/2019
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Application #:
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15911892
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Filing Dt:
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03/05/2018
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Publication #:
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|
Pub Dt:
|
07/12/2018
| | | | |
Title:
|
METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
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|
Patent #:
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|
Issue Dt:
|
01/22/2019
|
Application #:
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15912141
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Filing Dt:
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03/05/2018
|
Publication #:
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|
Pub Dt:
|
07/12/2018
| | | | |
Title:
|
FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK EXPOSED REGIONS
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Patent #:
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Issue Dt:
|
03/03/2020
|
Application #:
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15912641
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Filing Dt:
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03/06/2018
|
Publication #:
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|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
SYSTEM AND METHOD FOR PERFORMING FAILURE ANALYSIS USING VIRTUAL THREE-DIMENSIONAL IMAGING
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Patent #:
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Issue Dt:
|
07/09/2019
|
Application #:
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15912975
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Filing Dt:
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03/06/2018
|
Title:
|
INTERCONNECT FORMATION PROCESS USING WIRE TRENCH ETCH PRIOR TO VIA ETCH, AND RELATED INTERCONNECT
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Patent #:
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Issue Dt:
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01/07/2020
|
Application #:
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15913194
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Filing Dt:
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03/06/2018
|
Publication #:
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|
Pub Dt:
|
07/12/2018
| | | | |
Title:
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FINFET WITH MERGE-FREE FINS
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|
Patent #:
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|
Issue Dt:
|
01/05/2021
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Application #:
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15913344
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Filing Dt:
|
03/06/2018
|
Publication #:
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|
Pub Dt:
|
07/12/2018
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING A VARACTOR AND METHOD FOR THE FORMATION THEREOF
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Patent #:
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Issue Dt:
|
07/20/2021
|
Application #:
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15913474
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Filing Dt:
|
03/06/2018
|
Publication #:
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|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
MEMORY CELL ARRAY WITH LARGE GATE WIDTHS
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|
Patent #:
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|
Issue Dt:
|
03/17/2020
|
Application #:
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15914547
|
Filing Dt:
|
03/07/2018
|
Publication #:
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|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
CONTACT STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
04/28/2020
|
Application #:
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15916323
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Filing Dt:
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03/09/2018
|
Publication #:
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|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
FIN-TYPE TRANSISTORS WITH SPACERS ON THE GATES
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Patent #:
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|
Issue Dt:
|
04/21/2020
|
Application #:
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15916594
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Filing Dt:
|
03/09/2018
|
Publication #:
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|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
METAL INSULATOR METAL CAPACITOR DEVICES
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
15917027
|
Filing Dt:
|
03/09/2018
|
Publication #:
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|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
BITCELL LAYOUT FOR A TWO-PORT SRAM CELL EMPLOYING VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS
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Patent #:
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|
Issue Dt:
|
03/19/2019
|
Application #:
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15917940
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Filing Dt:
|
03/12/2018
|
Title:
|
GATE CUT STRUCTURE WITH LINER SPACER AND RELATED METHOD
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|
Patent #:
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|
Issue Dt:
|
05/05/2020
|
Application #:
|
15919079
|
Filing Dt:
|
03/12/2018
|
Publication #:
|
|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
METHODS, APPARATUS, AND SYSTEM FOR REDUCING GATE CUT GOUGING AND/OR GATE HEIGHT LOSS IN SEMICONDUCTOR DEVICES
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|
Patent #:
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|
Issue Dt:
|
07/02/2019
|
Application #:
|
15919119
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Filing Dt:
|
03/12/2018
|
Title:
|
METHODS, APPARATUS AND SYSTEM FOR SELF-ALIGNED METAL HARD MASKS
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|
Patent #:
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|
Issue Dt:
|
06/04/2019
|
Application #:
|
15919594
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Filing Dt:
|
03/13/2018
|
Title:
|
PROTECTED TRENCH ISOLATION FOR FIN-TYPE FIELD-EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
|
01/14/2020
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Application #:
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15919744
|
Filing Dt:
|
03/13/2018
|
Publication #:
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|
Pub Dt:
|
07/19/2018
| | | | |
Title:
|
LATERAL PiN DIODES AND SCHOTTKY DIODES
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|
Patent #:
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|
Issue Dt:
|
06/18/2019
|
Application #:
|
15920303
|
Filing Dt:
|
03/13/2018
|
Title:
|
METHODS, APPARATUS AND SYSTEM FOR PROVIDING A PRE-RMG REPLACEMENT METAL CONTACT FOR A FINFET DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
03/24/2020
|
Application #:
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15920537
|
Filing Dt:
|
03/14/2018
|
Publication #:
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|
Pub Dt:
|
09/19/2019
| | | | |
Title:
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PHOTONIC DIE FAN OUT PACKAGE WITH EDGE FIBER COUPLING INTERFACE AND RELATED METHODS
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|
Patent #:
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|
Issue Dt:
|
12/25/2018
|
Application #:
|
15920677
|
Filing Dt:
|
03/14/2018
|
Publication #:
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|
Pub Dt:
|
08/16/2018
| | | | |
Title:
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CIRCUIT AND METHOD FOR DETECTING TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) SHORTS AND SIGNAL-MARGIN TESTING
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|
Patent #:
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|
Issue Dt:
|
09/17/2019
|
Application #:
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15920748
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Filing Dt:
|
03/14/2018
|
Publication #:
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|
Pub Dt:
|
09/19/2019
| | | | |
Title:
|
VERTICAL FIELD EFFECT TRANSISTORS INCORPORATING U-SHAPED SEMICONDUCTOR BODIES AND METHODS
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Patent #:
|
|
Issue Dt:
|
08/04/2020
|
Application #:
|
15920886
|
Filing Dt:
|
03/14/2018
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Publication #:
|
|
Pub Dt:
|
09/19/2019
| | | | |
Title:
|
GATE-ALL-AROUND TRANSISTOR WITH SPACER SUPPORT AND METHODS OF FORMING SAME
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15921715
|
Filing Dt:
|
03/15/2018
|
Publication #:
|
|
Pub Dt:
|
07/19/2018
| | | | |
Title:
|
METHODS FOR FORMING MOSFETS USING SELECTIVE UNDERCUT AT GATE CONDUCTOR AND GATE INSULATOR CORNER
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|
|
Patent #:
|
|
Issue Dt:
|
07/14/2020
|
Application #:
|
15921852
|
Filing Dt:
|
03/15/2018
|
Publication #:
|
|
Pub Dt:
|
09/19/2019
| | | | |
Title:
|
INTERCONNECTED INTEGRATED CIRCUIT (IC) CHIP STRUCTURE AND PACKAGING AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2019
|
Application #:
|
15922321
|
Filing Dt:
|
03/15/2018
|
Title:
|
CIRCUITS CONSTRUCTED FROM STACKED FIELD-EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2019
|
Application #:
|
15922516
|
Filing Dt:
|
03/15/2018
|
Publication #:
|
|
Pub Dt:
|
09/19/2019
| | | | |
Title:
|
CMOS INVERTERS WITH ASYMMETRIC CONTACT DISTANCES AND METHODS OF MAKING SUCH INVERTERS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15923781
|
Filing Dt:
|
03/16/2018
|
Publication #:
|
|
Pub Dt:
|
09/19/2019
| | | | |
Title:
|
APPARATUS AND METHOD FOR INCREASED PURGE VELOCITY IN SPECIALTY GAS SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2021
|
Application #:
|
15924444
|
Filing Dt:
|
03/19/2018
|
Publication #:
|
|
Pub Dt:
|
09/19/2019
| | | | |
Title:
|
CAVITY FORMATION WITHIN AND UNDER SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
15924447
|
Filing Dt:
|
03/19/2018
|
Title:
|
GATE AND SOURCE/DRAIN CONTACT STRUCTURES POSITIONED ABOVE AN ACTIVE REGION OF A TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2020
|
Application #:
|
15924792
|
Filing Dt:
|
03/19/2018
|
Publication #:
|
|
Pub Dt:
|
09/19/2019
| | | | |
Title:
|
GIMBAL FOR CMP TOOL CONDITIONING DISK HAVING FLEXIBLE METAL DIAPHRAGM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
15925051
|
Filing Dt:
|
03/19/2018
|
Publication #:
|
|
Pub Dt:
|
07/26/2018
| | | | |
Title:
|
STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2020
|
Application #:
|
15925928
|
Filing Dt:
|
03/20/2018
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
Title:
|
COMPOSITE SACRIFICIAL GATE WITH ETCH SELECTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2019
|
Application #:
|
15928783
|
Filing Dt:
|
03/22/2018
|
Title:
|
CONTACTS FORMED WITH SELF-ALIGNED CUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2019
|
Application #:
|
15928910
|
Filing Dt:
|
03/22/2018
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
Title:
|
METHODS, APPARATUS, AND SYSTEM FOR FREQUENCY DOUBLER USING A PASSIVE MIXER FOR MILLIMETER WAVE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2022
|
Application #:
|
15930577
|
Filing Dt:
|
05/13/2020
|
Publication #:
|
|
Pub Dt:
|
11/18/2021
| | | | |
Title:
|
MRAM DEVICE AND METHODS OF MAKING SUCH AN MRAM DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2022
|
Application #:
|
15930876
|
Filing Dt:
|
05/13/2020
|
Publication #:
|
|
Pub Dt:
|
11/18/2021
| | | | |
Title:
|
WAFER-LEVEL TESTING OF LASERS ATTACHED TO PHOTONICS CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2021
|
Application #:
|
15931792
|
Filing Dt:
|
05/14/2020
|
Title:
|
SYSTEM AND METHOD FOR MEASURING ELECTRICAL PROPERTIES OF MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
15933032
|
Filing Dt:
|
03/22/2018
|
Title:
|
GATE OXIDE FORMATION THROUGH HYBRID METHODS OF THERMAL AND DEPOSITION PROCESSES AND METHOD FOR PRODUCING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
12/29/2020
|
Application #:
|
15933449
|
Filing Dt:
|
03/23/2018
|
Publication #:
|
|
Pub Dt:
|
07/26/2018
| | | | |
Title:
|
SELF-ALIGNED VIA FORMING TO CONDUCTIVE LINE AND RELATED WIRING STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2019
|
Application #:
|
15933542
|
Filing Dt:
|
03/23/2018
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
Title:
|
INJECTION LOCK POWER AMPLIFIER WITH BACK-GATE BIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2019
|
Application #:
|
15933579
|
Filing Dt:
|
03/23/2018
|
Title:
|
COMPARATOR HAVING DUPLICATE ALTERNATELY USED TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2019
|
Application #:
|
15933708
|
Filing Dt:
|
03/23/2018
|
Title:
|
GATE CUT IN REPLACEMENT METAL GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
15935606
|
Filing Dt:
|
03/26/2018
|
Title:
|
BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2019
|
Application #:
|
15936149
|
Filing Dt:
|
03/26/2018
|
Publication #:
|
|
Pub Dt:
|
08/02/2018
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING LOW-K SPACER MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2019
|
Application #:
|
15936734
|
Filing Dt:
|
03/27/2018
|
Publication #:
|
|
Pub Dt:
|
10/03/2019
| | | | |
Title:
|
MULTI-STEP INSULATOR FORMATION IN TRENCHES TO AVOID SEAMS IN INSULATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2019
|
Application #:
|
15938412
|
Filing Dt:
|
03/28/2018
|
Publication #:
|
|
Pub Dt:
|
08/02/2018
| | | | |
Title:
|
SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
15938510
|
Filing Dt:
|
03/28/2018
|
Title:
|
GATE CONTACT STRUCTURE POSITIONED ABOVE AN ACTIVE REGION WITH AIR GAPS POSITIONED ADJACENT THE GATE STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15943272
|
Filing Dt:
|
04/02/2018
|
Publication #:
|
|
Pub Dt:
|
10/03/2019
| | | | |
Title:
|
GATE SKIRT OXIDATION FOR IMPROVED FINFET PERFORMANCE AND METHOD FOR PRODUCING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
11/05/2019
|
Application #:
|
15944032
|
Filing Dt:
|
04/03/2018
|
Publication #:
|
|
Pub Dt:
|
10/03/2019
| | | | |
Title:
|
LOGIC-IN-MEMORY COMPUTATIONS FOR NON-VOLATILE RESISTIVE RANDOM ACCESS MEMORY (RAM) ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2019
|
Application #:
|
15944813
|
Filing Dt:
|
04/04/2018
|
Title:
|
CALIBRATION DEVICES FOR I/O DRIVER CIRCUITS HAVING SWITCHES BIASED DIFFERENTLY FOR DIFFERENT TEMPERATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2019
|
Application #:
|
15944885
|
Filing Dt:
|
04/04/2018
|
Publication #:
|
|
Pub Dt:
|
10/10/2019
| | | | |
Title:
|
SEMICONDUCTOR DEVICES INCLUDING SI/GE ACTIVE REGIONS WITH DIFFERENT GE CONCENTRATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2019
|
Application #:
|
15944910
|
Filing Dt:
|
04/04/2018
|
Title:
|
SEMICONDUCTOR DEVICES INCLUDING SELF-ALIGNED ACTIVE REGIONS FOR PLANAR TRANSISTOR ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2020
|
Application #:
|
15945347
|
Filing Dt:
|
04/04/2018
|
Publication #:
|
|
Pub Dt:
|
10/10/2019
| | | | |
Title:
|
GRATING COUPLERS WITH CLADDING LAYER(S)
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2020
|
Application #:
|
15945578
|
Filing Dt:
|
04/04/2018
|
Publication #:
|
|
Pub Dt:
|
08/16/2018
| | | | |
Title:
|
MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15946281
|
Filing Dt:
|
04/05/2018
|
Publication #:
|
|
Pub Dt:
|
10/10/2019
| | | | |
Title:
|
FIELD-EFFECT TRANSISTORS WITH A COMPOSITE CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2020
|
Application #:
|
15947364
|
Filing Dt:
|
04/06/2018
|
Publication #:
|
|
Pub Dt:
|
10/10/2019
| | | | |
Title:
|
SEALED CAVITY STRUCTURES WITH NON-PLANAR SURFACE FEATURES TO INDUCE STRESS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15947479
|
Filing Dt:
|
04/06/2018
|
Publication #:
|
|
Pub Dt:
|
08/16/2018
| | | | |
Title:
|
FINFET DEVICE AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15948016
|
Filing Dt:
|
04/09/2018
|
Publication #:
|
|
Pub Dt:
|
10/10/2019
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING FDSOI TRANSISTORS WITH COMPACT GROUND CONNECTION VIA BACK GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2019
|
Application #:
|
15948486
|
Filing Dt:
|
04/09/2018
|
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS WITH A CONTROLLED UNDERCUT FORMED BENEATH THE EXTRINSIC BASE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2020
|
Application #:
|
15948609
|
Filing Dt:
|
04/09/2018
|
Publication #:
|
|
Pub Dt:
|
10/10/2019
| | | | |
Title:
|
ON-CHIP METAL-INSULATOR-METAL (MIM) CAPACITOR AND METHODS AND SYSTEMS FOR FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2020
|
Application #:
|
15948609
|
Filing Dt:
|
04/09/2018
|
Publication #:
|
|
Pub Dt:
|
10/10/2019
| | | | |
Title:
|
ON-CHIP METAL-INSULATOR-METAL (MIM) CAPACITOR AND METHODS AND SYSTEMS FOR FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2020
|
Application #:
|
15949730
|
Filing Dt:
|
04/10/2018
|
Publication #:
|
|
Pub Dt:
|
10/10/2019
| | | | |
Title:
|
FINFET DEVICE WITH A WRAP-AROUND SILICIDE SOURCE/DRAIN CONTACT STRUCTURE
|
|