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03/20/2001
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09260821
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03/02/1999
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Title:
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METHOD FOR FABRICATING A MOSFET DEVICE STRUCTURE WHICH FACILITATES MITIGATION OF JUNCTION CAPACITANCE AND FLOATING BODY EFFECTS
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09/28/2004
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09260869
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03/02/1999
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07/04/2002
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REFLECTIVE LIGHTVALVE
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02/20/2001
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09261273
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03/03/1999
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MULTIPLE SEMICONDUCTOR-ON-INSULATOR THRESHOLD VOLTAGE CIRCUIT
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01/30/2001
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09261515
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03/03/1999
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THIN FILM TRANSISTORS WITH ORGANIC-INORGANIC HYBRID MATERIALS AS SEMICONDUCTING CHANNELS
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07/18/2000
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09261638
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03/03/1999
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METHODS FOR REPAIR PHOTOMASKS
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12/26/2000
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09261886
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03/03/1999
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Title:
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APPARATUS AND METHOD FOR FLOATING POINT EXCHANGE DISPATCH WITH REDUCED LATENCY
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07/10/2001
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09262214
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03/04/1999
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Title:
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DUMMY PATTERNING FOR SEMICONDUCTOR MANUFACTURING PROCESSES
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07/27/2004
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09262690
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03/04/1999
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OPEN-BOTTOMED VIA LINER STRUCTURE AND METHOD FOR FABRICATING SAME
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05/23/2000
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09262691
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03/04/1999
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ELECTRO ETCH CHEMICAL MECHANICAL POLISHING EQUIPMENT
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10/02/2001
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09263394
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03/05/1999
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Title:
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METHOD OF FORMING FOUR TRANSISTOR SRAM CELL HAVING A RESISTOR
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11/06/2001
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09263557
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03/08/1999
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Title:
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MOS TRANSISTOR WITH ASSISTED-GATE FOR ULTRA-LARGE-SCALE INTEGRATION
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07/27/2004
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09263948
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03/08/1999
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TWO-PART MEMORY ADDRESS GENERATOR
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03/27/2001
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09265161
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03/09/1999
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LOW TEMPERATURE THIN FILM TRANSISTOR FABRICATION
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09/26/2000
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09266341
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03/11/1999
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PHOTORESIST COMPOSITIONS WITH CYCLIC OLEFIN POLYMERS AND HYDROPHOBIC NON-STEROIDAL MULTI-ALICYCLIC ADDITIVES
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10/03/2000
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09266586
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03/11/1999
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CAPPED SOLDER BUMPS WHICH FORM AN INTERCONNECTION WITH A TAILORED REFLOW MELTING POINT
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08/22/2000
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09266658
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03/11/1999
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METHOD OF FABRICATING MULTILAYER PRINTED CIRCUIT BOARD
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04/03/2001
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09268527
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03/12/1999
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POLYCRYSTALLINE CONDUCTING POLYMERS AND PRECURSORS THEREOF HAVING ADJUSTABLE MORPHOLOGY AND PROPERTIES
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10/30/2001
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09270240
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03/15/1999
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SYSTEM FOR USING AN INDEPENDENT CLOCK TO COORDINATE ACCESS TO DATA REGISTERS WITHIN A MODULE BETWEEN PERIPHERAL DEVICE AND A HOST SYSTEM
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01/22/2002
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09272517
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03/19/1999
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STRESS RELIEVED BALL GRID ARRAY PACKAGE
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04/08/2008
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09275568
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03/24/1999
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SIMILARITY SEARCHING OF MOLECULES BASED UPON DESCRIPTOR VECTORS CHARACTERIZING MOLECULAR REGIONS
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08/15/2000
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09276160
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03/25/1999
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Title:
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CLOSELY PITCHED POLYSILICON FUSES AND METHOD OF FORMING THE SAME
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05/14/2002
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09276422
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03/25/1999
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METHODS FOR IDENTIFYING SOURCES OF PATTERNS IN PROCESSING EFFECTS IN MANUFACTURING
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01/22/2002
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09276839
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03/26/1999
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Title:
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METHOD FOR RAMPED CURRENT DENSITY PLATING OF SEMICONDUCTOR VIAS AND TRENCHES
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07/09/2002
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09277511
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03/26/1999
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METHOD FOR FABRICATING HIGH PERMITIVITY DIELECTRIC STACKS HAVING LOW BUFFER OXIDE
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08/06/2002
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09277699
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03/26/1999
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04/25/2002
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Title:
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WIRING STRUCTURES CONTAINING INTERCONNECTED METAL AND WIRING LEVELS INCLUDING A CONTINOUS, SINGLE CRYSTALLINE OR POLYCRYSTALLINE CONDUCTIVE MATERIAL HAVING ONE OR MORE TWIN BOUNDARIES
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01/02/2001
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09280391
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03/29/1999
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(METHOD OF MAKING) A CHEMICAL-MECHANICAL POLISHING SLURRY THAT REDUCES WAFER DEFECTS
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05/07/2002
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09280648
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03/29/1999
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Title:
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A SYSTEM FOR TESTING TRANSMITTER LOGIC OF A PHYSICAL LAYER DEVICE IN A LOCAL AREA NETWORK
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10/01/2002
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09281079
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03/30/1999
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DETECTING FULL CONDITIONS IN A QUEUE
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12/12/2000
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09281905
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03/31/1999
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Title:
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DRIVER WITH SWITCHABLE GAIN
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12/03/2002
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09281975
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03/31/1999
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Title:
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FRAME ASSEMBLY IN DEQUEUING BLOCK
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08/15/2000
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09282033
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03/30/1999
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Title:
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METHOD OF MAKING DISPOSABLE CHANNEL MASKING FOR BOTH SOURCE/DRAIN AND LDD IMPLANT AND SUBSEQUENT GATE FABRICATION
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12/30/2008
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09282141
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03/31/1999
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PORTABLE COMPUTER SYSTEM WITH THERMAL ENHANCEMENTS AND MULTIPLE POWER MODES OF OPERATION
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09/12/2000
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09282576
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03/31/1999
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APPLICATIONS OF MICRO-ELECTRO-MECHANICAL WOBBLE MOTORS AS RADIO FREQUENCY TRANSCEIVER COMPONENTS
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07/13/2004
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09283387
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03/31/1999
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01/02/2003
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Title:
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METHOD AND SYSTEM FOR GRAPHICS RENDERING USING HARDWARE-EVENT-TRIGGERED EXECUTION OF CAPTURED GRAPHICS HARDWARE INSTRUCTIONS
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09/18/2001
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09283679
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04/01/1999
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PROCESS FOR DESIGN AND MANUFACTURE OF FINE LINE CIRCUITS ON PLANARIZED THIN FILM DIELECTRICS AND CIRCUITS MANUFACTURED THEREBY
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12/26/2000
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09283753
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04/02/1999
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Title:
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POLYSILICON GATE HAVING A METAL PLUG FOR REDUCED GATE RESISTANCE WITHIN A TRENCH EXTENDING INTO THE POLYSILICON LAYER OF THE GATE
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06/26/2001
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09283754
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04/02/1999
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Title:
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PLASMA TREATMENT TO REDUCE STRESS CORROSION INDUCED VOIDING OF PATTERNED METAL LAYERS
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07/09/2002
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09283889
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04/01/1999
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Title:
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METHOD TO PRODUCE SMALL SPACE PATTERN USING PLASMA POLYMERIZATION LAYER
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12/25/2001
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09285388
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04/02/1999
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Title:
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METHOD OF REDUCING STRESS CORROSION INDUCED VOIDING OF PATTERNED METAL LAYERS
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02/20/2001
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09286401
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04/05/1999
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FORMING MINIMAL SIZE SPACES IN INTEGRATED CIRCUIT CONDUCTIVE LINES
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07/08/2003
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09286997
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04/07/1999
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ADAPTIVE TRANSMISSION SYSTEM IN A NETWORK
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02/05/2002
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09287173
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04/06/1999
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Title:
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MANAGING VT FOR REDUCED POWER USING A STATUS TABLE
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12/11/2001
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09288051
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04/07/1999
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LOW CTE POWER AND GROUND PLANES
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11/14/2000
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09289669
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04/12/1999
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HIGH DENSITY ISOLATION USING AN IMPLANT AS A POLISH STOP
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03/04/2003
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09289950
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04/13/1999
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NETWORK TRANSCEIVER HAVING MEDIA INDEPENDENT INTERFACE OPERABLE IN A GENERAL PURPOSE SERIAL INTERFACE MODE
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08/06/2002
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09289951
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04/13/1999
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NETWORK TRANSCEIVER HAVING CIRCUITRY FOR REFERENCING TRANSMIT DATA TO A SELECTED INPUT CLOCK
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01/14/2003
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09289953
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04/13/1999
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HANDSHAKING BETWEEN REPEATER AND PHYSICAL LAYER DEVICE IN A VARIABLE RATE NETWORK TRANSCEIVER
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03/23/2004
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09290048
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04/12/1999
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ACOUSTIC NOISE SUPPRESSING CIRCUIT BY SELECTIVE ENABLEMENT OF AN INTERPOLATOR
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09/11/2001
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09290086
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04/12/1999
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PROCESS FOR FABRICATING A METAL SEMICONDUCTOR DEVICE COMPONENT BY LATERAL OXIDIZATION
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04/03/2001
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09290087
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04/12/1999
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PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE COMPONENT USING A SELECTIVE SILICIDATION REACTION
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11/27/2001
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09290088
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04/12/1999
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PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE COMPONENT BY OXIDIZING A SILICON HARD MASK
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07/10/2001
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09290311
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04/12/1999
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POLYMER ENHANCED COLUMN GRID ARRAY
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04/10/2001
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09290555
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04/12/1999
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PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE COMPONENT USING LATERAL METAL OXIDATION
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02/27/2001
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09290755
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04/13/1999
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METHOD OF FORMING A COMPLEMENTARY ACTIVE PIXEL SENSOR CELL
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06/26/2001
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09290778
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04/13/1999
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BULK AND STRAINED SILICON ON INSULATOR USING LOCAL SELECTIVE OXIDATION
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10/10/2000
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09290784
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04/13/1999
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PARTICLE BEAM SYSTEM WITH DYNAMIC FOCUSING
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10/31/2000
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09291036
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04/14/1999
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AUTO-NEGOTIATION USING NEGATIVE LINK PULSES
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04/17/2001
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09291040
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04/14/1999
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POLISHING PAD AND METHOD FOR POLISHING POROUS MATERIALS
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08/07/2001
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09291138
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04/12/1999
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MODIFIED MATERIAL DEPOSITION SEQUENCE FOR REDUCED DETECT DENSITIES IN SEMICONDUCTOR MANUFACTURING
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04/02/2002
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09291389
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04/13/1999
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BLENDS OF HYDROXYSTYRENE POLYMERS FOR USE IN CHEMICALLY AMPLIFIED POSITIVE RESIST FORMULATIONS
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08/08/2000
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09291984
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04/14/1999
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FAST CHIP ERASE MODE FOR NON-VOLATILE MEMORY
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01/30/2001
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09292769
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04/14/1999
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SYSTEM FOR MAKING ELECTROPHORETIC DIES WHILE REDUCING DAMAGE DUE TO ELECTROSTATIC CHARGE
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07/16/2002
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09292913
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04/16/1999
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METHOD OF FORMING ELECTRODE FOR HIGH PERFORMANCE SEMICONDUCTOR DEVICES
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08/15/2000
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09293559
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04/15/1999
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METHOD OF IMPROVING CU DAMASCENE INTERCONNECT RELIABILITY BY LASER ANNEAL BEFORE BARRIER POLISH
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02/05/2002
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09294076
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04/19/1999
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SELF-ALIGNED DAMASCENE INTERCONNECT
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11/09/2004
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09294178
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04/19/1999
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04/24/2003
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METHOD FOR STATICALLY TIMING SOI DEVICES AND CIRCUITS
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05/22/2001
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09295271
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04/20/1999
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RESIST REMOVAL BY POLISHING
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05/29/2001
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09295357
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04/21/1999
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Title:
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WIRE BONDING CU INTERCONNECTS
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12/12/2000
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09295362
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04/21/1999
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BORDERLESS VIAS WITH CVD BARRIER LAYER
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04/16/2002
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09295977
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04/21/1999
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APPARATUS AND METHOD FOR PROVIDING LIST AND READ LIST CAPABILITY FOR A HOST COMPUTER SYSTEM
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04/09/2002
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09295978
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04/21/1999
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APPARATUS AND METHOD FOR PROVIDING A WAIT FOR STATUS CHANGE CAPABILITY FOR A HOST COMPUTER SYSTEM
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06/25/2002
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09296043
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04/21/1999
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SEMICONDUCTOR WAFER ALIGNMENT METHOD USING AN IDENTIFICATION SCRIBE
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07/10/2001
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09296054
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04/21/1999
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APPARATUS AND METHOD OF ENCAPSULATED COPPER (CU) INTERCONNECT FORMATION
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01/01/2002
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Application #:
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09296551
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Filing Dt:
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04/22/1999
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Title:
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INCREASED SPEED INITIALIZATION USING DYNAMIC SLOT ALLOCATION
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09296552
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Filing Dt:
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04/22/1999
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Title:
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OPTIMIZED TRENCH/VIA PROFILE FOR DAMASCENE FILLING
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09298690
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Filing Dt:
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04/23/1999
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Title:
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MERCURY PROCESS GOLD BALLBOND REMOVAL APPARATUS
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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09299477
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Filing Dt:
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04/26/1999
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Title:
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PROCESS FOR CONTROLLING ETCHING PARAMETERS
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09300762
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Filing Dt:
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04/26/1999
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Title:
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POROUS POWER AND GROUND PLANES FOR REDUCED PCB DELAMINATION AND BETTER RELIABILITY
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09301050
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Filing Dt:
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04/28/1999
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Title:
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METHOD AND APPARATUS FOR SLURRY POLISHING
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09301263
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Filing Dt:
|
04/28/1999
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Title:
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SEPARATELY OPTIMIZED GATE STRUCTURES FOR N-CHANNEL AND P-CHANNEL TRANSISTORS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
06/26/2001
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Application #:
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09301887
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Filing Dt:
|
04/29/1999
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Title:
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DIELECTRIC ADHESION ENHANCEMENT IN DAMASCENE PROCESS FOR SEMICONDUCTORS
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Patent #:
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Issue Dt:
|
10/29/2002
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Application #:
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09302294
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Filing Dt:
|
04/30/1999
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Title:
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APPARATUS AND METHOD FOR COUPLING ANALOG SUBSCIBER LINES CONNECTED TO A PRIVATE BRANCH EXCHANGE FOR TRANSMISSION OF NETWORK DATA SIGNALS IN A HOME NETWORK
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Patent #:
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Issue Dt:
|
06/24/2003
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Application #:
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09302371
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Filing Dt:
|
04/30/1999
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Title:
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APPARATUS AND METHOD OF IMPLEMENTING A HOME NETWORK BY FILTERING ISDN-BASED SIGNALS WITHIN THE CUSTOMER PREMISES
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Patent #:
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Issue Dt:
|
02/27/2001
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Application #:
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09302634
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Filing Dt:
|
04/29/1999
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Title:
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INPUT STRUCTURE FOR I/O DEVICE
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Patent #:
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|
Issue Dt:
|
10/22/2002
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Application #:
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09302639
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Filing Dt:
|
04/30/1999
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Title:
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METHOD AND APPARATUS FOR MULTIPHASE CHEMICAL MECHANICAL POLISHING
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Patent #:
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Issue Dt:
|
01/01/2002
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Application #:
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09302737
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Filing Dt:
|
04/30/1999
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Title:
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CHEMICAL MECHANICAL POLISHING IN-SITU END POINT SYSTEM
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|
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Patent #:
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Issue Dt:
|
04/17/2001
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Application #:
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09303042
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Filing Dt:
|
04/30/1999
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Title:
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CHIP THERMAL PROTECTION DEVICE
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|
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Patent #:
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|
Issue Dt:
|
03/06/2001
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Application #:
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09303187
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Filing Dt:
|
04/30/1999
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Title:
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AUTOMATED INSPECTION SYSTEM FOR METALLIC SURFACES
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|
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Patent #:
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|
Issue Dt:
|
11/05/2002
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Application #:
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09303277
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Filing Dt:
|
04/30/1999
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Title:
|
METHOD AND STRUCTURES FOR DUAL DEPTH OXYGEN LAYERS IN SILICON-ON-INSULATOR PROCESSES
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|
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Patent #:
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|
Issue Dt:
|
10/02/2001
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Application #:
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09303513
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Filing Dt:
|
05/03/1999
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Title:
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SYSTEM AND METHOD FOR CONDITIONAL MOVING AN OPERAND FROM A SOURCE REGISTER TO DESTINATION REGISTER
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|
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Patent #:
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Issue Dt:
|
10/02/2001
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Application #:
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09303696
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Filing Dt:
|
05/03/1999
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Title:
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CMOS PROCESSS WITH LOW THERMAL BUDGET
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|
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Patent #:
|
|
Issue Dt:
|
02/27/2001
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Application #:
|
09303959
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Filing Dt:
|
05/03/1999
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Title:
|
MOSFET WITH SUPPRESSED GATE-EDGE FRINGING FIELD EFFECT
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|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
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Application #:
|
09304129
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Filing Dt:
|
05/03/1999
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Publication #:
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Pub Dt:
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12/20/2001
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Title:
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HIGH-K GATE DIELECTRIC PROCESS WITH SELF ALIGNED DAMASCENE CONTACT TO DAMASCENE GATE AND A LOW-K INTER LEVEL DIELECTRIC
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|
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Patent #:
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Issue Dt:
|
09/05/2000
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Application #:
|
09304610
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Filing Dt:
|
05/04/1999
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Title:
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ARYL CYANATE AND/OR DIEPOXIDE AND TETRAHYDROPYRANYL-PROTECTED HYDROXYMETHYLATED PHENOLIC OR HYDROXYSTYRENE RESIN
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|
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Patent #:
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Issue Dt:
|
01/01/2002
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Application #:
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09304959
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Filing Dt:
|
05/05/1999
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Title:
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MULTIPORT COMMUNICATION SWITCH HAVING GIGAPORT AND EXPANSION PORTS SHARING THE SAME TIME SLOT IN INTERNAL RULES CHECKER
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|
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Patent #:
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|
Issue Dt:
|
11/12/2002
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Application #:
|
09305662
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Filing Dt:
|
05/05/1999
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Title:
|
INTERLEAVED ACCESS TO ADDRESS TABLE IN NETWORK SWITCHING SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
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Application #:
|
09305906
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Filing Dt:
|
05/05/1999
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Title:
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LOW DIELECTRIC CONSTANT COATING OF CONDUCTIVE MATERIAL IN A DAMASCENE PROCESS FOR SEMICONDUCTORS
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|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
09306458
|
Filing Dt:
|
05/07/1999
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Title:
|
METHOD AND APPARATUS FOR CHANGING REGISTER IMPLEMENTATION WITHOUT CODE CHANGE
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|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09306508
|
Filing Dt:
|
05/06/1999
|
Title:
|
ASYMMETRICAL TRANSISTOR STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09306871
|
Filing Dt:
|
05/07/1999
|
Title:
|
APPARATUS AND METHOD FOR DETECTING AN INVALID RESOURCE CONFIGURATION USING A PLURALITY OF BIT MASK REGISTERS COUPLED TO A STATUS REGISTER IN A SYSTEM HAVING A PLURALITY OF RESOURCES
|
|