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Patent #:
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|
Issue Dt:
|
04/08/2003
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Application #:
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09614234
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Filing Dt:
|
07/12/2000
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Title:
|
ON CHIP ALPHA-PARTICLE DETECTOR
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|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
09614300
|
Filing Dt:
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07/12/2000
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Title:
|
SYSTEM AND METHOD FOR ADHESION IMPROVEMENT AT AN INTERFACE BETWEEN FLUORINE DOPED SILICON OXIDE AND TANTALUM
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|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09614817
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Filing Dt:
|
07/12/2000
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Title:
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Spring contact for providing high current power to an integrated circuit
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|
Patent #:
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|
Issue Dt:
|
04/16/2002
|
Application #:
|
09614894
|
Filing Dt:
|
07/12/2000
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Title:
|
SELF-ALIGNED SOI DEVICE WITH BODY CONTACT AND NISI2 GATE
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|
Patent #:
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|
Issue Dt:
|
12/24/2002
|
Application #:
|
09615149
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Filing Dt:
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07/13/2000
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Title:
|
METHOD OF ASSIGNING INTEGRATED CIRCUIT I/O SIGNALS IN AN INTEGRATED CIRCUIT PACKAGE
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|
Patent #:
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|
Issue Dt:
|
06/25/2002
|
Application #:
|
09615481
|
Filing Dt:
|
07/13/2000
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Title:
|
METHOD AND APPARATUS FOR MODELING THICKNESS PROFILES AND CONTROLLING SUBSEQUENT ETCH PROCESS
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|
Patent #:
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|
Issue Dt:
|
08/26/2003
|
Application #:
|
09616473
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Filing Dt:
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07/14/2000
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Title:
|
METHOD AND SYSTEM FOR POLISHING A SEMICONDUCTOR WAFER
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|
Patent #:
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|
Issue Dt:
|
04/20/2004
|
Application #:
|
09616862
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Filing Dt:
|
07/14/2000
|
Title:
|
METHOD AND SYSTEM FOR MEASURING CHARACTERISTICS OF CURVED FEATURES
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|
|
Patent #:
|
|
Issue Dt:
|
02/05/2002
|
Application #:
|
09616951
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Filing Dt:
|
07/14/2000
|
Title:
|
Capacitor having sidewall spacer protecting the dielectric layer
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|
|
Patent #:
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|
Issue Dt:
|
03/23/2004
|
Application #:
|
09617104
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Filing Dt:
|
07/14/2000
|
Title:
|
METHOD AND APPARATUS FOR JET PRINTING A FLUX PATTERN SELECTIVELY ON FLIP-CHIP BUMPS
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|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09617158
|
Filing Dt:
|
07/17/2000
|
Title:
|
DELIBERATE VOID IN INNERLAYER DIELECTRIC GAPFILL TO REDUCE DIELECTRIC CONSTANT
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|
|
Patent #:
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|
Issue Dt:
|
02/25/2003
|
Application #:
|
09617259
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Filing Dt:
|
07/14/2000
|
Title:
|
OSCILLATOR WITH DIGITALLY VARIABLE PHASE FOR A PHASE-LOCKED LOOP
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09617374
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Filing Dt:
|
07/17/2000
|
Title:
|
LOW K ILD PROCESS BY REMOVABLE ILD
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|
|
Patent #:
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|
Issue Dt:
|
03/18/2003
|
Application #:
|
09617908
|
Filing Dt:
|
07/14/2000
|
Title:
|
METHOD AND APPARATUS FOR MAKING INTEGRATED CIRCUITS HAVING GATED CLOCK TREES
|
|
|
Patent #:
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|
Issue Dt:
|
02/17/2004
|
Application #:
|
09618059
|
Filing Dt:
|
07/17/2000
|
Title:
|
APPARATUS AND METHOD FOR BUFFER-FREE EVALUATION OF PACKET DATA BYTES WITH MULTIPLE MIN TERMS
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|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
09618167
|
Filing Dt:
|
07/17/2000
|
Title:
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METHOD TO ACHIEVE LOW AND STABLE FERROMAGNETIC COUPLING FIELD
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|
Patent #:
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|
Issue Dt:
|
12/27/2005
|
Application #:
|
09618291
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Filing Dt:
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07/18/2000
|
Title:
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FLOW CONTROL ARRANGEMENT IN A NETWORK SWITCH BASED ON PRIORITY TRAFFIC
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|
|
Patent #:
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|
Issue Dt:
|
07/18/2006
|
Application #:
|
09619037
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Filing Dt:
|
07/19/2000
|
Title:
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SYSTEM AND METHOD FOR PROTECTING AGAINST UNAUTHORIZED USE OF SOFTWARE BY AUTOMATICALLY RECEIVING PCI VENDOR ID FROM VENDOR
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|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09619789
|
Filing Dt:
|
07/20/2000
|
Title:
|
Damascene T-gate using a relacs flow
|
|
|
Patent #:
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|
Issue Dt:
|
07/03/2001
|
Application #:
|
09619836
|
Filing Dt:
|
07/20/2000
|
Title:
|
Damascene T-gate using a spacer flow
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09619838
|
Filing Dt:
|
07/20/2000
|
Title:
|
Capacitively coupled DTMOS on SOI for multiple devices
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|
|
Patent #:
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|
Issue Dt:
|
11/20/2001
|
Application #:
|
09620145
|
Filing Dt:
|
07/20/2000
|
Title:
|
T-gate formation using modified damascene processing with two masks
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09620300
|
Filing Dt:
|
07/20/2000
|
Title:
|
T-GATE FORMATION USING A MODIFIED CONVENTIONAL POLY PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09620981
|
Filing Dt:
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07/21/2000
|
Title:
|
FLEXIBLE IMPLEMENTATION OF A SYSTEM MANAGEMENT MODE (SMM) IN A PROCESSOR
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|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09621156
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Filing Dt:
|
07/21/2000
|
Title:
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METHOD OF POROUS DIELECTRIC FORMATION WITH ANODIC TEMPLATE
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|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09621290
|
Filing Dt:
|
07/20/2000
|
Title:
|
ARGON IMPLANTATION AFTER SILICIDATION FOR IMPROVED FLOATING-BODY EFFECTS
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|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09621931
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Filing Dt:
|
07/24/2000
|
Title:
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A SYSTEM AND METHOD FOR SELECTING BETWEEN A VOLTAGE SPECIFIED BY A PROCESSOR AND AN ALTERNATE VOLTAGE TO BE SUPPLIED TO HE PROCESSOR
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|
|
Patent #:
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|
Issue Dt:
|
03/16/2004
|
Application #:
|
09624656
|
Filing Dt:
|
07/25/2000
|
Title:
|
METHOD OF CONTROLLING SHEET RESISTANCE OF METAL SILICIDE REGIONS BY CONTROLLING THE SALICIDE STRIP TIME
|
|
|
Patent #:
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|
Issue Dt:
|
10/23/2001
|
Application #:
|
09624841
|
Filing Dt:
|
07/25/2000
|
Title:
|
INSTRUCTION QUEUE EVALUATING DEPENDENCY VECTOR IN PORTIONS DURING DIFFERENT CLOCK PHASES
|
|
|
Patent #:
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|
Issue Dt:
|
09/23/2003
|
Application #:
|
09625140
|
Filing Dt:
|
07/25/2000
|
Title:
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METHOD AND APPARATUS FOR PERFORMING FINAL CRITICAL DIMENSION CONTROL
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|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09625367
|
Filing Dt:
|
07/26/2000
|
Title:
|
EDGE SEAL RING FOR COPPER DAMASCENE PROCESS AND METHOD FOR FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09625587
|
Filing Dt:
|
07/26/2000
|
Title:
|
Method and apparatus for monitoring material removal tool performance using endpoint time removal rate determination
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|
|
Patent #:
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|
Issue Dt:
|
10/08/2002
|
Application #:
|
09625620
|
Filing Dt:
|
07/26/2000
|
Title:
|
APPARATUS AND METHOD FOR VERIFYING PROCESS INTEGRITY
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|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09625649
|
Filing Dt:
|
07/26/2000
|
Title:
|
PHOTORESIST COMPOSITIONS WITH CYCLIC OLEFIN POLYMERS AND HYDROPHOBIC NON-STEROIDAL MULTI-ALICYCLIC ADDITIVES
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|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09625711
|
Filing Dt:
|
07/25/2000
|
Title:
|
METHOD AND SYSTEM FOR CONTROLLING THE PLASMA TREATMENT OF A TITANIUM NITRIDE LAYER FORMED BY A CHEMICAL VAPOR DEPOSITION PROCESS
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|
|
Patent #:
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|
Issue Dt:
|
03/29/2005
|
Application #:
|
09625996
|
Filing Dt:
|
07/26/2000
|
Title:
|
SYSTEM INITIALIZATION OF MICROCODE-BASED MEMORY BUILT-IN SELF-TEST
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09626454
|
Filing Dt:
|
07/26/2000
|
Title:
|
Method of forming capped copper interconnects with reduced hillocks
|
|
|
Patent #:
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|
Issue Dt:
|
07/22/2003
|
Application #:
|
09626455
|
Filing Dt:
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07/26/2000
|
Title:
|
METHOD OF FORMING COPPER INTERCONNECT CAPPING LAYERS WITH IMPROVED INTERFACE AND ADHESION
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|
|
Patent #:
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|
Issue Dt:
|
06/12/2001
|
Application #:
|
09626556
|
Filing Dt:
|
07/27/2000
|
Title:
|
Processor configured to map logical register numbers to physical register numbers using virtual register numbers
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|
|
Patent #:
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|
Issue Dt:
|
11/25/2003
|
Application #:
|
09626604
|
Filing Dt:
|
07/27/2000
|
Title:
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METHOD AND APPARATUS FOR REMOVING SPECULATIVE MEMORY ACCESSES FROM A MEMORY ACCESS QUEUE FOR ISSUANCE TO MEMORY OR DISCARDING
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|
|
Patent #:
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|
Issue Dt:
|
02/04/2003
|
Application #:
|
09626615
|
Filing Dt:
|
07/27/2000
|
Title:
|
SYSTEM AND METHOD FOR CONTROLLING ACCESS TO A PRIVILEGE-PARTITIONED ADDRESS SPACE WITH A FIXED SET OF ATTRIBUTES
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|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09626666
|
Filing Dt:
|
07/27/2000
|
Title:
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METHOD OF REDUCING PHOTORESIST SHADOWING DURING ANGLED IMPLANTS
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|
|
Patent #:
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|
Issue Dt:
|
05/21/2002
|
Application #:
|
09626668
|
Filing Dt:
|
07/27/2000
|
Title:
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METHOD FOR FORMING VERTICAL PROFILE OF POLYSILICON GATE ELECTRODES
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|
|
Patent #:
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|
Issue Dt:
|
07/22/2003
|
Application #:
|
09627436
|
Filing Dt:
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07/28/2000
|
Title:
|
DETERMINATION OF FLUX COVERAGE
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|
|
Patent #:
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|
Issue Dt:
|
01/08/2002
|
Application #:
|
09627599
|
Filing Dt:
|
07/28/2000
|
Title:
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Low-power DC voltage generator system
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
09627874
|
Filing Dt:
|
07/28/2000
|
Title:
|
METHOD AND APPARATUS FOR MONITORING CONSUMABLE PERFORMANCE
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|
|
Patent #:
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|
Issue Dt:
|
04/16/2002
|
Application #:
|
09628382
|
Filing Dt:
|
08/01/2000
|
Title:
|
METHOD FOR MAKING RAISED SOURCE/DRAIN REGIONS USING LASER
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|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09628822
|
Filing Dt:
|
07/31/2000
|
Title:
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REDUCTION OF VIA ETCH CHARGING DAMAGE THROUGH THE USE OF A CONDUCTING HARD MASK
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|
|
Patent #:
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|
Issue Dt:
|
04/30/2002
|
Application #:
|
09629883
|
Filing Dt:
|
08/01/2000
|
Title:
|
PREVENTION OF DOPANT OUT-DIFFUSION DURING SILICIDATION AND JUNCTION FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09629925
|
Filing Dt:
|
07/31/2000
|
Title:
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SYSTEM MANAGEMENT BUS ADDRESS RESOLUTION PROTOCOL PROXY DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09632499
|
Filing Dt:
|
08/03/2000
|
Title:
|
Method and system for package orientation checking for laser mark operations
|
|
|
Patent #:
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|
Issue Dt:
|
08/06/2002
|
Application #:
|
09633208
|
Filing Dt:
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08/07/2000
|
Title:
|
MULTIPLE ACTIVE LAYER STRUCTURE AND A METHOD OF MAKING SUCH A STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
02/19/2002
|
Application #:
|
09633620
|
Filing Dt:
|
08/07/2000
|
Title:
|
Electroplating multi-trace circuit board substrates using single tie bar
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09633930
|
Filing Dt:
|
08/08/2000
|
Title:
|
METHOD AND APPARATUS FOR DYNAMIC SAMPLING OF A PRODUCTION LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09633960
|
Filing Dt:
|
08/08/2000
|
Title:
|
SILICON WAFER INCLUDING BOTH BULK AND SOI REGIONS AND METHOD FOR FORMING SAME ON A BULK SILICON WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09633963
|
Filing Dt:
|
08/08/2000
|
Title:
|
DEVICE AND METHOD FOR I/Q MODULATION, FREQUENCY TRANSLATION AND UPSAMPLING
|
|
|
Patent #:
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|
Issue Dt:
|
04/30/2002
|
Application #:
|
09634990
|
Filing Dt:
|
08/08/2000
|
Title:
|
Shallow trench isolation formation with two source/drain masks and simplified planarization mask
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09635332
|
Filing Dt:
|
08/09/2000
|
Title:
|
INTEGRATED CIRCUIT CARRIER ARRANGEMENT FOR REDUCING NON-UNIFORMITY IN CURRENT FLOW THROUGH POWER PINS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09636239
|
Filing Dt:
|
08/10/2000
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR TRANSISTOR WITH RECESSED SOURCE AND DRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09636273
|
Filing Dt:
|
08/10/2000
|
Title:
|
METHOD FOR FABRICATING T-SHAPED TRANSISTOR GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2001
|
Application #:
|
09636516
|
Filing Dt:
|
08/10/2000
|
Title:
|
Slurry for chemical mechanical polishing of copper
|
|
|
Patent #:
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|
Issue Dt:
|
11/08/2005
|
Application #:
|
09637015
|
Filing Dt:
|
08/14/2000
|
Title:
|
APPARATUS AND METHOD FOR IDENTIFYING DATA PACKET AT WIRE RATE ON A NETWORK SWITCH PORT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
09637100
|
Filing Dt:
|
08/10/2000
|
Title:
|
LOT SPECIFIC PROCESS DESIGN METHODOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09637710
|
Filing Dt:
|
08/11/2000
|
Title:
|
SYSTEM AND METHOD FOR SYNCHRONIZING A SKIP PATTERN AND INITIALIZING A CLOCK FORWARDING INTERFACE IN A MULTIPLE-CLOCK SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
09638729
|
Filing Dt:
|
08/14/2000
|
Title:
|
BALL GRID ARRAY MODULE
|
|
|
Patent #:
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|
Issue Dt:
|
10/29/2002
|
Application #:
|
09639380
|
Filing Dt:
|
08/15/2000
|
Title:
|
SELF-AMORPHIZED REGIONS FOR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09639784
|
Filing Dt:
|
08/16/2000
|
Title:
|
RESIST COMPOSITIONS CONTAINING BULKY ANHYDRIDE ADDITIVES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09639785
|
Filing Dt:
|
08/16/2000
|
Title:
|
RESIST COMPOSITIONS CONTAINING LACTONE ADDITIVES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09639799
|
Filing Dt:
|
08/17/2000
|
Title:
|
METHOD OF SELECTIVELY CONTROLLING CONTACT RESISTANCE BY CONTROLLING IMPURITY CONCENTRATION AND SILICIDE THICKNESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09639812
|
Filing Dt:
|
08/17/2000
|
Title:
|
Method and apparatus for improved planarity metallization by electroplating and CMP
|
|
|
Patent #:
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|
Issue Dt:
|
02/11/2003
|
Application #:
|
09640081
|
Filing Dt:
|
08/17/2000
|
Title:
|
AVOIDING FLUORINE CONTAMINATION OF COPPER INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09640177
|
Filing Dt:
|
08/17/2000
|
Title:
|
LASER TAILORING RETROGRADE CHANNEL PROFILE IN SURFACES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09640186
|
Filing Dt:
|
08/17/2000
|
Title:
|
NON-UNIFORM CHANNEL PROFILE VIA ENHANCED DIFFUSION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2002
|
Application #:
|
09641205
|
Filing Dt:
|
08/18/2000
|
Title:
|
MANUFACTURIMG A DRAM CELL HAVING AN ANNULAR SIGNAL TRANSFER REGION
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|
|
Patent #:
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|
Issue Dt:
|
05/07/2002
|
Application #:
|
09641436
|
Filing Dt:
|
08/18/2000
|
Title:
|
Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09641727
|
Filing Dt:
|
08/21/2000
|
Title:
|
LOW RESISTANCE COMPOSITE CONTACT STRUCTURE UTILIZING A REACTION BARRIER LAYER UNDER A METAL LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09641834
|
Filing Dt:
|
08/18/2000
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Title:
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METHOD OF FORMING BARRIER LAYERS FOR DAMASCENE INTERCONNECTS
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09642831
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Filing Dt:
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08/22/2000
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Title:
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DETECTION OF FLUX RESIDUE
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09642832
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Filing Dt:
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08/22/2000
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Title:
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Determination of flux prior to package assembly
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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09642959
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Filing Dt:
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08/21/2000
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Title:
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OPTIMIZATION OF OPC DESIGN FACTORS UTILIZING AN ADVANCED ALGORITHM ON A LOW VOLTAGE CD-SEM SYSTEM
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09643072
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Filing Dt:
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08/21/2000
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Title:
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VERTICAL CACHE CONFIGURATION
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09643343
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Filing Dt:
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08/22/2000
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Title:
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Y-gate formation using damascene processing
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09643531
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Filing Dt:
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08/22/2000
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Title:
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SUPER CRITICAL DRYING OF LOW K MATERIALS
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09643591
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Filing Dt:
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08/22/2000
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Title:
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RECORDER BUFFER CONFIGURED TO ALLOCATE STORGE FOR INSTRUCTION RESULTS CORRESPONDING TO PREDEFINED MAXIMUM NUMBER OF CONCURRENTLY RECEIVABLE INSTRUCTIONS INDEPENDENT OF A NUMBER OF INSTRUCTIONS RECEIVED
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09643611
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Filing Dt:
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08/22/2000
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Title:
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T OR T/Y GATE FORMATION USING TRIM ETCH PROCESSING
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Patent #:
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Issue Dt:
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01/03/2006
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Application #:
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09643847
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Filing Dt:
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08/23/2000
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Title:
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DESIGN TOOL FOR INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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03/01/2005
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Application #:
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09644464
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Filing Dt:
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08/23/2000
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Title:
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NETWORK TRANSMITTER WITH DATA FRAME PRIORITY MANAGEMENT FOR DATA TRANSMISSION
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09645499
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Filing Dt:
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08/25/2000
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Title:
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SALICIDE DEVICE WITH BORDERLESS CONTACT BACKGROUND OF THE INVENTION
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09645923
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Filing Dt:
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08/24/2000
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Title:
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METHOD AND SYSTEM TO REDUCE SWITCHING SIGNAL NOISE ON A DEVICE AND A DEVICE AS RESULT THEREOF
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09648862
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Filing Dt:
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08/25/2000
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Title:
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Multilayer ceramic substrate with anchored pad
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09649733
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Filing Dt:
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08/28/2000
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Title:
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ANALOG-TO-DIGITAL CONVERTER
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09650011
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Filing Dt:
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08/29/2000
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Title:
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DUAL-PORT DRAM ARCHITECTURE SYSTEM
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09650153
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Filing Dt:
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08/29/2000
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Title:
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METHOD TO DETERMINE RETRIES FOR PARALLEL ECC CORRECTION IN A PIPELINE
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09650399
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Filing Dt:
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08/29/2000
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Title:
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DISTRIBUTED STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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09650538
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Filing Dt:
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08/30/2000
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Title:
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CVD PLASMA PROCESS TO FILL CONTACT HOLE IN DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09651464
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Filing Dt:
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08/30/2000
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Title:
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CONTRACT METHODOLOGY FOR CONCURRENT HIERARCHICAL DESIGN
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09651891
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Filing Dt:
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08/30/2000
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Title:
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SELECTIVE EPITAXY TO REDUCE GATE/GATE DIELECTRIC INTERFACE ROUGHNESS
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09651893
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Filing Dt:
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08/30/2000
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Title:
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INTEGRATED CIRCUIT PACKAGE INCORPORATING CAMOUFLAGED PROGRAMMABLE ELEMENTS
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09652596
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Filing Dt:
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08/30/2000
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Title:
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CAPACITOR LAMINATE FOR USE IN PRINTED CIRCUIT BOARD AND AS AN INTERCONNECTOR
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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09652647
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Filing Dt:
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08/31/2000
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Title:
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SYSTEM AND METHOD FOR MONITOING AND CONTROLLING A POWER-MANAGEABLE RESOURCE BASED UPON ACTIVITIES OF A PLURALITY OF DEVICES
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