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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
04/08/2003
Application #:
09614234
Filing Dt:
07/12/2000
Title:
ON CHIP ALPHA-PARTICLE DETECTOR
2
Patent #:
Issue Dt:
11/04/2003
Application #:
09614300
Filing Dt:
07/12/2000
Title:
SYSTEM AND METHOD FOR ADHESION IMPROVEMENT AT AN INTERFACE BETWEEN FLUORINE DOPED SILICON OXIDE AND TANTALUM
3
Patent #:
Issue Dt:
04/02/2002
Application #:
09614817
Filing Dt:
07/12/2000
Title:
Spring contact for providing high current power to an integrated circuit
4
Patent #:
Issue Dt:
04/16/2002
Application #:
09614894
Filing Dt:
07/12/2000
Title:
SELF-ALIGNED SOI DEVICE WITH BODY CONTACT AND NISI2 GATE
5
Patent #:
Issue Dt:
12/24/2002
Application #:
09615149
Filing Dt:
07/13/2000
Title:
METHOD OF ASSIGNING INTEGRATED CIRCUIT I/O SIGNALS IN AN INTEGRATED CIRCUIT PACKAGE
6
Patent #:
Issue Dt:
06/25/2002
Application #:
09615481
Filing Dt:
07/13/2000
Title:
METHOD AND APPARATUS FOR MODELING THICKNESS PROFILES AND CONTROLLING SUBSEQUENT ETCH PROCESS
7
Patent #:
Issue Dt:
08/26/2003
Application #:
09616473
Filing Dt:
07/14/2000
Title:
METHOD AND SYSTEM FOR POLISHING A SEMICONDUCTOR WAFER
8
Patent #:
Issue Dt:
04/20/2004
Application #:
09616862
Filing Dt:
07/14/2000
Title:
METHOD AND SYSTEM FOR MEASURING CHARACTERISTICS OF CURVED FEATURES
9
Patent #:
Issue Dt:
02/05/2002
Application #:
09616951
Filing Dt:
07/14/2000
Title:
Capacitor having sidewall spacer protecting the dielectric layer
10
Patent #:
Issue Dt:
03/23/2004
Application #:
09617104
Filing Dt:
07/14/2000
Title:
METHOD AND APPARATUS FOR JET PRINTING A FLUX PATTERN SELECTIVELY ON FLIP-CHIP BUMPS
11
Patent #:
Issue Dt:
09/03/2002
Application #:
09617158
Filing Dt:
07/17/2000
Title:
DELIBERATE VOID IN INNERLAYER DIELECTRIC GAPFILL TO REDUCE DIELECTRIC CONSTANT
12
Patent #:
Issue Dt:
02/25/2003
Application #:
09617259
Filing Dt:
07/14/2000
Title:
OSCILLATOR WITH DIGITALLY VARIABLE PHASE FOR A PHASE-LOCKED LOOP
13
Patent #:
Issue Dt:
02/25/2003
Application #:
09617374
Filing Dt:
07/17/2000
Title:
LOW K ILD PROCESS BY REMOVABLE ILD
14
Patent #:
Issue Dt:
03/18/2003
Application #:
09617908
Filing Dt:
07/14/2000
Title:
METHOD AND APPARATUS FOR MAKING INTEGRATED CIRCUITS HAVING GATED CLOCK TREES
15
Patent #:
Issue Dt:
02/17/2004
Application #:
09618059
Filing Dt:
07/17/2000
Title:
APPARATUS AND METHOD FOR BUFFER-FREE EVALUATION OF PACKET DATA BYTES WITH MULTIPLE MIN TERMS
16
Patent #:
Issue Dt:
12/09/2003
Application #:
09618167
Filing Dt:
07/17/2000
Title:
METHOD TO ACHIEVE LOW AND STABLE FERROMAGNETIC COUPLING FIELD
17
Patent #:
Issue Dt:
12/27/2005
Application #:
09618291
Filing Dt:
07/18/2000
Title:
FLOW CONTROL ARRANGEMENT IN A NETWORK SWITCH BASED ON PRIORITY TRAFFIC
18
Patent #:
Issue Dt:
07/18/2006
Application #:
09619037
Filing Dt:
07/19/2000
Title:
SYSTEM AND METHOD FOR PROTECTING AGAINST UNAUTHORIZED USE OF SOFTWARE BY AUTOMATICALLY RECEIVING PCI VENDOR ID FROM VENDOR
19
Patent #:
Issue Dt:
08/07/2001
Application #:
09619789
Filing Dt:
07/20/2000
Title:
Damascene T-gate using a relacs flow
20
Patent #:
Issue Dt:
07/03/2001
Application #:
09619836
Filing Dt:
07/20/2000
Title:
Damascene T-gate using a spacer flow
21
Patent #:
Issue Dt:
03/19/2002
Application #:
09619838
Filing Dt:
07/20/2000
Title:
Capacitively coupled DTMOS on SOI for multiple devices
22
Patent #:
Issue Dt:
11/20/2001
Application #:
09620145
Filing Dt:
07/20/2000
Title:
T-gate formation using modified damascene processing with two masks
23
Patent #:
Issue Dt:
07/09/2002
Application #:
09620300
Filing Dt:
07/20/2000
Title:
T-GATE FORMATION USING A MODIFIED CONVENTIONAL POLY PROCESS
24
Patent #:
Issue Dt:
09/17/2002
Application #:
09620981
Filing Dt:
07/21/2000
Title:
FLEXIBLE IMPLEMENTATION OF A SYSTEM MANAGEMENT MODE (SMM) IN A PROCESSOR
25
Patent #:
Issue Dt:
05/14/2002
Application #:
09621156
Filing Dt:
07/21/2000
Title:
METHOD OF POROUS DIELECTRIC FORMATION WITH ANODIC TEMPLATE
26
Patent #:
Issue Dt:
12/17/2002
Application #:
09621290
Filing Dt:
07/20/2000
Title:
ARGON IMPLANTATION AFTER SILICIDATION FOR IMPROVED FLOATING-BODY EFFECTS
27
Patent #:
Issue Dt:
06/08/2004
Application #:
09621931
Filing Dt:
07/24/2000
Title:
A SYSTEM AND METHOD FOR SELECTING BETWEEN A VOLTAGE SPECIFIED BY A PROCESSOR AND AN ALTERNATE VOLTAGE TO BE SUPPLIED TO HE PROCESSOR
28
Patent #:
Issue Dt:
03/16/2004
Application #:
09624656
Filing Dt:
07/25/2000
Title:
METHOD OF CONTROLLING SHEET RESISTANCE OF METAL SILICIDE REGIONS BY CONTROLLING THE SALICIDE STRIP TIME
29
Patent #:
Issue Dt:
10/23/2001
Application #:
09624841
Filing Dt:
07/25/2000
Title:
INSTRUCTION QUEUE EVALUATING DEPENDENCY VECTOR IN PORTIONS DURING DIFFERENT CLOCK PHASES
30
Patent #:
Issue Dt:
09/23/2003
Application #:
09625140
Filing Dt:
07/25/2000
Title:
METHOD AND APPARATUS FOR PERFORMING FINAL CRITICAL DIMENSION CONTROL
31
Patent #:
Issue Dt:
03/26/2002
Application #:
09625367
Filing Dt:
07/26/2000
Title:
EDGE SEAL RING FOR COPPER DAMASCENE PROCESS AND METHOD FOR FABRICATION THEREOF
32
Patent #:
Issue Dt:
04/30/2002
Application #:
09625587
Filing Dt:
07/26/2000
Title:
Method and apparatus for monitoring material removal tool performance using endpoint time removal rate determination
33
Patent #:
Issue Dt:
10/08/2002
Application #:
09625620
Filing Dt:
07/26/2000
Title:
APPARATUS AND METHOD FOR VERIFYING PROCESS INTEGRITY
34
Patent #:
Issue Dt:
05/13/2003
Application #:
09625649
Filing Dt:
07/26/2000
Title:
PHOTORESIST COMPOSITIONS WITH CYCLIC OLEFIN POLYMERS AND HYDROPHOBIC NON-STEROIDAL MULTI-ALICYCLIC ADDITIVES
35
Patent #:
Issue Dt:
05/06/2003
Application #:
09625711
Filing Dt:
07/25/2000
Title:
METHOD AND SYSTEM FOR CONTROLLING THE PLASMA TREATMENT OF A TITANIUM NITRIDE LAYER FORMED BY A CHEMICAL VAPOR DEPOSITION PROCESS
36
Patent #:
Issue Dt:
03/29/2005
Application #:
09625996
Filing Dt:
07/26/2000
Title:
SYSTEM INITIALIZATION OF MICROCODE-BASED MEMORY BUILT-IN SELF-TEST
37
Patent #:
Issue Dt:
04/09/2002
Application #:
09626454
Filing Dt:
07/26/2000
Title:
Method of forming capped copper interconnects with reduced hillocks
38
Patent #:
Issue Dt:
07/22/2003
Application #:
09626455
Filing Dt:
07/26/2000
Title:
METHOD OF FORMING COPPER INTERCONNECT CAPPING LAYERS WITH IMPROVED INTERFACE AND ADHESION
39
Patent #:
Issue Dt:
06/12/2001
Application #:
09626556
Filing Dt:
07/27/2000
Title:
Processor configured to map logical register numbers to physical register numbers using virtual register numbers
40
Patent #:
Issue Dt:
11/25/2003
Application #:
09626604
Filing Dt:
07/27/2000
Title:
METHOD AND APPARATUS FOR REMOVING SPECULATIVE MEMORY ACCESSES FROM A MEMORY ACCESS QUEUE FOR ISSUANCE TO MEMORY OR DISCARDING
41
Patent #:
Issue Dt:
02/04/2003
Application #:
09626615
Filing Dt:
07/27/2000
Title:
SYSTEM AND METHOD FOR CONTROLLING ACCESS TO A PRIVILEGE-PARTITIONED ADDRESS SPACE WITH A FIXED SET OF ATTRIBUTES
42
Patent #:
Issue Dt:
05/27/2003
Application #:
09626666
Filing Dt:
07/27/2000
Title:
METHOD OF REDUCING PHOTORESIST SHADOWING DURING ANGLED IMPLANTS
43
Patent #:
Issue Dt:
05/21/2002
Application #:
09626668
Filing Dt:
07/27/2000
Title:
METHOD FOR FORMING VERTICAL PROFILE OF POLYSILICON GATE ELECTRODES
44
Patent #:
Issue Dt:
07/22/2003
Application #:
09627436
Filing Dt:
07/28/2000
Title:
DETERMINATION OF FLUX COVERAGE
45
Patent #:
Issue Dt:
01/08/2002
Application #:
09627599
Filing Dt:
07/28/2000
Title:
Low-power DC voltage generator system
46
Patent #:
Issue Dt:
05/20/2003
Application #:
09627874
Filing Dt:
07/28/2000
Title:
METHOD AND APPARATUS FOR MONITORING CONSUMABLE PERFORMANCE
47
Patent #:
Issue Dt:
04/16/2002
Application #:
09628382
Filing Dt:
08/01/2000
Title:
METHOD FOR MAKING RAISED SOURCE/DRAIN REGIONS USING LASER
48
Patent #:
Issue Dt:
07/30/2002
Application #:
09628822
Filing Dt:
07/31/2000
Title:
REDUCTION OF VIA ETCH CHARGING DAMAGE THROUGH THE USE OF A CONDUCTING HARD MASK
49
Patent #:
Issue Dt:
04/30/2002
Application #:
09629883
Filing Dt:
08/01/2000
Title:
PREVENTION OF DOPANT OUT-DIFFUSION DURING SILICIDATION AND JUNCTION FORMATION
50
Patent #:
Issue Dt:
04/27/2004
Application #:
09629925
Filing Dt:
07/31/2000
Title:
SYSTEM MANAGEMENT BUS ADDRESS RESOLUTION PROTOCOL PROXY DEVICE
51
Patent #:
Issue Dt:
05/07/2002
Application #:
09632499
Filing Dt:
08/03/2000
Title:
Method and system for package orientation checking for laser mark operations
52
Patent #:
Issue Dt:
08/06/2002
Application #:
09633208
Filing Dt:
08/07/2000
Title:
MULTIPLE ACTIVE LAYER STRUCTURE AND A METHOD OF MAKING SUCH A STRUCTURE
53
Patent #:
Issue Dt:
02/19/2002
Application #:
09633620
Filing Dt:
08/07/2000
Title:
Electroplating multi-trace circuit board substrates using single tie bar
54
Patent #:
Issue Dt:
08/27/2002
Application #:
09633930
Filing Dt:
08/08/2000
Title:
METHOD AND APPARATUS FOR DYNAMIC SAMPLING OF A PRODUCTION LINE
55
Patent #:
Issue Dt:
10/15/2002
Application #:
09633960
Filing Dt:
08/08/2000
Title:
SILICON WAFER INCLUDING BOTH BULK AND SOI REGIONS AND METHOD FOR FORMING SAME ON A BULK SILICON WAFER
56
Patent #:
Issue Dt:
03/18/2003
Application #:
09633963
Filing Dt:
08/08/2000
Title:
DEVICE AND METHOD FOR I/Q MODULATION, FREQUENCY TRANSLATION AND UPSAMPLING
57
Patent #:
Issue Dt:
04/30/2002
Application #:
09634990
Filing Dt:
08/08/2000
Title:
Shallow trench isolation formation with two source/drain masks and simplified planarization mask
58
Patent #:
Issue Dt:
12/17/2002
Application #:
09635332
Filing Dt:
08/09/2000
Title:
INTEGRATED CIRCUIT CARRIER ARRANGEMENT FOR REDUCING NON-UNIFORMITY IN CURRENT FLOW THROUGH POWER PINS
59
Patent #:
Issue Dt:
08/20/2002
Application #:
09636239
Filing Dt:
08/10/2000
Title:
SEMICONDUCTOR-ON-INSULATOR TRANSISTOR WITH RECESSED SOURCE AND DRAIN
60
Patent #:
Issue Dt:
09/10/2002
Application #:
09636273
Filing Dt:
08/10/2000
Title:
METHOD FOR FABRICATING T-SHAPED TRANSISTOR GATE
61
Patent #:
Issue Dt:
12/25/2001
Application #:
09636516
Filing Dt:
08/10/2000
Title:
Slurry for chemical mechanical polishing of copper
62
Patent #:
Issue Dt:
11/08/2005
Application #:
09637015
Filing Dt:
08/14/2000
Title:
APPARATUS AND METHOD FOR IDENTIFYING DATA PACKET AT WIRE RATE ON A NETWORK SWITCH PORT
63
Patent #:
Issue Dt:
03/16/2004
Application #:
09637100
Filing Dt:
08/10/2000
Title:
LOT SPECIFIC PROCESS DESIGN METHODOLOGY
64
Patent #:
Issue Dt:
06/08/2004
Application #:
09637710
Filing Dt:
08/11/2000
Title:
SYSTEM AND METHOD FOR SYNCHRONIZING A SKIP PATTERN AND INITIALIZING A CLOCK FORWARDING INTERFACE IN A MULTIPLE-CLOCK SYSTEM
65
Patent #:
Issue Dt:
10/28/2003
Application #:
09638729
Filing Dt:
08/14/2000
Title:
BALL GRID ARRAY MODULE
66
Patent #:
Issue Dt:
10/29/2002
Application #:
09639380
Filing Dt:
08/15/2000
Title:
SELF-AMORPHIZED REGIONS FOR TRANSISTORS
67
Patent #:
Issue Dt:
05/21/2002
Application #:
09639784
Filing Dt:
08/16/2000
Title:
RESIST COMPOSITIONS CONTAINING BULKY ANHYDRIDE ADDITIVES
68
Patent #:
Issue Dt:
09/30/2003
Application #:
09639785
Filing Dt:
08/16/2000
Title:
RESIST COMPOSITIONS CONTAINING LACTONE ADDITIVES
69
Patent #:
Issue Dt:
05/21/2002
Application #:
09639799
Filing Dt:
08/17/2000
Title:
METHOD OF SELECTIVELY CONTROLLING CONTACT RESISTANCE BY CONTROLLING IMPURITY CONCENTRATION AND SILICIDE THICKNESS
70
Patent #:
Issue Dt:
11/20/2001
Application #:
09639812
Filing Dt:
08/17/2000
Title:
Method and apparatus for improved planarity metallization by electroplating and CMP
71
Patent #:
Issue Dt:
02/11/2003
Application #:
09640081
Filing Dt:
08/17/2000
Title:
AVOIDING FLUORINE CONTAMINATION OF COPPER INTERCONNECTS
72
Patent #:
Issue Dt:
09/03/2002
Application #:
09640177
Filing Dt:
08/17/2000
Title:
LASER TAILORING RETROGRADE CHANNEL PROFILE IN SURFACES
73
Patent #:
Issue Dt:
01/07/2003
Application #:
09640186
Filing Dt:
08/17/2000
Title:
NON-UNIFORM CHANNEL PROFILE VIA ENHANCED DIFFUSION
74
Patent #:
Issue Dt:
01/01/2002
Application #:
09641205
Filing Dt:
08/18/2000
Title:
MANUFACTURIMG A DRAM CELL HAVING AN ANNULAR SIGNAL TRANSFER REGION
75
Patent #:
Issue Dt:
05/07/2002
Application #:
09641436
Filing Dt:
08/18/2000
Title:
Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption
76
Patent #:
Issue Dt:
04/09/2002
Application #:
09641727
Filing Dt:
08/21/2000
Title:
LOW RESISTANCE COMPOSITE CONTACT STRUCTURE UTILIZING A REACTION BARRIER LAYER UNDER A METAL LAYER
77
Patent #:
Issue Dt:
03/19/2002
Application #:
09641834
Filing Dt:
08/18/2000
Title:
METHOD OF FORMING BARRIER LAYERS FOR DAMASCENE INTERCONNECTS
78
Patent #:
Issue Dt:
04/09/2002
Application #:
09642831
Filing Dt:
08/22/2000
Title:
DETECTION OF FLUX RESIDUE
79
Patent #:
Issue Dt:
07/10/2001
Application #:
09642832
Filing Dt:
08/22/2000
Title:
Determination of flux prior to package assembly
80
Patent #:
Issue Dt:
12/07/2004
Application #:
09642959
Filing Dt:
08/21/2000
Title:
OPTIMIZATION OF OPC DESIGN FACTORS UTILIZING AN ADVANCED ALGORITHM ON A LOW VOLTAGE CD-SEM SYSTEM
81
Patent #:
Issue Dt:
09/02/2003
Application #:
09643072
Filing Dt:
08/21/2000
Title:
VERTICAL CACHE CONFIGURATION
82
Patent #:
Issue Dt:
11/06/2001
Application #:
09643343
Filing Dt:
08/22/2000
Title:
Y-gate formation using damascene processing
83
Patent #:
Issue Dt:
11/26/2002
Application #:
09643531
Filing Dt:
08/22/2000
Title:
SUPER CRITICAL DRYING OF LOW K MATERIALS
84
Patent #:
Issue Dt:
05/22/2001
Application #:
09643591
Filing Dt:
08/22/2000
Title:
RECORDER BUFFER CONFIGURED TO ALLOCATE STORGE FOR INSTRUCTION RESULTS CORRESPONDING TO PREDEFINED MAXIMUM NUMBER OF CONCURRENTLY RECEIVABLE INSTRUCTIONS INDEPENDENT OF A NUMBER OF INSTRUCTIONS RECEIVED
85
Patent #:
Issue Dt:
06/11/2002
Application #:
09643611
Filing Dt:
08/22/2000
Title:
T OR T/Y GATE FORMATION USING TRIM ETCH PROCESSING
86
Patent #:
Issue Dt:
01/03/2006
Application #:
09643847
Filing Dt:
08/23/2000
Title:
DESIGN TOOL FOR INTEGRATED CIRCUIT DESIGN
87
Patent #:
Issue Dt:
03/01/2005
Application #:
09644464
Filing Dt:
08/23/2000
Title:
NETWORK TRANSMITTER WITH DATA FRAME PRIORITY MANAGEMENT FOR DATA TRANSMISSION
88
Patent #:
Issue Dt:
03/25/2003
Application #:
09645499
Filing Dt:
08/25/2000
Title:
SALICIDE DEVICE WITH BORDERLESS CONTACT BACKGROUND OF THE INVENTION
89
Patent #:
Issue Dt:
02/18/2003
Application #:
09645923
Filing Dt:
08/24/2000
Title:
METHOD AND SYSTEM TO REDUCE SWITCHING SIGNAL NOISE ON A DEVICE AND A DEVICE AS RESULT THEREOF
90
Patent #:
Issue Dt:
11/06/2001
Application #:
09648862
Filing Dt:
08/25/2000
Title:
Multilayer ceramic substrate with anchored pad
91
Patent #:
Issue Dt:
02/11/2003
Application #:
09649733
Filing Dt:
08/28/2000
Title:
ANALOG-TO-DIGITAL CONVERTER
92
Patent #:
Issue Dt:
04/08/2003
Application #:
09650011
Filing Dt:
08/29/2000
Title:
DUAL-PORT DRAM ARCHITECTURE SYSTEM
93
Patent #:
Issue Dt:
11/25/2003
Application #:
09650153
Filing Dt:
08/29/2000
Title:
METHOD TO DETERMINE RETRIES FOR PARALLEL ECC CORRECTION IN A PIPELINE
94
Patent #:
Issue Dt:
04/29/2003
Application #:
09650399
Filing Dt:
08/29/2000
Title:
DISTRIBUTED STATIC TIMING ANALYSIS
95
Patent #:
Issue Dt:
08/12/2003
Application #:
09650538
Filing Dt:
08/30/2000
Title:
CVD PLASMA PROCESS TO FILL CONTACT HOLE IN DAMASCENE PROCESS
96
Patent #:
Issue Dt:
11/26/2002
Application #:
09651464
Filing Dt:
08/30/2000
Title:
CONTRACT METHODOLOGY FOR CONCURRENT HIERARCHICAL DESIGN
97
Patent #:
Issue Dt:
04/15/2003
Application #:
09651891
Filing Dt:
08/30/2000
Title:
SELECTIVE EPITAXY TO REDUCE GATE/GATE DIELECTRIC INTERFACE ROUGHNESS
98
Patent #:
Issue Dt:
09/10/2002
Application #:
09651893
Filing Dt:
08/30/2000
Title:
INTEGRATED CIRCUIT PACKAGE INCORPORATING CAMOUFLAGED PROGRAMMABLE ELEMENTS
99
Patent #:
Issue Dt:
04/09/2002
Application #:
09652596
Filing Dt:
08/30/2000
Title:
CAPACITOR LAMINATE FOR USE IN PRINTED CIRCUIT BOARD AND AS AN INTERCONNECTOR
100
Patent #:
Issue Dt:
07/06/2004
Application #:
09652647
Filing Dt:
08/31/2000
Title:
SYSTEM AND METHOD FOR MONITOING AND CONTROLLING A POWER-MANAGEABLE RESOURCE BASED UPON ACTIVITIES OF A PLURALITY OF DEVICES
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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