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Reel/Frame:	056987/0001			Pages:	1045
		Recorded:	05/12/2021
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 18026
Page 32 of 181
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Patent #:	6514844	Issue Dt:	02/04/2003	Application #:	09840598	Filing Dt:	04/23/2001
Title:	SIDEWALL TREATMENT FOR LOW DIELECTRIC CONSTANT (LOW K) MATERIALS BY ION IMPLANTATION

Patent #:	6684305	Issue Dt:	01/27/2004	Application #:	09841469	Filing Dt:	04/24/2001
Title:	MULTIPROCESSOR SYSTEM IMPLEMENTING VIRTUAL MEMORY USING A SHARED MEMORY, AND A PAGE REPLACEMENT METHOD FOR MAINTAINING PAGED MEMORY COHERENCE

Patent #:	6383824	Issue Dt:	05/07/2002	Application #:	09843111	Filing Dt:	04/25/2001
Title:	METHOD OF USING SCATTEROMETRY MEASUREMENTS TO CONTROL DEPOSITION PROCESSES

Patent #:	6829682	Issue Dt:	12/07/2004	Application #:	09843504	Filing Dt:	04/26/2001
Publication #:	US20020161967	Pub Dt:	10/31/2002
Title:	DESTRUCTIVE READ ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORIES

Patent #:	6506650	Issue Dt:	01/14/2003	Application #:	09843782	Filing Dt:	04/27/2001
Title:	METHOD OF FABRICATION BASED ON SOLID-PHASE EPITAXY FOR A MOSFET TRANSISTOR WITH A CONTROLLED DOPANT PROFILE

Patent #:	6780735	Issue Dt:	08/24/2004	Application #:	09843783	Filing Dt:	04/30/2001
Publication #:	US20020160587	Pub Dt:	10/31/2002
Title:	METHOD TO INCREASE CARBON AND BORON DOPING CONCENTRATIONS IN SI AND SIGE FILMS

Patent #:	6515333	Issue Dt:	02/04/2003	Application #:	09843958	Filing Dt:	04/27/2001
Title:	REMOVAL OF HEAT FROM SOI DEVICE

Patent #:	6384631	Issue Dt:	05/07/2002	Application #:	09844183	Filing Dt:	04/27/2001
Title:	VOLTAGE LEVEL SHIFTER WITH HIGH IMPEDANCE TRI-STATE OUTPUT AND METHOD OF OPERATION

Patent #:	6475811	Issue Dt:	11/05/2002	Application #:	09844213	Filing Dt:	04/27/2001
Title:	SYSTEM FOR AND METHOD OF USING BACTERIA TO AID IN CONTACT HOLE PRINTING

Patent #:	6528412	Issue Dt:	03/04/2003	Application #:	09844727	Filing Dt:	04/30/2001
Title:	DEPOSITING AN ADHESION SKIN LAYER AND A CONFORMAL SEED LAYER TO FILL AN INTERCONNECT OPENING

Patent #:	6630385	Issue Dt:	10/07/2003	Application #:	09844773	Filing Dt:	04/27/2001
Title:	MOSFET WITH DIFFERENTIAL HALO IMPLANT AND ANNEALING STRATEGY

Patent #:	6586683	Issue Dt:	07/01/2003	Application #:	09844814	Filing Dt:	04/27/2001
Publication #:	US20020157861	Pub Dt:	10/31/2002
Title:	PRINTED CIRCUIT BOARD WITH MIXED METALLURGY PADS OXIDE LAYER AND SOLDER MASK

Patent #:	6420189	Issue Dt:	07/16/2002	Application #:	09844845	Filing Dt:	04/27/2001
Title:	SUPERCONDUCTING DAMASCENE INTERCONNECT FOR INTEGRATED CIRCUIT

Patent #:	6534239	Issue Dt:	03/18/2003	Application #:	09844848	Filing Dt:	04/27/2001
Publication #:	US20020182534	Pub Dt:	12/05/2002
Title:	RESIST COMPOSITIONS WITH POLYMERS HAVING PENDANT GROUPS CONTAINING PLURAL ACID LABILE MOIETIES

Patent #:	7079975	Issue Dt:	07/18/2006	Application #:	09845231	Filing Dt:	04/30/2001
Title:	SCATTEROMETRY AND ACOUSTIC BASED ACTIVE CONTROL OF THIN FILM DEPOSITION PROCESS

Patent #:	6535015	Issue Dt:	03/18/2003	Application #:	09845266	Filing Dt:	04/30/2001
Title:	DEVICE AND METHOD FOR TESTING PERFORMANCE OF SILICON STRUCTURES

Patent #:	7052575	Issue Dt:	05/30/2006	Application #:	09845454	Filing Dt:	04/30/2001
Title:	SYSTEM AND METHOD FOR ACTIVE CONTROL OF ETCH PROCESS

Patent #:	6447933	Issue Dt:	09/10/2002	Application #:	09845616	Filing Dt:	04/30/2001
Title:	FORMATION OF ALLOY MATERIAL USING ALTERNATING DEPOSITIONS OF ALLOY DOPING ELEMENT AND BULK MATERIAL

Patent #:	6753266	Issue Dt:	06/22/2004	Application #:	09845654	Filing Dt:	04/30/2001
Title:	METHOD OF ENHANCING GATE PATTERNING PROPERTIES WITH REFLECTIVE HARD MASK

Patent #:	6440806	Issue Dt:	08/27/2002	Application #:	09845859	Filing Dt:	04/30/2001
Title:	METHOD FOR PRODUCING METAL-SEMICONDUCTOR COMPOUND REGIONS ON SEMICONDUCTOR DEVICES

Patent #:	6458686	Issue Dt:	10/01/2002	Application #:	09845980	Filing Dt:	04/30/2001
Title:	INVERSE INTEGRATED CIRCUIT FABRICATION PROCESS

Patent #:	6506677	Issue Dt:	01/14/2003	Application #:	09846186	Filing Dt:	05/02/2001
Title:	METHOD OF FORMING CAPPED COPPER INTERCONNECTS WITH REDUCED HILLOCK FORMATION AND IMPROVED ELECTROMIGRATION RESISTANCE

Patent #:	6562416	Issue Dt:	05/13/2003	Application #:	09846187	Filing Dt:	05/02/2001
Publication #:	US20020162736	Pub Dt:	11/07/2002
Title:	METHOD OF FORMING LOW RESISTANCE VIAS

Patent #:	6611023	Issue Dt:	08/26/2003	Application #:	09846502	Filing Dt:	05/01/2001
Title:	FIELD EFFECT TRANSISTOR WITH SELF ALLIGNED DOUBLE GATE AND METHOD OF FORMING SAME

Patent #:	6432822	Issue Dt:	08/13/2002	Application #:	09846611	Filing Dt:	05/02/2001
Title:	METHOD OF IMPROVING ELECTROMIGRATION RESISTANCE OF CAPPED CU

Patent #:	6620671	Issue Dt:	09/16/2003	Application #:	09846813	Filing Dt:	05/01/2001
Title:	METHOD OF FABRICATING TRANSISTOR HAVING A SINGLE CRYSTALLINE GATE CONDUCTOR

Patent #:	6448613	Issue Dt:	09/10/2002	Application #:	09846958	Filing Dt:	05/01/2001
Title:	FABRICATION OF A FIELD EFFECT TRANSISTOR WITH MINIMIZED PARASITIC MILLER CAPACITANCE

Patent #:	6593037	Issue Dt:	07/15/2003	Application #:	09847803	Filing Dt:	05/02/2001
Title:	EUV MASK OR RETICLE HAVING REDUCED REFLECTIONS

Patent #:	6566718	Issue Dt:	05/20/2003	Application #:	09848085	Filing Dt:	05/03/2001
Publication #:	US20020056879	Pub Dt:	05/16/2002
Title:	FIELD EFFECT TRANSISTOR WITH AN IMPROVED GATE CONTACT

Patent #:	6780499	Issue Dt:	08/24/2004	Application #:	09848153	Filing Dt:	05/03/2001
Publication #:	US20020164891	Pub Dt:	11/07/2002
Title:	ORDERED TWO-PHASE DIELECTRIC FILM, AND SEMICONDUCTOR DEVICE CONTAINING THE SAME

Patent #:	6577154	Issue Dt:	06/10/2003	Application #:	09848454	Filing Dt:	05/03/2001
Publication #:	US20020163360	Pub Dt:	11/07/2002
Title:	CONSTANT IMPEDANCE DRIVER FOR HIGH SPEED INTERFACE

Patent #:	6521949	Issue Dt:	02/18/2003	Application #:	09848508	Filing Dt:	05/03/2001
Publication #:	US20020164841	Pub Dt:	11/07/2002
Title:	SOI TRANSISTOR WITH POLYSILICON SEED

Patent #:	6735649	Issue Dt:	05/11/2004	Application #:	09848652	Filing Dt:	05/03/2001
Publication #:	US20020166006	Pub Dt:	11/07/2002
Title:	MULTIPLE BUFFERS FOR REMOVING UNWANTED HEADER INFORMATION FROM RECEIVED DATA PACKETS

Patent #:	6498397	Issue Dt:	12/24/2002	Application #:	09848979	Filing Dt:	05/04/2001
Title:	SEED LAYER WITH ANNEALED REGION FOR INTEGRATED CIRCUIT INTERCONNECTS

Patent #:	6410461	Issue Dt:	06/25/2002	Application #:	09849357	Filing Dt:	05/07/2001
Title:	METHOD OF DEPOSITING SION WITH REDUCED DEFECTS

Patent #:	6509613	Issue Dt:	01/21/2003	Application #:	09849494	Filing Dt:	05/04/2001
Title:	SELF-ALIGNED FLOATING BODY CONTROL FOR SOI DEVICE THROUGH LEAKAGE ENHANCED BURIED OXIDE

Patent #:	6821890	Issue Dt:	11/23/2004	Application #:	09849530	Filing Dt:	05/07/2001
Publication #:	US20010023987	Pub Dt:	09/27/2001
Title:	METHOD FOR IMPROVING ADHESION TO COPPER

Patent #:	6424009	Issue Dt:	07/23/2002	Application #:	09849560	Filing Dt:	05/04/2001
Title:	POLYSILICON INSULATOR MATERIAL IN SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE

Patent #:	6512244	Issue Dt:	01/28/2003	Application #:	09850392	Filing Dt:	05/07/2001
Title:	SOI DEVICE WITH STRUCTURE FOR ENHANCING CARRIER RECOMBINATION AND METHOD OF FABRICATING SAME

Patent #:	7122863	Issue Dt:	10/17/2006	Application #:	09850393	Filing Dt:	05/07/2001
Title:	SOI DEVICE WITH STRUCTURE FOR ENHANCING CARRIER RECOMBINATION AND METHOD OF FABRICATING SAME

Patent #:	6838364	Issue Dt:	01/04/2005	Application #:	09850816	Filing Dt:	05/08/2001
Publication #:	US20010029096	Pub Dt:	10/11/2001
Title:	SPUTTERED TUNGSTEN DIFFUSION BARRIER FOR IMPROVED INTERCONNECT ROBUSTNESS

Patent #:	6957345	Issue Dt:	10/18/2005	Application #:	09850917	Filing Dt:	05/07/2001
Publication #:	US20010056542	Pub Dt:	12/27/2001
Title:	TAMPER RESISTANT CARD ENCLOSURE WITH IMPROVED INTRUSION DETECTION CIRCUIT

Patent #:	6593227	Issue Dt:	07/15/2003	Application #:	09851199	Filing Dt:	05/08/2001
Title:	METHOD AND APPARATUS FOR PLANARIZING SURFACES OF SEMICONDUCTOR DEVICE CONDUCTIVE LAYERS

Patent #:	6709797	Issue Dt:	03/23/2004	Application #:	09851900	Filing Dt:	05/09/2001
Title:	METHOD AND APPARATUS FOR CONTROLLING FOCUS BASED ON A THICKNESS OF A LAYER OF PHOTORESIST

Patent #:	7065654	Issue Dt:	06/20/2006	Application #:	09852372	Filing Dt:	05/10/2001
Title:	SECURE EXECUTION BOX

Patent #:	6410410	Issue Dt:	06/25/2002	Application #:	09852535	Filing Dt:	05/10/2001
Publication #:	US20020061626	Pub Dt:	05/23/2002
Title:	METHOD OF FORMING LIGHTLY DOPED REGIONS IN A SEMICONDUCTOR DEVICE

Patent #:	6862641	Issue Dt:	03/01/2005	Application #:	09853234	Filing Dt:	05/11/2001
Title:	INTERRUPTABLE AND RE-ENTERABLE SYSTEM MANAGEMENT MODE PROGRAMMING CODE

Patent #:	6531710	Issue Dt:	03/11/2003	Application #:	09853342	Filing Dt:	05/10/2001
Title:	SOI FILM FORMED BY LASER ANNEALING

Patent #:	6821715	Issue Dt:	11/23/2004	Application #:	09853345	Filing Dt:	05/10/2001
Publication #:	US20020167764	Pub Dt:	11/14/2002
Title:	FULLY UNDERCUT RESIST SYSTEMS USING E-BEAM LITHOGRAPHY FOR THE FABRICATION OF HIGH RESOLUTION MR SENSORS

Patent #:	7216362	Issue Dt:	05/08/2007	Application #:	09853395	Filing Dt:	05/11/2001
Title:	ENHANCED SECURITY AND MANAGEABILITY USING SECURE STORAGE IN A PERSONAL COMPUTER SYSTEM

Patent #:	6832317	Issue Dt:	12/14/2004	Application #:	09853437	Filing Dt:	05/11/2001
Title:	PERSONAL COMPUTER SECURITY MECHANSIM

Patent #:	7043581	Issue Dt:	05/09/2006	Application #:	09853446	Filing Dt:	05/11/2001
Title:	RESOURSE SEQUESTER MECHANISM

Patent #:	6823451	Issue Dt:	11/23/2004	Application #:	09853447	Filing Dt:	05/11/2001
Title:	INTEGRATED CIRCUIT FOR SECURITY AND MANAGEABILITY

Patent #:	6968460	Issue Dt:	11/22/2005	Application #:	09854040	Filing Dt:	05/11/2001
Title:	CRYPTOGRAPHIC RANDOMNESS REGISTER FOR COMPUTER SYSTEM SECURITY

Patent #:	6469949	Issue Dt:	10/22/2002	Application #:	09854049	Filing Dt:	05/11/2001
Publication #:	US20020167855	Pub Dt:	11/14/2002
Title:	FUSE LATCH ARRAY SYSTEM FOR AN EMBEDDED DRAM HAVING A MICRO-CELL ARCHITECTURE

Patent #:	6854071	Issue Dt:	02/08/2005	Application #:	09854543	Filing Dt:	05/14/2001
Publication #:	US20020169996	Pub Dt:	11/14/2002
Title:	METHOD AND APPARATUS FOR PROVIDING WRITE RECOVERY OF FAULTY DATA IN A NON-REDUNDANT RAID SYSTEM

Patent #:	7035335	Issue Dt:	04/25/2006	Application #:	09854586	Filing Dt:	05/11/2001
Title:	TRANSPORT STREAM PARSER

Patent #:	6501675	Issue Dt:	12/31/2002	Application #:	09854987	Filing Dt:	05/14/2001
Publication #:	US20020176275	Pub Dt:	11/28/2002
Title:	ALTERNATING REFERENCE WORDLINE SCHEME FOR FAST DRAM

Patent #:	6941414	Issue Dt:	09/06/2005	Application #:	09855240	Filing Dt:	05/15/2001
Publication #:	US20020174291	Pub Dt:	11/21/2002
Title:	HIGH SPEED EMBEDDED DRAM WITH SRAM-LIKE INTERFACE

Patent #:	6823087	Issue Dt:	11/23/2004	Application #:	09855871	Filing Dt:	05/15/2001
Title:	PARALLEL EDGE FILTERS IN VIDEO CODEC

Patent #:	6726996	Issue Dt:	04/27/2004	Application #:	09858687	Filing Dt:	05/16/2001
Publication #:	US20020172811	Pub Dt:	11/21/2002
Title:	LAMINATED DIFFUSION BARRIER

Patent #:	6673287	Issue Dt:	01/06/2004	Application #:	09858919	Filing Dt:	05/16/2001
Publication #:	US20020172895	Pub Dt:	11/21/2002
Title:	VAPOR PHASE SURFACE MODIFICATION OF COMPOSITE SUBSTRATES TO FORM A MOLECULARLY THIN RELEASE LAYER

Patent #:	6808974	Issue Dt:	10/26/2004	Application #:	09859021	Filing Dt:	05/15/2001
Publication #:	US20020173105	Pub Dt:	11/21/2002
Title:	CMOS STRUCTURE WITH MAXIMIZED POLYSILICON GATE ACTIVATION AND A METHOD FOR SELECTIVELY MAXIMIZING DOPING ACTIVATION IN GATE, EXTENSION, AND SOURCE/DRAIN REGIONS

Patent #:	6519174	Issue Dt:	02/11/2003	Application #:	09859145	Filing Dt:	05/16/2001
Publication #:	US20020172067	Pub Dt:	11/21/2002
Title:	EARLY WRITE DRAM ARCHITECTURE WITH VERTICALLY FOLDED BITLINES

Patent #:	6563173	Issue Dt:	05/13/2003	Application #:	09859146	Filing Dt:	05/16/2001
Publication #:	US20010024863	Pub Dt:	09/27/2001
Title:	SILICON-ON-INSULATOR CHIP HAVING AN ISOLATION BARRIER FOR RELIABILITY

Patent #:	6493240	Issue Dt:	12/10/2002	Application #:	09859252	Filing Dt:	05/17/2001
Publication #:	US20010046129	Pub Dt:	11/29/2001
Title:	INTERPOSER FOR CONNECTING TWO SUBSTRATES AND RESULTING ASSEMBLY

Patent #:	6725337	Issue Dt:	04/20/2004	Application #:	09859290	Filing Dt:	05/16/2001
Title:	METHOD AND SYSTEM FOR SPECULATIVELY INVALIDATING LINES IN A CACHE

Patent #:	6399493	Issue Dt:	06/04/2002	Application #:	09860141	Filing Dt:	05/17/2001
Title:	METHOD OF SILICIDE FORMATION BY SILICON PRETREATMENT

Patent #:	6464563	Issue Dt:	10/15/2002	Application #:	09860226	Filing Dt:	05/18/2001
Title:	METHOD AND APPARATUS FOR DETECTING DISHING IN A POLISHED LAYER

Patent #:	6727873	Issue Dt:	04/27/2004	Application #:	09860264	Filing Dt:	05/18/2001
Publication #:	US20020171619	Pub Dt:	11/21/2002
Title:	REFLECTIVE ELECTROPHORETIC DISPLAY WITH STACKED COLOR CELLS

Patent #:	6680726	Issue Dt:	01/20/2004	Application #:	09860265	Filing Dt:	05/18/2001
Publication #:	US20020171620	Pub Dt:	11/21/2002
Title:	TRANSMISSIVE ELECTROPHORETIC DISPLAY WITH STACKED COLOR CELLS

Patent #:	6563736	Issue Dt:	05/13/2003	Application #:	09860736	Filing Dt:	05/18/2001
Publication #:	US20020171101	Pub Dt:	11/21/2002
Title:	FLASH MEMORY STRUCTURE HAVING DOUBLE CELLED ELEMENTS AND METHOD FOR FABRICATING THE SAME

Patent #:	6753252	Issue Dt:	06/22/2004	Application #:	09861253	Filing Dt:	05/18/2001
Publication #:	US20020173094	Pub Dt:	11/21/2002
Title:	CONTACT PLUG FORMATION FOR DEVICES WITH STACKED CAPACITORS

Patent #:	6486037	Issue Dt:	11/26/2002	Application #:	09861593	Filing Dt:	05/21/2001
Publication #:	US20010033002	Pub Dt:	10/25/2001
Title:	CONTROL OF BURIED OXIDE QUALITY IN LOW DOSE SIMOX

Patent #:	6602757	Issue Dt:	08/05/2003	Application #:	09861594	Filing Dt:	05/21/2001
Publication #:	US20020171106	Pub Dt:	11/21/2002
Title:	SELF-ADJUSTING THICKNESS UNIFORMITY IN SOI BY HIGH-TEMPERATURE OXIDATION OF SIMOX AND BONDED SOI

Patent #:	6541356	Issue Dt:	04/01/2003	Application #:	09861596	Filing Dt:	05/21/2001
Publication #:	US20020173123	Pub Dt:	11/21/2002
Title:	THE ULTIMATE SIMOX

Patent #:	6556477	Issue Dt:	04/29/2003	Application #:	09861788	Filing Dt:	05/21/2001
Publication #:	US20020172074	Pub Dt:	11/21/2002
Title:	INTEGRATED CHIP HAVING SRAM, DRAM AND FLASH MEMORY AND METHOD FOR FABRICATING THE SAME

Patent #:	6756646	Issue Dt:	06/29/2004	Application #:	09862372	Filing Dt:	05/22/2001
Publication #:	US20030190780	Pub Dt:	10/09/2003
Title:	OXYNITRIDE GATE DIELECTRIC AND METHOD OF FORMING

Patent #:	6549990	Issue Dt:	04/15/2003	Application #:	09862687	Filing Dt:	05/21/2001
Publication #:	US20010037434	Pub Dt:	11/01/2001
Title:	STORE TO LOAD FORWARDING USING A DEPENDENCY LINK FILE

Patent #:	6777733	Issue Dt:	08/17/2004	Application #:	09862827	Filing Dt:	05/22/2001
Publication #:	US20020055224	Pub Dt:	05/09/2002
Title:	METHOD FOR FORMING DUAL WORKFUNCTION HIGH-PERFORMANCE SUPPORT MOSFETS IN EDRAM ARRAYS

Patent #:	6677170	Issue Dt:	01/13/2004	Application #:	09863596	Filing Dt:	05/23/2001
Title:	METHOD FOR DETERMINING PROCESS LAYER THICKNESS USING SCATTEROMETRY MEASUREMENTS

Patent #:	6657716	Issue Dt:	12/02/2003	Application #:	09863598	Filing Dt:	05/23/2001
Title:	METHOD AND APPARATUS FOR DETECTING NECKING OVER FIELD/ACTIVE TRANSITIONS

Patent #:	6341079	Issue Dt:	01/22/2002	Application #:	09863848	Filing Dt:	05/23/2001
Title:	Content addressable memory device

Patent #:	6728916	Issue Dt:	04/27/2004	Application #:	09863952	Filing Dt:	05/23/2001
Publication #:	US20020178416	Pub Dt:	11/28/2002
Title:	HIERARCHICAL BUILT-IN SELF-TEST FOR SYSTEM-ON-CHIP DESIGN

Patent #:	6498383	Issue Dt:	12/24/2002	Application #:	09863980	Filing Dt:	05/23/2001
Publication #:	US20020177270	Pub Dt:	11/28/2002
Title:	OXYNITRIDE SHALLOW TRENCH ISOLATION AND METHOD OF FORMATION

Patent #:	6725121	Issue Dt:	04/20/2004	Application #:	09864692	Filing Dt:	05/24/2001
Title:	METHOD AND APPARATUS FOR USING A DYNAMIC CONTROL MODEL TO COMPENSATE FOR A PROCESS INTERRUPT

Patent #:	6645867	Issue Dt:	11/11/2003	Application #:	09864974	Filing Dt:	05/24/2001
Publication #:	US20020175146	Pub Dt:	11/28/2002
Title:	STRUCTURE AND METHOD TO PRESERVE STI DURING ETCHING

Patent #:	6479309	Issue Dt:	11/12/2002	Application #:	09865286	Filing Dt:	05/25/2001
Title:	METHOD AND APPARATUS FOR DETERMINING PROCESS LAYER CONFORMALITY

Patent #:	6597233	Issue Dt:	07/22/2003	Application #:	09865830	Filing Dt:	05/25/2001
Publication #:	US20020175717	Pub Dt:	11/28/2002
Title:	DIFFERENTIAL SCSI DRIVER RISE TIME AND AMPLITUDE CONTROL CIRCUIT

Patent #:	6472740	Issue Dt:	10/29/2002	Application #:	09867902	Filing Dt:	05/30/2001
Title:	SELF-SUPPORTING AIR BRIDGE INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS

Patent #:	6878608	Issue Dt:	04/12/2005	Application #:	09870531	Filing Dt:	05/31/2001
Publication #:	US20020180013	Pub Dt:	12/05/2002
Title:	METHOD OF MANUFACTURE OF SILICON BASED PACKAGE

Patent #:	7149854	Issue Dt:	12/12/2006	Application #:	09870889	Filing Dt:	05/30/2001
Publication #:	US20030041248	Pub Dt:	02/27/2003
Title:	EXTERNAL LOCKING MECHANISM FOR PERSONAL COMPUTER MEMORY LOCATIONS

Patent #:	7007300	Issue Dt:	02/28/2006	Application #:	09870890	Filing Dt:	05/30/2001
Title:	SECURE BOOTING OF A PERSONAL COMPUTER SYSTEM

Patent #:	6458610	Issue Dt:	10/01/2002	Application #:	09871015	Filing Dt:	05/31/2001
Title:	METHOD AND APPARATUS FOR OPTICAL FILM STACK FAULT DETECTION

Patent #:	7003676	Issue Dt:	02/21/2006	Application #:	09871084	Filing Dt:	05/30/2001
Title:	LOCKING MECHANISM OVERRIDE AND DISABLE FOR PERSONAL COMPUTER ROM ACCESS PROTECTION

Patent #:	6528851	Issue Dt:	03/04/2003	Application #:	09871191	Filing Dt:	05/31/2001
Title:	POST-SILICIDATION IMPLANT FOR INTRODUCING RECOMBINATION CENTER IN BODY OF SOI MOSFET

Patent #:	6489240	Issue Dt:	12/03/2002	Application #:	09871305	Filing Dt:	05/31/2001
Title:	METHOD FOR FORMING COPPER INTERCONNECTS

Patent #:	6526655	Issue Dt:	03/04/2003	Application #:	09871536	Filing Dt:	05/31/2001
Publication #:	US20010045012	Pub Dt:	11/29/2001
Title:	ANGLED FLYING LEAD WIRE BONDING PROCESS

Patent #:	6545226	Issue Dt:	04/08/2003	Application #:	09871556	Filing Dt:	05/31/2001
Publication #:	US20020179331	Pub Dt:	12/05/2002
Title:	PRINTED WIRING BOARD INTERPOSER SUB-ASSEMBLY

100

Patent #:	6746578	Issue Dt:	06/08/2004	Application #:	09871557	Filing Dt:	05/31/2001
Publication #:	US20020179450	Pub Dt:	12/05/2002
Title:	SELECTIVE SHIELD/MATERIAL FLOW MECHANISM

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

440 STONE BREAK ROAD EXTENSION

MALTA, NEW YORK 12020

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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