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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 33 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
7224063
Issue Dt:
05/29/2007
Application #:
09871883
Filing Dt:
06/01/2001
Publication #:
US20020182855
Pub Dt:
12/05/2002
Title:
DUAL-DAMASCENE METALLIZATION INTERCONNECTION
2
Patent #:
6718439
Issue Dt:
04/06/2004
Application #:
09872313
Filing Dt:
06/01/2001
Title:
CACHE MEMORY AND METHOD OF OPERATION
3
Patent #:
6528884
Issue Dt:
03/04/2003
Application #:
09872328
Filing Dt:
06/01/2001
Title:
CONFORMAL ATOMIC LINER LAYER IN AN INTERGRATED CIRCUIT INTERCONNECT
4
Patent #:
6465341
Issue Dt:
10/15/2002
Application #:
09872465
Filing Dt:
05/31/2001
Title:
MANUFACTURING METHOD FOR SEMICONDUCTOR INTERCONNECT BARRIER OF BORON SILICON NITRIDE
5
Patent #:
6482656
Issue Dt:
11/19/2002
Application #:
09873667
Filing Dt:
06/04/2001
Title:
METHOD OF ELECTROCHEMICAL FORMATION OF HIGH TC SUPERCONDUCTING DAMASCENE INTERCONNECT FOR INTEGRATED CIRCUIT
6
Patent #:
6888198
Issue Dt:
05/03/2005
Application #:
09873674
Filing Dt:
06/04/2001
Title:
STRADDLED GATE FDSOI DEVICE
7
Patent #:
6795882
Issue Dt:
09/21/2004
Application #:
09873735
Filing Dt:
06/04/2001
Title:
HIGH SPEED ASYNCHRONOUS BUS FOR AN INTEGRATED CIRCUIT
8
Patent #:
6528892
Issue Dt:
03/04/2003
Application #:
09874196
Filing Dt:
06/05/2001
Publication #:
US20020180061
Pub Dt:
12/05/2002
Title:
LAND GRID ARRAY STIFFENER USE WITH FLEXIBLE CHIP CARRIERS
9
Patent #:
6495443
Issue Dt:
12/17/2002
Application #:
09874513
Filing Dt:
06/05/2001
Title:
METHOD OF RE-WORKING COPPER DAMASCENE WAFERS
10
Patent #:
6417100
Issue Dt:
07/09/2002
Application #:
09874558
Filing Dt:
06/04/2001
Title:
ANNEALING AMBIENT IN INTEGRATED CIRCUIT INTERCONNECTS
11
Patent #:
6541860
Issue Dt:
04/01/2003
Application #:
09875457
Filing Dt:
06/05/2001
Title:
BARRIER-TO-SEED LAYER ALLOYING IN INTEGRATED CIRCUIT INTERCONNECTS
12
Patent #:
6592939
Issue Dt:
07/15/2003
Application #:
09875596
Filing Dt:
06/06/2001
Title:
SYSTEM FOR AND METHOD OF USING DEVELOPER AS A SOLVENT TO SPREAD PHOTORESIST FASTER AND REDUCE PHOTORESIST CONSUMPTION
13
Patent #:
6724225
Issue Dt:
04/20/2004
Application #:
09876631
Filing Dt:
06/07/2001
Publication #:
US20020186050
Pub Dt:
12/12/2002
Title:
LOGIC CIRCUIT FOR TRUE AND COMPLEMENT SIGNAL GENERATOR
14
Patent #:
8009584
Issue Dt:
08/30/2011
Application #:
09877120
Filing Dt:
06/11/2001
Title:
SYSTEM AND METHOD FOR IMPLEMENTING AN IRC ACROSS MULTIPLE NETWORK DEVICES
15
Patent #:
6433391
Issue Dt:
08/13/2002
Application #:
09877631
Filing Dt:
06/08/2001
Title:
BONDED SOI FOR FLOATING BODY AND METAL GETTERING CONTROL
16
Patent #:
6413869
Issue Dt:
07/02/2002
Application #:
09877688
Filing Dt:
06/08/2001
Title:
DIELECTRIC PROTECTED CHEMICAL-MECHANICAL POLISHING IN INTEGRATED CIRCUIT INTERCONNECTS
17
Patent #:
6858889
Issue Dt:
02/22/2005
Application #:
09878117
Filing Dt:
06/08/2001
Publication #:
US20020030216
Pub Dt:
03/14/2002
Title:
POLYSILICON CAPACITOR HAVING LARGE CAPACITANCE AND LOW RESISTANCE
18
Patent #:
6656313
Issue Dt:
12/02/2003
Application #:
09878474
Filing Dt:
06/11/2001
Publication #:
US20020195197
Pub Dt:
12/26/2002
Title:
STRUCTURE AND METHOD FOR IMPROVED ADHESION BETWEEN TWO POLYMER FILMS
19
Patent #:
6512684
Issue Dt:
01/28/2003
Application #:
09878525
Filing Dt:
06/11/2001
Publication #:
US20020196648
Pub Dt:
12/26/2002
Title:
CONTENT ADDRESSABLE MEMORY HAVING CASCADED SUB-ENTRY ARCHITECTURE
20
Patent #:
6492684
Issue Dt:
12/10/2002
Application #:
09878681
Filing Dt:
06/11/2001
Publication #:
US20020043686
Pub Dt:
04/18/2002
Title:
SILICON-ON-INSULATOR CHIP HAVING AN ISOLATION BARRIER FOR RELIABILITY
21
Patent #:
6686617
Issue Dt:
02/03/2004
Application #:
09878804
Filing Dt:
06/11/2001
Publication #:
US20010031535
Pub Dt:
10/18/2001
Title:
SEMICONDUCTOR CHIP HAVING BOTH COMPACT MEMORY AND HIGH PERFORMANCE LOGIC
22
Patent #:
6573539
Issue Dt:
06/03/2003
Application #:
09878930
Filing Dt:
06/12/2001
Publication #:
US20020020852
Pub Dt:
02/21/2002
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR WITH SILICON-GERMANIUM BASE
23
Patent #:
6891231
Issue Dt:
05/10/2005
Application #:
09879105
Filing Dt:
06/13/2001
Publication #:
US20020190302
Pub Dt:
12/19/2002
Title:
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) GATE STACK WITH HIGH DIELECTRIC CONSTANT GATE DIELECTRIC AND INTEGRATED DIFFUSION BARRIER
24
Patent #:
6529282
Issue Dt:
03/04/2003
Application #:
09879338
Filing Dt:
06/11/2001
Title:
METHOD OF CONTROLLING PHOTOLITHOGRAPHY PROCESSES BASED UPON SCATTEROMETRIC MEASUREMENTS OF PHOTORESIST THICKNESS, AND SYSTEM FOR ACCOMPLISHING SAME
25
Patent #:
6555479
Issue Dt:
04/29/2003
Application #:
09879376
Filing Dt:
06/11/2001
Title:
METHOD FOR FORMING OPENINGS FOR CONDUCTIVE INTERCONNECTS
26
Patent #:
6759282
Issue Dt:
07/06/2004
Application #:
09879530
Filing Dt:
06/12/2001
Publication #:
US20020185684
Pub Dt:
12/12/2002
Title:
METHOD AND STRUCTURE FOR BURIED CIRCUITS AND DEVICES
27
Patent #:
6635542
Issue Dt:
10/21/2003
Application #:
09879579
Filing Dt:
06/12/2001
Publication #:
US20020187612
Pub Dt:
12/12/2002
Title:
COMPACT BODY FOR SILICON-ON-INSULATOR TRANSISTORS REQUIRING NO ADDITIONAL LAYOUT AREA
28
Patent #:
6876557
Issue Dt:
04/05/2005
Application #:
09879653
Filing Dt:
06/12/2001
Publication #:
US20020188797
Pub Dt:
12/12/2002
Title:
UNIFIED SRAM CACHE SYSTEM FOR AN EMBEDDED DRAM SYSTEM HAVING A MICRO-CELL ARCHITECTURE
29
Patent #:
6717212
Issue Dt:
04/06/2004
Application #:
09879724
Filing Dt:
06/12/2001
Publication #:
US20020185685
Pub Dt:
12/12/2002
Title:
LEAKY, THERMALLY CONDUCTIVE INSULATOR MATERIAL (LTCIM) IN SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE
30
Patent #:
6534865
Issue Dt:
03/18/2003
Application #:
09880219
Filing Dt:
06/12/2001
Title:
METHOD OF ENHANCED FILL OF VIAS AND TRENCHES
31
Patent #:
6482755
Issue Dt:
11/19/2002
Application #:
09880513
Filing Dt:
06/12/2001
Title:
HDP DEPOSITION HILLOCK SUPPRESSION METHOD IN INTEGRATED CIRCUITS
32
Patent #:
6597463
Issue Dt:
07/22/2003
Application #:
09880591
Filing Dt:
06/13/2001
Title:
SYSTEM TO DETERMINE SUITABILITY OF SION ARC SURFACE FOR DUV RESIST PATTERNING
33
Patent #:
6538932
Issue Dt:
03/25/2003
Application #:
09880598
Filing Dt:
06/13/2001
Publication #:
US20020191448
Pub Dt:
12/19/2002
Title:
TIMING CIRCUIT AND METHOD FOR A COMPILABLE DRAM
34
Patent #:
6630362
Issue Dt:
10/07/2003
Application #:
09880990
Filing Dt:
06/13/2001
Title:
METHOD AND APPARATUS FOR PERFORMING TRENCH DEPTH ANALYSIS
35
Patent #:
6592747
Issue Dt:
07/15/2003
Application #:
09881817
Filing Dt:
06/18/2001
Publication #:
US20030000850
Pub Dt:
01/02/2003
Title:
METHOD OF CONTROLLING ADDITIVES IN COPPER PLATING BATHS
36
Patent #:
6492258
Issue Dt:
12/10/2002
Application #:
09881831
Filing Dt:
06/14/2001
Title:
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25MM AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY
37
Patent #:
6492075
Issue Dt:
12/10/2002
Application #:
09881993
Filing Dt:
06/15/2001
Title:
CHEMICAL TRIM PROCESS
38
Patent #:
7013422
Issue Dt:
03/14/2006
Application #:
09882006
Filing Dt:
06/15/2001
Publication #:
US20030070137
Pub Dt:
04/10/2003
Title:
NOISE REMOVAL IN MULTIBYTE TEXT ENCODINGS USING STATISTICAL MODELS
39
Patent #:
6440807
Issue Dt:
08/27/2002
Application #:
09882095
Filing Dt:
06/15/2001
Title:
SURFACE ENGINEERING TO PREVENT EPI GROWTH ON GATE POLY DURING SELECTIVE EPI PROCESSING
40
Patent #:
6511873
Issue Dt:
01/28/2003
Application #:
09882749
Filing Dt:
06/15/2001
Publication #:
US20020192881
Pub Dt:
12/19/2002
Title:
HIGH-DIELECTRIC CONSTANT INSULATORS FOR FEOL CAPACITORS
41
Patent #:
6662430
Issue Dt:
12/16/2003
Application #:
09883433
Filing Dt:
06/18/2001
Publication #:
US20010030628
Pub Dt:
10/18/2001
Title:
METHOD FOR FORMING AN ANTENNA AND A RADIO FREQUENCY TRANSPONDER
42
Patent #:
6509267
Issue Dt:
01/21/2003
Application #:
09884058
Filing Dt:
06/20/2001
Title:
METHOD OF FORMING LOW RESISTANCE BARRIER ON LOW K INTERCONNECT WITH ELECTROLESSLY PLATED COPPER SEED LAYER
43
Patent #:
6555461
Issue Dt:
04/29/2003
Application #:
09884059
Filing Dt:
06/20/2001
Title:
METHOD OF FORMING LOW RESISTANCE BARRIER ON LOW K INTERCONNECT
44
Patent #:
6834313
Issue Dt:
12/21/2004
Application #:
09884617
Filing Dt:
06/19/2001
Title:
PERFORMING A TWO-STEP READ ON A MAC REGISTER IN A HOME NETWORK AS AN ATOMIC READ
45
Patent #:
6537833
Issue Dt:
03/25/2003
Application #:
09885411
Filing Dt:
06/19/2001
Title:
METHOD AND APPARATUS FOR CHARACTERIZING AN INTERCONNECT STRUCTURE PROFILE USING SCATTEROMETRY MEASUREMENTS
46
Patent #:
6454899
Issue Dt:
09/24/2002
Application #:
09885455
Filing Dt:
06/19/2001
Title:
APPARATUS FOR FILLING TRENCHES
47
Patent #:
6489230
Issue Dt:
12/03/2002
Application #:
09886032
Filing Dt:
06/22/2001
Title:
INTEGRATION OF LOW-K SIOF AS INTER-LAYER DIELECTRIC
48
Patent #:
6960806
Issue Dt:
11/01/2005
Application #:
09886823
Filing Dt:
06/21/2001
Publication #:
US20020197781
Pub Dt:
12/26/2002
Title:
DOUBLE GATED VERTICAL TRANSISTOR WITH DIFFERENT FIRST AND SECOND GATE MATERIALS
49
Patent #:
6594024
Issue Dt:
07/15/2003
Application #:
09886863
Filing Dt:
06/21/2001
Title:
MONITOR CMP PROCESS USING SCATTEROMETRY
50
Patent #:
6495447
Issue Dt:
12/17/2002
Application #:
09888431
Filing Dt:
06/26/2001
Title:
USE OF HYDROGEN DOPING FOR PROTECTION OF LOW-K DIELECTRIC LAYERS
51
Patent #:
6511876
Issue Dt:
01/28/2003
Application #:
09888777
Filing Dt:
06/25/2001
Publication #:
US20020197789
Pub Dt:
12/26/2002
Title:
HIGH MOBILITY FETS USING AL2O3 AS A GATE OXIDE
52
Patent #:
6678570
Issue Dt:
01/13/2004
Application #:
09891898
Filing Dt:
06/26/2001
Title:
METHOD AND APPARATUS FOR DETERMINING OUTPUT CHARACTERISTICS USING TOOL STATE DATA
53
Patent #:
6542418
Issue Dt:
04/01/2003
Application #:
09892026
Filing Dt:
06/26/2001
Publication #:
US20020196677
Pub Dt:
12/26/2002
Title:
REDUNDANT MEMORY ARRAY HAVING DUAL-USE REPAIR ELEMENTS
54
Patent #:
6541865
Issue Dt:
04/01/2003
Application #:
09892234
Filing Dt:
06/26/2001
Publication #:
US20010040294
Pub Dt:
11/15/2001
Title:
POROUS DIELECTRIC MATERIAL AND ELECTRONIC DEVICES FABRICATED THEREWITH
55
Patent #:
6804799
Issue Dt:
10/12/2004
Application #:
09892328
Filing Dt:
06/26/2001
Publication #:
US20020199151
Pub Dt:
12/26/2002
Title:
USING TYPE BITS TO TRACK STORAGE OF ECC AND PREDECODE BITS IN A LEVEL TWO CACHE
56
Patent #:
6483169
Issue Dt:
11/19/2002
Application #:
09892777
Filing Dt:
06/28/2001
Title:
EXTRUDED HEAT SPREADER
57
Patent #:
6538320
Issue Dt:
03/25/2003
Application #:
09892778
Filing Dt:
06/28/2001
Title:
HEAT SPREADER HAVING HOLES FOR RIVET-LIKE ADHESIVE CONNECTIONS
58
Patent #:
6569694
Issue Dt:
05/27/2003
Application #:
09892799
Filing Dt:
06/28/2001
Title:
METHOD OF CHECKING BGA SUBSTRATE DESIGN
59
Patent #:
7072351
Issue Dt:
07/04/2006
Application #:
09893100
Filing Dt:
06/26/2001
Title:
COLLISION RECOVERY INTERFACE SUPPORT IN A HOME PHONELINE NETWORKING ALLIANCE MEDIA ACCESS CONTROLLER (HPNA MAC) OPERATING IN ACCORDANCE WITH AT LEAST TWO DIFFERENT DATA RATE STANDARDS
60
Patent #:
6545753
Issue Dt:
04/08/2003
Application #:
09893186
Filing Dt:
06/27/2001
Publication #:
US20030000644
Pub Dt:
01/02/2003
Title:
USING SCATTEROMETRY FOR ETCH END POINTS FOR DUAL DAMASCENE PROCESS
61
Patent #:
7078348
Issue Dt:
07/18/2006
Application #:
09893188
Filing Dt:
06/27/2001
Title:
DUAL LAYER PATTERNING SCHEME TO MAKE DUAL DAMASCENE
62
Patent #:
6905950
Issue Dt:
06/14/2005
Application #:
09893198
Filing Dt:
06/27/2001
Publication #:
US20030003701
Pub Dt:
01/02/2003
Title:
GROWING COPPER VIAS OR LINES WITHIN A PATTERNED RESIST USING A COPPER SEED LAYER
63
Patent #:
6617087
Issue Dt:
09/09/2003
Application #:
09893272
Filing Dt:
06/27/2001
Title:
USE OF SCATTEROMETRY TO MEASURE PATTERN ACCURACY
64
Patent #:
6561706
Issue Dt:
05/13/2003
Application #:
09893807
Filing Dt:
06/28/2001
Publication #:
US20030002878
Pub Dt:
01/02/2003
Title:
CRITICAL DIMENSION MONITORING FROM LATENT IMAGE
65
Patent #:
6452198
Issue Dt:
09/17/2002
Application #:
09893847
Filing Dt:
06/28/2001
Title:
MINIMIZED CONTAMINATION OF SEMICONDUCTOR WAFERS WITHIN AN IMPLANTATION SYSTEM
66
Patent #:
6614540
Issue Dt:
09/02/2003
Application #:
09894048
Filing Dt:
06/28/2001
Title:
METHOD AND APPARATUS FOR DETERMINING FEATURE CHARACTERISTICS USING SCATTEROMETRY
67
Patent #:
6541286
Issue Dt:
04/01/2003
Application #:
09894284
Filing Dt:
06/27/2001
Title:
IMAGING OF INTEGRATED CIRCUIT INTERCONNECTS
68
Patent #:
6531780
Issue Dt:
03/11/2003
Application #:
09894289
Filing Dt:
06/27/2001
Title:
VIA FORMATION IN INTEGRATED CIRCUIT INTERCONNECTS
69
Patent #:
6559042
Issue Dt:
05/06/2003
Application #:
09894337
Filing Dt:
06/28/2001
Publication #:
US20030003703
Pub Dt:
01/02/2003
Title:
PROCESS FOR FORMING FUSIBLE LINKS
70
Patent #:
6828162
Issue Dt:
12/07/2004
Application #:
09894434
Filing Dt:
06/28/2001
Title:
SYSTEM AND METHOD FOR ACTIVE CONTROL OF BPSG DEPOSITION
71
Patent #:
6630361
Issue Dt:
10/07/2003
Application #:
09894701
Filing Dt:
06/28/2001
Title:
USE OF SCATTEROMETRY FOR IN-SITU CONTROL OF GASEOUS PHASE CHEMICAL TRIM PROCESS
72
Patent #:
6423433
Issue Dt:
07/23/2002
Application #:
09895038
Filing Dt:
06/29/2001
Title:
METHOD OF FORMING CU-CA-O THIN FILMS ON CU SURFACES IN A CHEMICAL SOLUTION AND SEMICONDUCTOR DEVICE THEREBY FORMED
73
Patent #:
RE38282
Issue Dt:
10/21/2003
Application #:
09895624
Filing Dt:
06/28/2001
Title:
PROCESS FOR USING BILAYER PHOTORESIST
74
Patent #:
6656389
Issue Dt:
12/02/2003
Application #:
09895650
Filing Dt:
06/29/2001
Publication #:
US20030004066
Pub Dt:
01/02/2003
Title:
THERMAL PASTE FOR LOW TEMPERATURE APPLICATIONS
75
Patent #:
6620676
Issue Dt:
09/16/2003
Application #:
09895672
Filing Dt:
06/29/2001
Publication #:
US20030003653
Pub Dt:
01/02/2003
Title:
STRUCTURE AND METHODS FOR PROCESS INTEGRATION IN VERTICAL DRAM CELL FABRICATION
76
Patent #:
6475885
Issue Dt:
11/05/2002
Application #:
09896490
Filing Dt:
06/29/2001
Title:
SOURCE/DRAIN FORMATION WITH SUB-AMORPHIZING IMPLANTATION
77
Patent #:
6696216
Issue Dt:
02/24/2004
Application #:
09896538
Filing Dt:
06/29/2001
Publication #:
US20030008230
Pub Dt:
01/09/2003
Title:
THIOPHENE-CONTAINING PHOTO ACID GENERATORS FOR PHOTOLITHOGRAPHY
78
Patent #:
6549453
Issue Dt:
04/15/2003
Application #:
09896745
Filing Dt:
06/29/2001
Publication #:
US20030002329
Pub Dt:
01/02/2003
Title:
METHOD AND APPARATUS FOR WRITING OPERATION IN SRAM CELLS EMPLOYING PFETS PASS GATES
79
Patent #:
6441683
Issue Dt:
08/27/2002
Application #:
09897198
Filing Dt:
07/02/2001
Publication #:
US20020021165
Pub Dt:
02/21/2002
Title:
DEVICE AND METHOD FOR RECOVERING FREQUENCY REDUNDANT DATA IN A NETWORK COMMUNICATIONS RECEIVER
80
Patent #:
6707562
Issue Dt:
03/16/2004
Application #:
09897205
Filing Dt:
07/02/2001
Title:
METHOD OF USING SCATTEROMETRY MEASUREMENTS TO CONTROL PHOTORESIST ETCH PROCESS
81
Patent #:
7262864
Issue Dt:
08/28/2007
Application #:
09897573
Filing Dt:
07/02/2001
Title:
METHOD AND APPARATUS FOR DETERMINING GRID DIMENSIONS USING SCATTEROMETRY
82
Patent #:
6804014
Issue Dt:
10/12/2004
Application #:
09897576
Filing Dt:
07/02/2001
Title:
METHOD AND APPARATUS FOR DETERMINING CONTACT OPENING DIMENSIONS USING SCATTEROMETRY
83
Patent #:
6650423
Issue Dt:
11/18/2003
Application #:
09897623
Filing Dt:
07/02/2001
Title:
METHOD AND APPARATUS FOR DETERMINING COLUMN DIMENSIONS USING SCATTEROMETRY
84
Patent #:
6773939
Issue Dt:
08/10/2004
Application #:
09897624
Filing Dt:
07/02/2001
Title:
METHOD AND APPARATUS FOR DETERMINING CRITICAL DIMENSION VARIATION IN A LINE STRUCTURE
85
Patent #:
6444481
Issue Dt:
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Filing Dt:
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Title:
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Publication #:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Filing Dt:
07/10/2001
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Pub Dt:
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Title:
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Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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