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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 38 of 181
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1
Patent #:
6633040
Issue Dt:
10/14/2003
Application #:
10132896
Filing Dt:
04/25/2002
Title:
SOLENOID ELECTRON BEAM LENSES WITH HIGH DEMAGNIFICATION AND LOW ABERRATIONS
2
Patent #:
6763278
Issue Dt:
07/13/2004
Application #:
10133045
Filing Dt:
04/26/2002
Title:
OPERATING A PROCESSING TOOL IN A DEGRADED MODE UPON DETECTING A FAULT
3
Patent #:
7200779
Issue Dt:
04/03/2007
Application #:
10133097
Filing Dt:
04/26/2002
Title:
FAULT NOTIFICATION BASED ON A SEVERITY LEVEL
4
Patent #:
6922595
Issue Dt:
07/26/2005
Application #:
10134107
Filing Dt:
04/29/2002
Title:
SELECTING CONTROL ALGORITHMS BASED ON BUSINESS RULES
5
Patent #:
6751518
Issue Dt:
06/15/2004
Application #:
10134244
Filing Dt:
04/29/2002
Title:
DYNAMIC PROCESS STATE ADJUSTMENT OF A PROCESSING TOOL TO REDUCE NON-UNIFORMITY
6
Patent #:
6528409
Issue Dt:
03/04/2003
Application #:
10134883
Filing Dt:
04/29/2002
Title:
INTERCONNECT STRUCTURE FORMED IN POROUS DIELECTRIC MATERIAL WITH MINIMIZED DEGRADATION AND ELECTROMIGRATION
7
Patent #:
6624476
Issue Dt:
09/23/2003
Application #:
10134973
Filing Dt:
04/29/2002
Title:
SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE HAVING SELECTIVE DOPANT IMPLANT IN INSULATOR LAYER AND METHOD OF FABRICATING
8
Patent #:
6743666
Issue Dt:
06/01/2004
Application #:
10134981
Filing Dt:
04/29/2002
Title:
SELECTIVE THICKENING OF THE SOURCE-DRAIN AND GATE AREAS OF FIELD EFFECT TRANSISTORS
9
Patent #:
6674128
Issue Dt:
01/06/2004
Application #:
10135008
Filing Dt:
04/29/2002
Title:
SEMICONDUCTOR-ON-INSULATOR DEVICE WITH THERMOELECTRIC COOLER ON SURFACE
10
Patent #:
6900139
Issue Dt:
05/31/2005
Application #:
10135175
Filing Dt:
04/30/2002
Title:
METHOD FOR PHOTORESIST TRIM ENDPOINT DETECTION
11
Patent #:
7009618
Issue Dt:
03/07/2006
Application #:
10135461
Filing Dt:
04/30/2002
Title:
INTEGRATED I/O REMAPPING MECHANISM
12
Patent #:
7028166
Issue Dt:
04/11/2006
Application #:
10135496
Filing Dt:
04/30/2002
Publication #:
US20040177236
Pub Dt:
09/09/2004
Title:
SYSTEM AND METHOD FOR LINKING SPECULATIVE RESULTS OF LOAD OPERATIONS TO REGISTER VALUES
13
Patent #:
6845442
Issue Dt:
01/18/2005
Application #:
10135497
Filing Dt:
04/30/2002
Title:
SYSTEM AND METHOD OF USING SPECULATIVE OPERAND SOURCES IN ORDER TO SPECULATIVELY BYPASS LOAD-STORE OPERATIONS
14
Patent #:
6639800
Issue Dt:
10/28/2003
Application #:
10135502
Filing Dt:
04/30/2002
Title:
HEAT SINK SUBASSEMBLY
15
Patent #:
6806182
Issue Dt:
10/19/2004
Application #:
10137274
Filing Dt:
05/01/2002
Publication #:
US20030207559
Pub Dt:
11/06/2003
Title:
METHOD FOR ELIMINATING VIA RESISTANCE SHIFT IN ORGANIC ILD
16
Patent #:
6653048
Issue Dt:
11/25/2003
Application #:
10138498
Filing Dt:
05/06/2002
Publication #:
US20020127490
Pub Dt:
09/12/2002
Title:
HIGH SILICON CONTENT MONOMERS AND POLYMERS SUITABLE FOR 193 NM BILAYER RESISTS
17
Patent #:
6701206
Issue Dt:
03/02/2004
Application #:
10138712
Filing Dt:
05/03/2002
Title:
METHOD AND SYSTEM FOR CONTROLLING A PROCESS TOOL
18
Patent #:
6627944
Issue Dt:
09/30/2003
Application #:
10139331
Filing Dt:
05/07/2002
Publication #:
US20020163030
Pub Dt:
11/07/2002
Title:
FLOATING GATE MEMORY DEVICE USING COMPOSITE MOLECULAR MATERIAL
19
Patent #:
6809955
Issue Dt:
10/26/2004
Application #:
10139746
Filing Dt:
05/07/2002
Publication #:
US20020163829
Pub Dt:
11/07/2002
Title:
ADDRESABLE AND ELECTRICALLY REVERSIBLE MEMORY SWITCH
20
Patent #:
6826740
Issue Dt:
11/30/2004
Application #:
10140517
Filing Dt:
05/07/2002
Publication #:
US20030212976
Pub Dt:
11/13/2003
Title:
AUTOMATED BUFFER INSERTION INCORPORATING CONGESTION RELIEF FOR USE IN CONNECTION WITH PHYSICAL DESIGN OF INTEGRATED CIRCUIT
21
Patent #:
6797641
Issue Dt:
09/28/2004
Application #:
10141279
Filing Dt:
05/08/2002
Publication #:
US20020125503
Pub Dt:
09/12/2002
Title:
GATE OXIDE STABILIZATION BY MEANS OF GERMANIUM COMPONENTS IN GATE CONDUCTOR
22
Patent #:
6782177
Issue Dt:
08/24/2004
Application #:
10141637
Filing Dt:
05/07/2002
Publication #:
US20020178760
Pub Dt:
12/05/2002
Title:
METHOD FOR MANUFACTURING AN OPTICAL DEVICE WITH A DEFINED TOTAL DEVICE STRESS
23
Patent #:
6768857
Issue Dt:
07/27/2004
Application #:
10141665
Filing Dt:
05/07/2002
Publication #:
US20020194876
Pub Dt:
12/26/2002
Title:
METHOD FOR MANUFACTURING AN OPTICAL DEVICE WITH A DEFINED TOTAL DEVICE STRESS
24
Patent #:
6576382
Issue Dt:
06/10/2003
Application #:
10142018
Filing Dt:
05/09/2002
Publication #:
US20020177072
Pub Dt:
11/28/2002
Title:
COMPOSITION FOR PHOTOIMAGING
25
Patent #:
7426559
Issue Dt:
09/16/2008
Application #:
10143317
Filing Dt:
05/09/2002
Publication #:
US20030212789
Pub Dt:
11/13/2003
Title:
METHOD FOR SEQUENTIAL COORDINATION OF EXTERNAL DATABASE APPLICATION EVENTS WITH ASYNCHRONOUS INTERNAL DATABASE EVENTS
26
Patent #:
6706566
Issue Dt:
03/16/2004
Application #:
10144402
Filing Dt:
05/13/2002
Publication #:
US20020173083
Pub Dt:
11/21/2002
Title:
METHODOLOGY FOR ELECTRICALLY INDUCED SELECTIVE BREAKDOWN OF NANOTUBES
27
Patent #:
6767584
Issue Dt:
07/27/2004
Application #:
10144510
Filing Dt:
05/13/2002
Publication #:
US20030211365
Pub Dt:
11/13/2003
Title:
DISK SUBSTRATE WITH MONOSIZED MICROBUMPS
28
Patent #:
6737725
Issue Dt:
05/18/2004
Application #:
10144574
Filing Dt:
05/13/2002
Publication #:
US20020127844
Pub Dt:
09/12/2002
Title:
MULTILEVEL INTERCONNECT STRUCTURE CONTAINING AIR GAPS AND METHOD FOR MAKING
29
Patent #:
7216284
Issue Dt:
05/08/2007
Application #:
10145018
Filing Dt:
05/15/2002
Publication #:
US20030217321
Pub Dt:
11/20/2003
Title:
CONTENT ADDRESSABLE MEMORY HAVING REDUCED POWER CONSUMPTION
30
Patent #:
6541321
Issue Dt:
04/01/2003
Application #:
10145519
Filing Dt:
05/14/2002
Title:
METHOD OF MAKING TRANSISTORS WITH GATE INSULATION LAYERS OF DIFFERING THICKNESS
31
Patent #:
6548361
Issue Dt:
04/15/2003
Application #:
10145915
Filing Dt:
05/15/2002
Title:
SOI MOSFET AND METHOD OF FABRICATION
32
Patent #:
6815340
Issue Dt:
11/09/2004
Application #:
10145928
Filing Dt:
05/15/2002
Title:
METHOD OF FORMING AN ELECTROLESS NUCLEATION LAYER ON A VIA BOTTOM
33
Patent #:
6642066
Issue Dt:
11/04/2003
Application #:
10145942
Filing Dt:
05/15/2002
Title:
INTEGRATED PROCESS FOR DEPOSITING LAYER OF HIGH-K DIELECTRIC WITH IN-SITU CONTROL OF K VALUE AND THICKNESS OF HIGH-K DIELECTRIC LAYER
34
Patent #:
6861349
Issue Dt:
03/01/2005
Application #:
10145944
Filing Dt:
05/15/2002
Title:
METHOD OF FORMING AN ADHESION LAYER WITH AN ELEMENT REACTIVE WITH A BARRIER LAYER
35
Patent #:
6706614
Issue Dt:
03/16/2004
Application #:
10145953
Filing Dt:
05/15/2002
Title:
SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING PARTIAL HETERO SOURCE/DRAIN JUNCTIONS FABRICATED WITH HIGH ENERGY GERMANIUM IMPLANTATION
36
Patent #:
6784101
Issue Dt:
08/31/2004
Application #:
10146029
Filing Dt:
05/16/2002
Title:
FORMATION OF HIGH-K GATE DIELECTRIC LAYERS FOR MOS DEVICES FABRICATED ON STRAINED LATTICE SEMICONDUCTOR SUBSTRATES WITH MINIMIZED STRESS RELAXATION
37
Patent #:
6618281
Issue Dt:
09/09/2003
Application #:
10146154
Filing Dt:
05/15/2002
Title:
CONTENT ADDRESSABLE MEMORY (CAM) WITH ERROR CHECKING AND CORRECTION (ECC) CAPABILITY
38
Patent #:
7353159
Issue Dt:
04/01/2008
Application #:
10146331
Filing Dt:
05/15/2002
Publication #:
US20020173943
Pub Dt:
11/21/2002
Title:
METHOD FOR PARALLEL SIMULATION ON A SINGLE MICROPROCESSOR USING META-MODELS
39
Patent #:
6727539
Issue Dt:
04/27/2004
Application #:
10147150
Filing Dt:
05/16/2002
Publication #:
US20030003651
Pub Dt:
01/02/2003
Title:
EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT
40
Patent #:
6682992
Issue Dt:
01/27/2004
Application #:
10147270
Filing Dt:
05/15/2002
Publication #:
US20030216013
Pub Dt:
11/20/2003
Title:
METHOD OF CONTROLLING GRAIN SIZE IN A POLYSILICON LAYER AND IN SEMICONDUCTOR DEVICES HAVING POLYSILICONE STRUCTURES
41
Patent #:
6787436
Issue Dt:
09/07/2004
Application #:
10147382
Filing Dt:
05/15/2002
Title:
SILICIDE-SILICON CONTACTS FOR REDUCTION OF MOSFET SOURCE-DRAIN RESISTANCES
42
Patent #:
6800494
Issue Dt:
10/05/2004
Application #:
10150320
Filing Dt:
05/17/2002
Title:
METHOD AND APPARATUS FOR CONTROLLING COPPER BARRIER/SEED DEPOSITION PROCESSES
43
Patent #:
7568228
Issue Dt:
07/28/2009
Application #:
10150783
Filing Dt:
05/17/2002
Publication #:
US20020194469
Pub Dt:
12/19/2002
Title:
INTRUSION DETECTION IN DATA PROCESSING SYSTEMS
44
Patent #:
6621114
Issue Dt:
09/16/2003
Application #:
10151269
Filing Dt:
05/20/2002
Title:
MOS TRANSISTORS WITH HIGH-K DIELECTRIC GATE INSULATOR FOR REDUCING REMOTE SCATTERING
45
Patent #:
6764929
Issue Dt:
07/20/2004
Application #:
10151625
Filing Dt:
05/16/2002
Title:
METHOD AND SYSTEM FOR PROVIDING A CONTACT HOLE IN A SEMICONDUCTOR DEVICE
46
Patent #:
6689671
Issue Dt:
02/10/2004
Application #:
10151946
Filing Dt:
05/22/2002
Title:
LOW TEMPERATURE SOLID-PHASE EPITAXY FABRICATION PROCESS FOR MOS DEVICES BUILT ON STRAINED SEMICONDUCTOR SUBSTRATE
47
Patent #:
7043318
Issue Dt:
05/09/2006
Application #:
10154092
Filing Dt:
05/23/2002
Title:
LOT START AGENT THAT DETERMINES QUANTITY AND TIMING FOR LOT STARTS
48
Patent #:
6787376
Issue Dt:
09/07/2004
Application #:
10154274
Filing Dt:
05/22/2002
Title:
CREATING A PROCESS RECIPE BASED ON A DESIRED RESULT
49
Patent #:
6879512
Issue Dt:
04/12/2005
Application #:
10154796
Filing Dt:
05/24/2002
Publication #:
US20030218903
Pub Dt:
11/27/2003
Title:
NONVOLATILE MEMORY DEVICE UTILIZING SPIN-VALVE-TYPE DESIGNS AND CURRENT PULSES
50
Patent #:
6621165
Issue Dt:
09/16/2003
Application #:
10154871
Filing Dt:
05/23/2002
Title:
SEMICONDUCTOR DEVICE FABRICATED BY REDUCING CARBON, SULPHUR, AND OXYGEN IMPURITIES IN A CALCIUM-DOPED COPPER SURFACE
51
Patent #:
6613643
Issue Dt:
09/02/2003
Application #:
10155044
Filing Dt:
05/24/2002
Title:
STRUCTURE , AND A METHOD OF REALIZING, FOR EFFICIENT HEAT REMOVAL ON SOI
52
Patent #:
6653737
Issue Dt:
11/25/2003
Application #:
10159181
Filing Dt:
05/31/2002
Publication #:
US20020142581
Pub Dt:
10/03/2002
Title:
INTERCONNECTION STRUCTURE AND METHOD FOR FABRICATING SAME
53
Patent #:
6835973
Issue Dt:
12/28/2004
Application #:
10159573
Filing Dt:
05/31/2002
Publication #:
US20020182837
Pub Dt:
12/05/2002
Title:
ANTIFUSE FOR USE WITH LOW KAPPA DIELECTRIC FOAM INSULATORS
54
Patent #:
6806026
Issue Dt:
10/19/2004
Application #:
10159635
Filing Dt:
05/31/2002
Publication #:
US20030224283
Pub Dt:
12/04/2003
Title:
PHOTORESIST COMPOSITION
55
Patent #:
6826733
Issue Dt:
11/30/2004
Application #:
10159921
Filing Dt:
05/30/2002
Publication #:
US20030226122
Pub Dt:
12/04/2003
Title:
PARAMETER VARIATION TOLERANT METHOD FOR CIRCUIT DESIGN OPTIMIZATION
56
Patent #:
6662347
Issue Dt:
12/09/2003
Application #:
10160300
Filing Dt:
05/30/2002
Publication #:
US20030097645
Pub Dt:
05/22/2003
Title:
ON-CHIP DIAGNOSTIC SYSTEM, INTEGRATED CIRCUIT AND METHOD
57
Patent #:
6972576
Issue Dt:
12/06/2005
Application #:
10160334
Filing Dt:
05/31/2002
Title:
ELECTRICAL CRITICAL DIMENSION MEASUREMENT AND DEFECT DETECTION FOR RETICLE FABRICATION
58
Patent #:
6652665
Issue Dt:
11/25/2003
Application #:
10160627
Filing Dt:
05/31/2002
Title:
METHOD OF REMOVING SILICONE POLYMER DEPOSITS FROM ELECTRONIC COMPONENTS
59
Patent #:
6766258
Issue Dt:
07/20/2004
Application #:
10160933
Filing Dt:
05/31/2002
Title:
METHOD AND APPARATUS FOR DYNAMICALLY ENABLING TRACE DATA COLLECTION
60
Patent #:
6622061
Issue Dt:
09/16/2003
Application #:
10160963
Filing Dt:
05/31/2002
Title:
METHOD AND APPARATUS FOR RUN-TO-RUN CONTROLLING OF OVERLAY REGISTRATION
61
Patent #:
7451324
Issue Dt:
11/11/2008
Application #:
10161500
Filing Dt:
05/31/2002
Publication #:
US20030226022
Pub Dt:
12/04/2003
Title:
SECURE EXECUTION MODE EXCEPTIONS
62
Patent #:
6884702
Issue Dt:
04/26/2005
Application #:
10162299
Filing Dt:
06/04/2002
Publication #:
US20030223258
Pub Dt:
12/04/2003
Title:
METHOD OF MAKING AN SOI SEMICONDUCTOR DEVICE HAVING ENHANCED, SELF-ALIGNED DIELECTRIC REGIONS IN THE BULK SILICON SUBSTRATE
63
Patent #:
6771087
Issue Dt:
08/03/2004
Application #:
10162421
Filing Dt:
06/04/2002
Title:
SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUIT MODULES
64
Patent #:
7197102
Issue Dt:
03/27/2007
Application #:
10163340
Filing Dt:
06/07/2002
Publication #:
US20030227989
Pub Dt:
12/11/2003
Title:
METHOD AND APPARATUS FOR CLOCK-AND-DATA RECOVERY USING A SECONDARY DELAY-LOCKED LOOP
65
Patent #:
6835656
Issue Dt:
12/28/2004
Application #:
10163459
Filing Dt:
06/07/2002
Title:
METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN A SEMICONDUCTOR WAFER WITH A DEPOSITED SILICON LAYER AND IN-SITU ANNEAL TO REDUCE SILICON CONSUMPTION DURING SALICIDATION
66
Patent #:
6589858
Issue Dt:
07/08/2003
Application #:
10163534
Filing Dt:
06/07/2002
Title:
METAL GATE STACK WITH ETCH ENDPOINT TRACER LAYER
67
Patent #:
6790750
Issue Dt:
09/14/2004
Application #:
10163676
Filing Dt:
06/06/2002
Title:
SEMICONDUCTOR-ON-INSULATOR BODY-SOURCE CONTACT AND METHOD
68
Patent #:
6657276
Issue Dt:
12/02/2003
Application #:
10163925
Filing Dt:
06/06/2002
Title:
SHALLOW TRENCH ISOLATION (STI) REGION WITH HIGH-K LINER AND METHOD OF FORMATION
69
Patent #:
7051250
Issue Dt:
05/23/2006
Application #:
10164091
Filing Dt:
06/06/2002
Title:
ROUTING WORKPIECES BASED UPON DETECTING A FAULT
70
Patent #:
6732007
Issue Dt:
05/04/2004
Application #:
10164133
Filing Dt:
06/05/2002
Title:
METHOD AND APPARATUS FOR IMPLEMENTING DYNAMIC QUALIFICATION RECIPES
71
Patent #:
6824932
Issue Dt:
11/30/2004
Application #:
10164242
Filing Dt:
06/05/2002
Publication #:
US20030228526
Pub Dt:
12/11/2003
Title:
SELF-ALIGNED ALTERNATING PHASE SHIFT MASK PATTERNING PROCESS
72
Patent #:
6809027
Issue Dt:
10/26/2004
Application #:
10165264
Filing Dt:
06/06/2002
Publication #:
US20030228752
Pub Dt:
12/11/2003
Title:
SELF-ALIGNED BORDERLESS CONTACTS
73
Patent #:
6789099
Issue Dt:
09/07/2004
Application #:
10167170
Filing Dt:
06/10/2002
Publication #:
US20040073592
Pub Dt:
04/15/2004
Title:
SENSE-AMP BASED ADDER WITH SOURCE FOLLOWER EVALUATION TREE
74
Patent #:
7129142
Issue Dt:
10/31/2006
Application #:
10167184
Filing Dt:
06/11/2002
Publication #:
US20030228722
Pub Dt:
12/11/2003
Title:
METHOD OF FORMING DOPED REGIONS IN THE BULK SUBSTRATE OF AN SOI SUBSTRATE TO CONTROL THE OPERATIONAL CHARACTERISTICS OF TRANSISTORS FORMED THEREABOVE, AND AN INTEGRATED CIRCUIT DEVICE COMPRISING SAME
75
Patent #:
6559017
Issue Dt:
05/06/2003
Application #:
10170909
Filing Dt:
06/13/2002
Title:
METHOD OF USING AMORPHOUS CARBON AS SPACER MATERIAL IN A DISPOSABLE SPACER PROCESS
76
Patent #:
7887711
Issue Dt:
02/15/2011
Application #:
10170914
Filing Dt:
06/13/2002
Publication #:
US20030230549
Pub Dt:
12/18/2003
Title:
METHOD FOR ETCHING CHEMICALLY INERT METAL OXIDES
77
Patent #:
7169711
Issue Dt:
01/30/2007
Application #:
10170984
Filing Dt:
06/13/2002
Title:
METHOD OF USING CARBON SPACERS FOR CRITICAL DIMENSION (CD) REDUCTION
78
Patent #:
6777298
Issue Dt:
08/17/2004
Application #:
10172649
Filing Dt:
06/14/2002
Publication #:
US20030232464
Pub Dt:
12/18/2003
Title:
ELEVATED SOURCE DRAIN DISPOSABLE SPACER CMOS
79
Patent #:
6809043
Issue Dt:
10/26/2004
Application #:
10173611
Filing Dt:
06/19/2002
Title:
MULTI-STAGE, LOW DEPOSITION RATE PECVD OXIDE
80
Patent #:
6686232
Issue Dt:
02/03/2004
Application #:
10173717
Filing Dt:
06/19/2002
Title:
ULTRA LOW DEPOSITION RATE PECVD SILICON NITRIDE
81
Patent #:
6764908
Issue Dt:
07/20/2004
Application #:
10173770
Filing Dt:
06/19/2002
Title:
NARROW WIDTH CMOS DEVICES FABRICATED ON STRAINED LATTICE SEMICONDUCTOR SUBSTRATES WITH MAXIMIZED NMOS AND PMOS DRIVE CURRENTS
82
Patent #:
6833587
Issue Dt:
12/21/2004
Application #:
10174328
Filing Dt:
06/18/2002
Title:
HEAT REMOVAL IN SOI DEVICES USING A BURIED OXIDE LAYER/CONDUCTIVE LAYER COMBINATION
83
Patent #:
6764774
Issue Dt:
07/20/2004
Application #:
10174748
Filing Dt:
06/19/2002
Publication #:
US20030235710
Pub Dt:
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Title:
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Pub Dt:
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Title:
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06/21/2002
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Pub Dt:
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Title:
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11/25/2003
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06/24/2002
Title:
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Pub Dt:
01/29/2004
Title:
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Title:
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05/09/2006
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06/27/2002
Title:
PIGGYBACKING OF ECC CORRECTIONS BEHIND LOADS
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04/17/2003
Title:
SELF-ALIGNED CORROSION STOP FOR COPPER C4 AND WIREBOND
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02/10/2004
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Pub Dt:
12/25/2003
Title:
METHOD AND DEVICE USING SILICIDE CONTACTS FOR SEMICONDUCTOR PROCESSING
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06/27/2002
Title:
BATCH/LOT ORGANIZATION BASED ON QUALITY CHARACTERISTICS
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12/31/2002
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06/28/2002
Title:
METHOD OF FORMING SUB-LITHOGRAPHIC SPACES BETWEEN POLYSILICON LINES
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Title:
GAIN CONTROL IN WIRELESS LAN DEVICES
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SWITCHED COMBINING ANTENNA DIVERSITY TECHNIQUE
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06/27/2002
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05/15/2003
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6628163
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6664154
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10185320
Filing Dt:
06/28/2002
Title:
METHOD OF USING AMORPHOUS CARBON FILM AS A SACRIFICIAL LAYER IN REPLACEMENT GATE INTEGRATION PROCESSES
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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