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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 41 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
6924157
Issue Dt:
08/02/2005
Application #:
10277003
Filing Dt:
10/21/2002
Title:
REAL TIME PARTICLE MONITOR INSIDE OF PLASMA CHAMBER DURING RESIST STRIP PROCESSSING
2
Patent #:
6912438
Issue Dt:
06/28/2005
Application #:
10277016
Filing Dt:
10/21/2002
Publication #:
US20040078108
Pub Dt:
04/22/2004
Title:
USING SCATTEROMETRY TO OBTAIN MEASUREMENTS OF IN CIRCUIT STRUCTURES
3
Patent #:
6953697
Issue Dt:
10/11/2005
Application #:
10277357
Filing Dt:
10/22/2002
Title:
ADVANCED PROCESS CONTROL OF THE MANUFACTURE OF AN OXIDE-NITRIDE-OXIDE STACK OF A MEMORY DEVICE, AND SYSTEM FOR ACCOMPLISHING SAME
4
Patent #:
6702648
Issue Dt:
03/09/2004
Application #:
10277559
Filing Dt:
10/22/2002
Title:
USE OF SCATTEROMETRY/REFLECTOMETRY TO MEASURE THIN FILM DELAMINATION DURING CMP
5
Patent #:
6770501
Issue Dt:
08/03/2004
Application #:
10277835
Filing Dt:
10/23/2002
Publication #:
US20030102529
Pub Dt:
06/05/2003
Title:
DEUTERIUM RESERVOIRS AND INGRESS PATHS
6
Patent #:
6661069
Issue Dt:
12/09/2003
Application #:
10278211
Filing Dt:
10/22/2002
Title:
MICRO-ELECTROMECHANICAL VARACTOR WITH ENHANCED TUNING RANGE
7
Patent #:
6787852
Issue Dt:
09/07/2004
Application #:
10278420
Filing Dt:
10/23/2002
Title:
SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE HAVING SOURCE/DRAIN SILICON-GERMANIUM REGIONS
8
Patent #:
6812143
Issue Dt:
11/02/2004
Application #:
10279057
Filing Dt:
10/24/2002
Publication #:
US20030203617
Pub Dt:
10/30/2003
Title:
PROCESS OF FORMING COPPER STRUCTURES
9
Patent #:
7023093
Issue Dt:
04/04/2006
Application #:
10280283
Filing Dt:
10/24/2002
Publication #:
US20040087135
Pub Dt:
05/06/2004
Title:
VERY LOW EFFECTIVE DIELECTRIC CONSTANT INTERCONNECT STRUCTURES AND METHODS FOR FABRICATING THE SAME
10
Patent #:
6835983
Issue Dt:
12/28/2004
Application #:
10280661
Filing Dt:
10/25/2002
Publication #:
US20040079993
Pub Dt:
04/29/2004
Title:
SILICON-ON-INSULATOR (SOI) INTEGRATED CIRCUIT (IC) CHIP WITH THE SILICON LAYERS CONSISTING OF REGIONS OF DIFFERENT THICKNESS
11
Patent #:
6734259
Issue Dt:
05/11/2004
Application #:
10281038
Filing Dt:
10/24/2002
Publication #:
US20040082730
Pub Dt:
04/29/2004
Title:
RESIN COMPOSITION WITH A POLYMERIZING AGENT AND METHOD OF MANUFACTURING PREPREG AND OTHER LAMINATE STRUCTURES THEREFROM
12
Patent #:
6881594
Issue Dt:
04/19/2005
Application #:
10281666
Filing Dt:
10/28/2002
Title:
METHOD OF USING SCATTEROMETRY FOR ANALYSIS OF ELECTROMIGRATION, AND STRUCTURES FOR PERFORMING SAME
13
Patent #:
6927080
Issue Dt:
08/09/2005
Application #:
10281760
Filing Dt:
10/28/2002
Title:
STRUCTURES FOR ANALYZING ELECTROMIGRATION, AND METHODS OF USING SAME
14
Patent #:
6657223
Issue Dt:
12/02/2003
Application #:
10282538
Filing Dt:
10/29/2002
Title:
STRAINED SILICON MOSFET HAVING SILICON SOURCE/DRAIN REGIONS AND METHOD FOR ITS FABRICATION
15
Patent #:
6770559
Issue Dt:
08/03/2004
Application #:
10282558
Filing Dt:
10/29/2002
Title:
METHOD OF FORMING WIRING BY IMPLANTATION OF SEED LAYER MATERIAL
16
Patent #:
6703648
Issue Dt:
03/09/2004
Application #:
10282559
Filing Dt:
10/29/2002
Title:
STRAINED SILICON PMOS HAVING SILICON GERMANIUM SOURCE/DRAIN EXTENSIONS AND METHOD FOR ITS FABRICATION
17
Patent #:
6867428
Issue Dt:
03/15/2005
Application #:
10282712
Filing Dt:
10/29/2002
Title:
STRAINED SILICON NMOS HAVING SILICON SOURCE/DRAIN EXTENSIONS AND METHOD FOR ITS FABRICATION
18
Patent #:
7032146
Issue Dt:
04/18/2006
Application #:
10282825
Filing Dt:
10/29/2002
Publication #:
US20040083413
Pub Dt:
04/29/2004
Title:
BOUNDARY SCAN APPARATUS AND INTERCONNECT TEST METHOD
19
Patent #:
6864163
Issue Dt:
03/08/2005
Application #:
10283523
Filing Dt:
10/30/2002
Title:
FABRICATION OF DUAL WORK-FUNCTION METAL GATE STRUCTURE FOR COMPLEMENTARY FIELD EFFECT TRANSISTORS
20
Patent #:
6944725
Issue Dt:
09/13/2005
Application #:
10283733
Filing Dt:
10/30/2002
Publication #:
US20030204686
Pub Dt:
10/30/2003
Title:
RECIPROCALLY ADJUSTABLE DUAL QUEUE MECHANISM
21
Patent #:
7127446
Issue Dt:
10/24/2006
Application #:
10283901
Filing Dt:
10/30/2002
Title:
FILE SYSTEM BASED TASK QUEUE MANAGEMENT
22
Patent #:
6781141
Issue Dt:
08/24/2004
Application #:
10284509
Filing Dt:
10/29/2002
Publication #:
US20040079895
Pub Dt:
04/29/2004
Title:
METHOD AND STRUCTURE FOR DETECTION AND MEASUREMENT OF ELECTRICAL AND MECHANICAL RESONANCE ASSOCIATED WITH AN E-BEAM LITHOGRAPHY TOOL
23
Patent #:
6785615
Issue Dt:
08/31/2004
Application #:
10284510
Filing Dt:
10/29/2002
Publication #:
US20040079896
Pub Dt:
04/29/2004
Title:
METHOD AND STRUCTURE FOR DETECTION OF ELECTROMECHANICAL PROBLEMS USING VARIANCE STATISTICS IN AN E-BEAM LITHOGRAPHY DEVICE
24
Patent #:
6800864
Issue Dt:
10/05/2004
Application #:
10284511
Filing Dt:
10/29/2002
Publication #:
US20040079901
Pub Dt:
04/29/2004
Title:
METHOD AND STRUCTURE FOR REDUCING EFFECTS OF NOISE AND RESONANCE ASSOCIATED WITH AN E-BEAM LITHOGRAPHY TOOL
25
Patent #:
6834211
Issue Dt:
12/21/2004
Application #:
10284639
Filing Dt:
10/31/2002
Title:
ADJUSTING A TRACE DATA RATE BASED UPON A TOOL STATE
26
Patent #:
7246290
Issue Dt:
07/17/2007
Application #:
10284640
Filing Dt:
10/31/2002
Title:
DETERMINING THE HEALTH OF A DESIRED NODE IN A MULTI-LEVEL SYSTEM
27
Patent #:
7190713
Issue Dt:
03/13/2007
Application #:
10284641
Filing Dt:
10/31/2002
Publication #:
US20030223479
Pub Dt:
12/04/2003
Title:
PHASE ERROR CORRECTION USING DESPREAD SIGNALS
28
Patent #:
7003271
Issue Dt:
02/21/2006
Application #:
10284642
Filing Dt:
10/31/2002
Publication #:
US20030203727
Pub Dt:
10/30/2003
Title:
DIRECT CONVERSION RECEIVER HAVING A GAIN-SETTING DEPENDENT FILTER PARAMETER
29
Patent #:
7313099
Issue Dt:
12/25/2007
Application #:
10284644
Filing Dt:
10/31/2002
Publication #:
US20040001466
Pub Dt:
01/01/2004
Title:
PHASE SYSTEM ROTATION FOR POWER ESTIMATION
30
Patent #:
7184507
Issue Dt:
02/27/2007
Application #:
10284646
Filing Dt:
10/31/2002
Publication #:
US20030223524
Pub Dt:
12/04/2003
Title:
RESIDUAL PHASE ERROR CORRECTION
31
Patent #:
6833307
Issue Dt:
12/21/2004
Application #:
10284675
Filing Dt:
10/30/2002
Title:
SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
32
Patent #:
7337091
Issue Dt:
02/26/2008
Application #:
10284841
Filing Dt:
10/31/2002
Title:
METHOD AND APPARATUS FOR COORDINATING FAULT DETECTION SETTINGS AND PROCESS CONTROL CHANGES
33
Patent #:
6660543
Issue Dt:
12/09/2003
Application #:
10284996
Filing Dt:
10/31/2002
Title:
METHOD OF MEASURING IMPLANT PROFILES USING SCATTEROMETRIC TECHNIQUES WHEREIN DISPERSION COEFFICIENTS ARE VARIED BASED UPON DEPTH
34
Patent #:
6656825
Issue Dt:
12/02/2003
Application #:
10285004
Filing Dt:
10/31/2002
Publication #:
US20030201490
Pub Dt:
10/30/2003
Title:
SEMICONDUCTOR DEVICE HAVING AN IMPROVED LOCAL INTERCONNECT STRUCTURE AND A METHOD FOR FORMING SUCH A DEVICE
35
Patent #:
6933158
Issue Dt:
08/23/2005
Application #:
10285041
Filing Dt:
10/31/2002
Title:
METHOD OF MONITORING ANNEAL PROCESSES USING SCATTEROMETRY, AND SYSTEM FOR PERFORMING SAME
36
Patent #:
6638607
Issue Dt:
10/28/2003
Application #:
10285162
Filing Dt:
10/30/2002
Title:
METHOD AND STRUCTURE FOR PRODUCING Z-AXIS INTERCONNECTION ASSEMBLY OF PRINTED WIRING BOARD ELEMENTS
37
Patent #:
7148079
Issue Dt:
12/12/2006
Application #:
10285860
Filing Dt:
11/01/2002
Title:
DIAMOND LIKE CARBON SILICON ON INSULATOR SUBSTRATES AND METHODS OF FABRICATION THEREOF
38
Patent #:
7016994
Issue Dt:
03/21/2006
Application #:
10285935
Filing Dt:
11/01/2002
Publication #:
US20040024949
Pub Dt:
02/05/2004
Title:
RETRY MECHANISM FOR BLOCKING INTERFACES
39
Patent #:
NONE
Issue Dt:
Application #:
10285939
Filing Dt:
11/01/2002
Publication #:
US20040024948
Pub Dt:
02/05/2004
Title:
Response reordering mechanism
40
Patent #:
6875622
Issue Dt:
04/05/2005
Application #:
10286012
Filing Dt:
11/01/2002
Title:
METHOD AND APPARATUS FOR DETERMINING ELECTROMAGNETIC PROPERTIES OF A PROCESS LAYER USING SCATTEROMETRY MEASUREMENTS
41
Patent #:
6597596
Issue Dt:
07/22/2003
Application #:
10286206
Filing Dt:
11/01/2002
Publication #:
US20030065880
Pub Dt:
04/03/2003
Title:
CONTENT ADDRESSABLE MEMORY HAVING CASCADED SUB-ENTRY ARCHITECTURE
42
Patent #:
7031793
Issue Dt:
04/18/2006
Application #:
10286305
Filing Dt:
11/01/2002
Title:
CONFLICT RESOLUTION AMONG MULTIPLE CONTROLLERS
43
Patent #:
6654660
Issue Dt:
11/25/2003
Application #:
10287292
Filing Dt:
11/04/2002
Title:
CONTROLLING THERMAL EXPANSION OF MASK SUBSTRATES BY SCATTEROMETRY
44
Patent #:
6641899
Issue Dt:
11/04/2003
Application #:
10287935
Filing Dt:
11/05/2002
Title:
NONLITHOGRAPHIC METHOD TO PRODUCE MASKS BY SELECTIVE REACTION, ARTICLES PRODUCED, AND COMPOSITION FOR SAME
45
Patent #:
6624075
Issue Dt:
09/23/2003
Application #:
10288862
Filing Dt:
11/05/2002
Title:
METHOD OF REDUCING ELECTROMIGRATION IN A COPPER LINE BY ZINC-DOPING OF A COPPER SURFACE FROM AN ELECTROPLATED COPPER-ZINC ALLOY THIN FILM AND A SEMICONDUCTOR DEVICE THEREBY FORMED
46
Patent #:
7880305
Issue Dt:
02/01/2011
Application #:
10290049
Filing Dt:
11/07/2002
Publication #:
US20040089948
Pub Dt:
05/13/2004
Title:
TECHNOLOGY FOR FABRICATION OF PACKAGING INTERFACE SUBSTRATE WAFERS WITH FULLY METALLIZED VIAS THROUGH THE SUBSTRATE WAFER
47
Patent #:
6707095
Issue Dt:
03/16/2004
Application #:
10290400
Filing Dt:
11/06/2002
Title:
STRUCTURE AND METHOD FOR IMPROVED VERTICAL MOSFET DRAM CELL-TO-CELL ISOLATION
48
Patent #:
6783862
Issue Dt:
08/31/2004
Application #:
10290682
Filing Dt:
11/08/2002
Publication #:
US20030114013
Pub Dt:
06/19/2003
Title:
TOUGHNESS, ADHESION AND SMOOTH METAL LINES OF POROUS LOW K DIELECTRIC INTERCONNECT STRUCTURES
49
Patent #:
6660634
Issue Dt:
12/09/2003
Application #:
10291612
Filing Dt:
11/12/2002
Title:
METHOD OF FORMING RELIABLE CAPPED COPPER INTERCONNECTS
50
Patent #:
6833299
Issue Dt:
12/21/2004
Application #:
10292204
Filing Dt:
11/12/2002
Publication #:
US20030092239
Pub Dt:
05/15/2003
Title:
METHOD OF FABRICATING A STACKED POLY-POLY AND MOS CAPACITOR USING A SIGE INTEGRATION SCHEME
51
Patent #:
6716742
Issue Dt:
04/06/2004
Application #:
10292205
Filing Dt:
11/12/2002
Publication #:
US20030075803
Pub Dt:
04/24/2003
Title:
LOW-K INTERCONNECT STRUCTURE COMPRISED OF A MULTILAYER OF SPIN-ON POROUS DIELECTRICS
52
Patent #:
6819160
Issue Dt:
11/16/2004
Application #:
10293340
Filing Dt:
11/13/2002
Publication #:
US20040090261
Pub Dt:
05/13/2004
Title:
SELF-TIMED AND SELF-TESTED FUSE BLOW
53
Patent #:
6917108
Issue Dt:
07/12/2005
Application #:
10294139
Filing Dt:
11/14/2002
Publication #:
US20040094839
Pub Dt:
05/20/2004
Title:
RELIABLE LOW-K INTERCONNECT STRUCTURE WITH HYBRID DIELECTRIC
54
Patent #:
6776885
Issue Dt:
08/17/2004
Application #:
10294199
Filing Dt:
11/14/2002
Publication #:
US20040094403
Pub Dt:
05/20/2004
Title:
INTEGRATED PLATING AND PLANARIZATION APPARATUS HAVING A VARIABLE-DIAMETER COUNTERELECTRODE
55
Patent #:
6773570
Issue Dt:
08/10/2004
Application #:
10294200
Filing Dt:
11/14/2002
Publication #:
US20040094427
Pub Dt:
05/20/2004
Title:
INTEGRATED PLATING AND PLANARIZATION PROCESS AND APPARATUS THEREFOR
56
Patent #:
7168224
Issue Dt:
01/30/2007
Application #:
10295595
Filing Dt:
11/15/2002
Publication #:
US20040045866
Pub Dt:
03/11/2004
Title:
METHOD OF MAKING A PACKAGED RADIATION SENSITIVE RESIST FILM-COATED WORKPIECE
57
Patent #:
6771534
Issue Dt:
08/03/2004
Application #:
10295678
Filing Dt:
11/15/2002
Publication #:
US20040095801
Pub Dt:
05/20/2004
Title:
THERMALLY-ASSISTED MAGNETIC WRITING USING AN OXIDE LAYER AND CURRENT-INDUCED HEATING
58
Patent #:
6822260
Issue Dt:
11/23/2004
Application #:
10298664
Filing Dt:
11/19/2002
Title:
LINEWIDTH MEASUREMENT STRUCTURE WITH EMBEDDED SCATTEROMETRY STRUCTURE
59
Patent #:
6812506
Issue Dt:
11/02/2004
Application #:
10298923
Filing Dt:
11/19/2002
Title:
POLYSILICON LINEWIDTH MEASUREMENT STRUCTURE WITH EMBEDDED TRANSISTOR
60
Patent #:
6924810
Issue Dt:
08/02/2005
Application #:
10299367
Filing Dt:
11/18/2002
Title:
HIERARCHICAL TEXTURE CACHE
61
Patent #:
6812077
Issue Dt:
11/02/2004
Application #:
10299433
Filing Dt:
11/19/2002
Title:
METHOD FOR PATTERNING NARROW GATE LINES
62
Patent #:
6855649
Issue Dt:
02/15/2005
Application #:
10299880
Filing Dt:
11/19/2002
Publication #:
US20030218189
Pub Dt:
11/27/2003
Title:
RELAXED SIGE LAYERS ON SI OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING
63
Patent #:
6846734
Issue Dt:
01/25/2005
Application #:
10300165
Filing Dt:
11/20/2002
Publication #:
US20040094804
Pub Dt:
05/20/2004
Title:
METHOD AND PROCESS TO MAKE MULTIPLE-THRESHOLD METAL GATES CMOS TECHNOLOGY
64
Patent #:
6946373
Issue Dt:
09/20/2005
Application #:
10300189
Filing Dt:
11/20/2002
Publication #:
US20040094763
Pub Dt:
05/20/2004
Title:
RELAXED, LOW-DEFECT SGOI FOR STRAINED SI CMOS APPLICATIONS
65
Patent #:
6800503
Issue Dt:
10/05/2004
Application #:
10300520
Filing Dt:
11/20/2002
Publication #:
US20040097003
Pub Dt:
05/20/2004
Title:
MEMS ENCAPSULATED STRUCTURE AND METHOD OF MAKING SAME
66
Patent #:
6963080
Issue Dt:
11/08/2005
Application #:
10300630
Filing Dt:
11/20/2002
Publication #:
US20030136964
Pub Dt:
07/24/2003
Title:
THIN FILM TRANSISTORS USING SOLUTION PROCESSED PENTACENE PRECURSOR AS ORGANIC SEMICONDUCTOR
67
Patent #:
7125989
Issue Dt:
10/24/2006
Application #:
10300645
Filing Dt:
11/20/2002
Publication #:
US20030144562
Pub Dt:
07/31/2003
Title:
HETERO DIELS-ALDER ADDUCTS OF PENTACENE AS SOLUBLE PRECURSORS OF PENTACENE
68
Patent #:
6686637
Issue Dt:
02/03/2004
Application #:
10301436
Filing Dt:
11/21/2002
Title:
GATE STRUCTURE WITH INDEPENDENTLY TAILORED VERTICAL DOPING PROFILE
69
Patent #:
6842048
Issue Dt:
01/11/2005
Application #:
10301617
Filing Dt:
11/22/2002
Publication #:
US20040100306
Pub Dt:
05/27/2004
Title:
TWO TRANSISTOR NOR DEVICE
70
Patent #:
6790790
Issue Dt:
09/14/2004
Application #:
10302227
Filing Dt:
11/22/2002
Title:
HIGH MODULUS FILLER FOR LOW K MATERIALS
71
Patent #:
6872663
Issue Dt:
03/29/2005
Application #:
10302235
Filing Dt:
11/22/2002
Title:
METHOD FOR REWORKING A MULTI-LAYER PHOTORESIST FOLLOWING AN UNDERLAYER DEVELOPMENT
72
Patent #:
6790683
Issue Dt:
09/14/2004
Application #:
10303224
Filing Dt:
11/25/2002
Title:
METHODS OF CONTROLLING WET CHEMICAL PROCESSES IN FORMING METAL SILICIDE REGIONS, AND SYSTEM FOR PERFORMING SAME
73
Patent #:
6761812
Issue Dt:
07/13/2004
Application #:
10303276
Filing Dt:
11/25/2002
Publication #:
US20040000485
Pub Dt:
01/01/2004
Title:
APPARATUS AND METHOD FOR ELECTROCHEMICAL METAL DEPOSITION
74
Patent #:
6730445
Issue Dt:
05/04/2004
Application #:
10303341
Filing Dt:
11/22/2002
Publication #:
US20030194569
Pub Dt:
10/16/2003
Title:
ATTENUATED EMBEDDED PHASE SHIFT PHOTOMASK BLANKS
75
Patent #:
6803668
Issue Dt:
10/12/2004
Application #:
10303501
Filing Dt:
11/22/2002
Publication #:
US20040099963
Pub Dt:
05/27/2004
Title:
PROCESS-ROBUST ALIGNMENT MARK STRUCTURE FOR SEMICONDUCTOR WAFERS
76
Patent #:
6709982
Issue Dt:
03/23/2004
Application #:
10303702
Filing Dt:
11/26/2002
Title:
DOUBLE SPACER FINFET FORMATION
77
Patent #:
6815235
Issue Dt:
11/09/2004
Application #:
10304114
Filing Dt:
11/25/2002
Title:
METHODS OF CONTROLLING FORMATION OF METAL SILICIDE REGIONS, AND SYSTEM FOR PERFORMING SAME
78
Patent #:
6838695
Issue Dt:
01/04/2005
Application #:
10304163
Filing Dt:
11/25/2002
Publication #:
US20040099860
Pub Dt:
05/27/2004
Title:
CMOS DEVICE STRUCTURE WITH IMPROVED PFET GATE ELECTRODE
79
Patent #:
7017094
Issue Dt:
03/21/2006
Application #:
10304246
Filing Dt:
11/26/2002
Publication #:
US20040103355
Pub Dt:
05/27/2004
Title:
PERFORMANCE BUILT-IN SELF TEST SYSTEM FOR A DEVICE AND A METHOD OF USE
80
Patent #:
6795193
Issue Dt:
09/21/2004
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Pub Dt:
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Title:
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Pub Dt:
05/27/2004
Title:
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Filing Dt:
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Publication #:
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Title:
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Title:
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Pub Dt:
05/27/2004
Title:
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10/10/2006
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Pub Dt:
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Title:
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Title:
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Title:
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FERRULE-LESS OPTICAL FIBER APPARATUS FOR OPTICAL BACKPLANE CONNECTOR SYSTEMS
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Title:
METHOD FOR OPTIMIZING A VLSI FLOOR PLANNER USING A PATH BASED HYPER-EDGE REPRESENTATION
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Title:
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DAMASCENE GATE PROCESS WITH SACRIFICIAL OXIDE IN SEMICONDUCTOR DEVICES
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100
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07/19/2005
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12/09/2002
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Pub Dt:
06/10/2004
Title:
SYSTEM AND METHOD OF TRANSFER PRINTING AN ORGANIC SEMICONDUCTOR
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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