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03/17/2009
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10829741
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04/21/2004
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11/17/2005
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07/26/2005
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10830006
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04/23/2004
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10/07/2004
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NARROW FIN FINFET
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11/22/2005
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10832215
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04/26/2004
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10/07/2004
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DIVOT REDUCTION IN SIMOX LAYERS
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08/01/2006
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10832217
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04/26/2004
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11/18/2004
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HIGH SPEED COMPOSITE P-CHANNEL SI/SIGE HETEROSTRUCTURE FOR FIELD EFFECT DEVICES
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07/06/2010
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10832658
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04/27/2004
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10/27/2005
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ASYNCHRONOUS PACKET BASED DUAL PORT LINK LIST HEADER AND DATA CREDIT MANAGEMENT STRUCTURE
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04/11/2006
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10833651
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04/28/2004
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11/03/2005
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DEVICE AND METHOD FOR DETERMINING AN ILLUMINATION INTENSITY PROFILE OF AN ILLUMINATOR FOR A LITHOGRAPHY SYSTEM
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06/27/2006
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10835182
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04/29/2004
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12/02/2004
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METHOD OF FORMING A METAL SILICIDE
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10/05/2010
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10835411
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04/29/2004
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03/03/2005
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METHOD OF FORMING A TEOS CAP LAYER AT LOW TEMPERATURE AND REDUCED DEPOSITION RATE
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05/02/2006
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10835814
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04/30/2004
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11/03/2005
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NON-PLANARIZED, SELF-ALIGNED, NON-VOLATILE PHASE-CHANGE MEMORY ARRAY AND METHOD OF FORMATION
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06/12/2007
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10837395
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04/30/2004
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SPEED VERIFICATION OF AN EMBEDDED PROCESSOR IN A PROGRAMMABLE LOGIC DEVICE
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07/04/2006
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10838229
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05/05/2004
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Title:
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METHOD OF MAKING A TEST STRUCTURE FOR GATE-BODY CURRENT AND DIRECT EXTRACTION OF PHYSICAL GATE LENGTH USING CONVENTIONAL CMOS
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11/11/2008
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10838378
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05/04/2004
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11/10/2005
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SELF-ALIGNED METAL TO FORM CONTACTS TO GE CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY
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01/02/2007
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10838830
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05/04/2004
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USE OF NON-LITHOGRAPHIC SHRINK TECHNIQUES FOR FABRICATION/MAKING OF IMPRINTS MASKS
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07/17/2007
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10839072
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05/05/2004
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Title:
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EFFICIENT MEMORY CHECK ARCHITECTURE AND METHOD
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12/19/2006
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10839437
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05/04/2004
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Title:
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CONVERSION OF TRANSITION METAL TO SILICIDE THROUGH BACK END PROCESSING IN INTEGRATED CIRCUIT TECHNOLOGY
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08/28/2007
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10839474
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05/05/2004
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11/10/2005
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Title:
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SYSTEM AND METHOD FOR VALIDATING A MEMORY FILE THAT LINKS SPECULATIVE RESULTS OF LOAD OPERATIONS TO REGISTER VALUES
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03/10/2009
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10839872
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05/06/2004
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11/17/2005
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NETWORK INTERFACE WITH SECURITY ASSOCIATION DATA PREFETCH FOR HIGH SPEED OFFLOADED SECURITY PROCESSING
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09/16/2008
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10842085
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05/10/2004
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11/10/2005
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DESIGN VERIFICATION OF HIGHLY OPTIMIZED SYNCHRONOUS PIPELINES VIA RANDOM SIMULATION DRIVEN BY CRITICAL RESOURCE SCHEDULING
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03/21/2006
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10842297
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05/10/2004
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07/28/2005
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METHOD FOR INITIALIZING A SYSTEM INCLUDING A HOST AND PLURALITY OF MEMORY MODULES CONNECTED VIA A SERIAL MEMORY INTERCONNECT
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05/25/2010
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10843255
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05/10/2004
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MEDIA ACCELERATOR INTERFACE API
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04/14/2009
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10843607
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05/11/2004
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11/17/2005
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Title:
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POST INITIAL MICROCODE LOAD CO-SIMULATION METHOD, SYSTEM, AND PROGRAM PRODUCT
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10/07/2008
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10844093
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05/12/2004
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11/17/2005
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Title:
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ASYNCHRONOUS HIDDEN MARKOV MODEL METHOD AND SYSTEM
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10/31/2006
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10844794
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05/13/2004
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11/17/2005
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Title:
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FAST AND ACCURATE OPTICAL PROXIMITY CORRECTION ENGINE FOR INCORPORATING LONG RANGE FLARE EFFECTS
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07/25/2006
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10849459
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05/19/2004
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11/25/2004
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Title:
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SELF-ALIGNED CORROSION STOP FOR COPPER C4 AND WIREBOND
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07/07/2009
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10849847
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05/21/2004
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METHOD OF FORMING SEMICONDUCTOR DEVICES BY MICROWAVE CURING OF LOW-K DIELECTRIC FILMS
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11/14/2006
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10851821
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05/21/2004
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11/24/2005
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POLYCRYSTALLINE SIGE JUNCTIONS FOR ADVANCED DEVICES
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10/03/2006
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10852142
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05/25/2004
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10/28/2004
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Title:
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METHOD TO SELECTIVELY CAP INTERCONNECTS WITH INDIUM OR TIN BRONZES AND/OR OXIDES THEREOF AND THE INTERCONNECT SO CAPPED
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05/06/2008
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10853041
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05/25/2004
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12/15/2005
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MODELING LANGUAGE AND METHOD FOR ADDRESS TRANSLATION DESIGN MECHANISMS IN TEST GENERATION
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03/11/2008
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10855047
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05/27/2004
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12/01/2005
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METHOD FOR DEFERRED DATA COLLECTION IN A CLOCK RUNNING SYSTEM
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03/25/2008
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10855915
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05/27/2004
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12/23/2004
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HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT
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06/14/2005
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10856503
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05/28/2004
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11/11/2004
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METHOD TO FABRICATE HIGH-PERFORMANCE NPN TRANSISTORS IN A BICMOS PROCESS
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03/07/2006
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10856547
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05/28/2004
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12/01/2005
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INDIRECT SWITCHING AND SENSING OF PHASE CHANGE MEMORY CELLS
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11/11/2008
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10858605
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06/02/2004
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FEEDBACK CONTROL OF IMPRINT MASK FEATURE PROFILE USING SCATTEROMETRY AND SPACER ETCHBACK
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11/14/2006
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10858739
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06/01/2004
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WAFER LEVEL GLOBAL BITMAP CHARACTERIZATION IN INTEGRATED CIRCUIT TECHNOLOGY DEVELOPMENT
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05/29/2007
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10858759
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06/02/2004
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IN-SITU DEFECT MONITOR AND CONTROL SYSTEM FOR IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY
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04/29/2008
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10858791
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06/02/2004
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Title:
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METHOD FOR OPTIMIZING LOOP CONTROL OF MICROCODED INSTRUCTIONS
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NONE
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10859031
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06/01/2004
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Pub Dt:
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03/31/2005
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Title:
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Storage tank for process liquids with a reduced amount of bubbles
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09/09/2008
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10859276
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06/02/2004
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Title:
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OPTICAL PROXIMITY CORRECTION (OPC) TECHNIQUE TO COMPENSATE FOR FLARE
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08/14/2007
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10859673
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06/03/2004
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Title:
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METHODS AND FIXTURE FOR COUPLING A LID TO A SUPPORT SUBSTRATE
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02/20/2007
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10860100
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06/04/2004
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Title:
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METHOD FOR OFFSETTING A SILICIDE PROCESS FROM A GATE ELECTRODE OF A SEMICONDUCTOR DEVICE
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Issue Dt:
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02/08/2011
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10860966
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06/04/2004
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Title:
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MUTI-GIGABIT PER SECOND CONCURRENT ENCRYPTION IN BLOCK CIPHER MODES
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02/13/2007
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10862518
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06/07/2004
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05/05/2005
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TECHNIQUE FOR FORMING TRANSISTORS HAVING RAISED DRAIN AND SOURCE REGIONS WITH DIFFERENT HEIGHTS
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05/31/2005
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10865138
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06/10/2004
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Pub Dt:
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11/11/2004
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Title:
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DIFFUSED EXTRINSIC BASE AND METHOD FOR FABRICATION
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09/05/2006
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10865836
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06/14/2004
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Title:
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BACK TO BACK CONNECTION OF PCI HOST BRIDGES ON A SINGLE PCI BUS
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Issue Dt:
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10/24/2006
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10865920
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06/14/2004
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12/15/2005
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MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER
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08/05/2008
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10867094
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06/14/2004
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Pub Dt:
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12/15/2005
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Title:
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MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT
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08/05/2008
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10867302
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06/14/2004
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Pub Dt:
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12/02/2004
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Title:
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SYSTEM FOR FACILITATING COVERAGE FEEDBACK TESTCASE GENERATION REPRODUCIBILITY
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09/04/2007
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10867772
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06/16/2004
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01/06/2005
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METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN
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05/24/2005
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10868723
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06/15/2004
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Pub Dt:
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11/18/2004
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Title:
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METHOD FOR CONTROLLING LOCAL CURRENT TO ACHIEVE UNIFORM PLATING THICKNESS
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12/05/2006
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10868791
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06/17/2004
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11/25/2004
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METHOD FOR MANUFACTURING DEVICE SUBSTRATE WITH METAL BACK-GATE AND STRUCTURE FORMED THEREBY
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06/20/2006
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10869624
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06/16/2004
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Pub Dt:
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11/11/2004
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Title:
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IMPLANTED ASYMMETRIC DOPED POLYSILICON GATE FINFET
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10/09/2007
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10869658
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06/16/2004
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Pub Dt:
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12/22/2005
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HIGH-TEMPERATURE STABLE GATE STRUCTURE WITH METALLIC ELECTRODE
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Issue Dt:
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01/08/2013
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10870318
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06/17/2004
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NETWORK INTERFACE SYSTEMS AND METHODS FOR OFFLOADING SEGMENTATION AND/OR CHECKSUMMING WITH SECURITY PROCESSING
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06/20/2006
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10872173
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06/18/2004
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Pub Dt:
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11/18/2004
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MOS ANTIFUSE WITH LOW POST-PROGRAM RESISTANCE
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12/05/2006
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10873069
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06/21/2004
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Title:
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ELECTRICALLY ADDRESSABLE MEMORY SWITCH
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Issue Dt:
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05/29/2007
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10873240
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06/23/2004
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Title:
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MULTI-CHANNEL TRANSISTOR WITH TUNABLE HOT CARRIER EFFECT
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10/03/2006
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10873733
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06/22/2004
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Pub Dt:
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12/22/2005
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Title:
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METHOD OF FORMING METAL/HIGH-K GATE STACKS WITH HIGH MOBILITY
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06/10/2008
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10874498
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06/23/2004
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Title:
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POST FABRICATION CD MODIFICATION ON IMPRINT LITHOGRAPHY MASK
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Issue Dt:
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05/20/2008
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10874499
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06/23/2004
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Title:
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TOPOGRAPHY COMPENSATION OF IMPRINT LITHOGRAPHY PATTERNING
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03/06/2007
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10875727
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06/24/2004
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Publication #:
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Pub Dt:
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12/29/2005
| | | | |
Title:
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COMPRESSIVE SIGE <110> GROWTH AND STRUCTURE OF MOSFET DEVICES
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Issue Dt:
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04/12/2005
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10879538
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06/29/2004
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Publication #:
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Pub Dt:
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01/06/2005
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Title:
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CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEFECTS
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Issue Dt:
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11/29/2005
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Application #:
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10879833
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Filing Dt:
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06/29/2004
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Title:
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DUAL GATED FINFET GAIN CELL
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Patent #:
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Issue Dt:
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09/16/2008
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Application #:
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10880853
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
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01/05/2006
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Title:
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METHOD, SYSTEM AND PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING INCOMPLETELY SPECIFIED CONFIGURATION ENTITIES
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10881449
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
Title:
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MOSFET DEVICE WITH IN-SITU DOPED, RAISED SOURCE AND DRAIN STRUCTURES
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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10881853
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Filing Dt:
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06/29/2004
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Publication #:
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Pub Dt:
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12/29/2005
| | | | |
Title:
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WEAR GAUGE AND METHOD OF USE
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Patent #:
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Issue Dt:
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12/27/2011
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Application #:
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10881932
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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METHOD OF IMPROVING THE WAFER-TO-WAFER THICKNESS UNIFORMITY OF SILICON NITRIDE LAYERS
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10883392
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Filing Dt:
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07/01/2004
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Publication #:
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Pub Dt:
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01/05/2006
| | | | |
Title:
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APPARATUS AND METHODS FOR MICROCHANNEL COOLING OF SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGES
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10883434
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Filing Dt:
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07/01/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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SI/SIGE OPTOELECTRONIC INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10883887
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Filing Dt:
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07/02/2004
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Publication #:
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Pub Dt:
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01/05/2006
| | | | |
Title:
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STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED P+ SILICON GERMANIUM LAYER
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Patent #:
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Issue Dt:
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04/27/2010
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Application #:
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10885462
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Filing Dt:
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07/06/2004
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Publication #:
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Pub Dt:
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01/12/2006
| | | | |
Title:
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METHODS FOR THE FORMATION OF FULLY SILICIDED METAL GATES
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10886341
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Filing Dt:
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07/07/2004
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Title:
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BUILT-IN SELF TIMING TEST METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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11/02/2010
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Application #:
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10887069
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Filing Dt:
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07/08/2004
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Title:
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DATA PROCESSOR HAVING A CACHE WITH EFFICIENT STORAGE OF PREDECODE INFORMATION, CACHE, AND METHOD
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10887087
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Filing Dt:
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07/09/2004
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Publication #:
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Pub Dt:
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01/12/2006
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Title:
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COPPER CONDUCTOR
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10887983
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Filing Dt:
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07/08/2004
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Title:
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QUASI-STATIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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10890045
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Filing Dt:
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07/13/2004
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Title:
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THROUGHPUT AND LATENCY OF INBOUND AND OUTBOUND IPSEC PROCESSING
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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10890649
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Filing Dt:
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07/14/2004
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Title:
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Network interface with secondary data and packet information storage and memory control systems to accommodate out-of-order data processing and split transactions on a host system bus
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Patent #:
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Issue Dt:
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03/25/2008
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10892211
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Filing Dt:
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07/16/2004
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Publication #:
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Pub Dt:
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01/19/2006
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Title:
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METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
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Patent #:
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NONE
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Application #:
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10896398
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Filing Dt:
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07/22/2004
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Publication #:
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Pub Dt:
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12/22/2005
| | | | |
Title:
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System for controlling a multipurpose media access data processing system
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Patent #:
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Issue Dt:
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02/17/2009
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10896812
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Filing Dt:
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07/22/2004
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Publication #:
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Pub Dt:
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01/06/2005
| | | | |
Title:
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CONTROL OF BURIED OXIDE IN SIMOX
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Patent #:
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Issue Dt:
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03/17/2009
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Application #:
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10899199
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Filing Dt:
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07/26/2004
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Publication #:
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Pub Dt:
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09/01/2005
| | | | |
Title:
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ON-THE-FLY ENCRYPTION/DECRYPTION FOR WLAN COMMUNICATIONS
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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10899200
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Filing Dt:
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07/26/2004
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Publication #:
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Pub Dt:
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08/04/2005
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Title:
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FAST CIPHERING KEY SEARCH FOR WLAN RECEIVERS
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10899768
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Filing Dt:
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07/27/2004
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Publication #:
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Pub Dt:
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02/02/2006
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Title:
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TEMPERATURE SENSOR FOR HIGH POWER VERY LARGE SCALE INTEGRATION CIRCUITS
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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10899937
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Filing Dt:
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07/27/2004
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Publication #:
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Pub Dt:
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02/02/2006
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Title:
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DRAM ACCESS COMMAND QUEUING STRUCTURE
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Patent #:
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Issue Dt:
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07/03/2007
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Application #:
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10900487
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Filing Dt:
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07/28/2004
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Publication #:
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Pub Dt:
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01/13/2005
| | | | |
Title:
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TUNNELING MAGNETORESISTIVE (TMR) SENSOR HAVING A MAGNESIUM OXIDE BARRIER LAYER FORMED BY A MULTI-LAYER PROCESS
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10900832
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Filing Dt:
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07/28/2004
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Title:
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METHODS OF DETERMINING CHARACTERISTICS OF DOPED REGIONS ON DEVICE WAFERS, AND SYSTEM FOR ACCOMPLISHING SAME
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Patent #:
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Issue Dt:
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11/14/2006
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Application #:
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10901868
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Filing Dt:
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07/29/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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RELIABLE LOW-K INTERCONNECT STRUCTURE WITH HYBRID DIELECTRIC
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Patent #:
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Issue Dt:
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04/27/2010
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Application #:
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10902601
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Filing Dt:
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07/30/2004
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Publication #:
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Pub Dt:
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02/02/2006
| | | | |
Title:
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AUTONOMIC CLIENT MIGRATION SYSTEM FOR SERVICE ENGAGEMENTS
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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10902653
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Filing Dt:
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07/28/2004
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Publication #:
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Pub Dt:
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02/02/2006
| | | | |
Title:
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ESD DISSIPATIVE COATING ON CABLES
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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10904056
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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04/27/2006
| | | | |
Title:
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SIMULATION TESTING OF DIGITAL LOGIC CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10904059
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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STRUCTURE FOR STRAINED CHANNEL FIELD EFFECT TRANSISTOR PAIR HAVING A MEMBER AND A CONTACT VIA
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Patent #:
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Issue Dt:
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11/27/2007
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Application #:
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10904225
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
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Patent #:
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Issue Dt:
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03/25/2008
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Application #:
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10904355
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Filing Dt:
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11/05/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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METHOD FOR IMPROVING OPTICAL PROXIMITY CORRECTION
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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10904357
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Filing Dt:
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11/05/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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FIN DEVICE WITH CAPACITOR INTEGRATED UNDER GATE ELECTRODE
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10904391
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Filing Dt:
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11/08/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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SELF-ALIGNED LOW-K GATE CAP
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Patent #:
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Issue Dt:
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08/14/2007
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Application #:
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10904397
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Filing Dt:
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11/08/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR CONVERTING GLOBALLY CLOCK-GATED CIRCUITS TO LOCALLY CLOCK-GATED CIRCUITS
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10904435
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Filing Dt:
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11/10/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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APPARATUS AND METHOD FOR SINGLE DIE BACKSIDE PROBING OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10904438
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Filing Dt:
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11/10/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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IMPROVED ION DETECTOR FOR IONBEAM APPLICATIONS
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Issue Dt:
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01/15/2008
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Application #:
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10904528
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Filing Dt:
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11/15/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10904555
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Filing Dt:
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11/16/2004
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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FLUIDIC COOLING SYSTEMS AND METHODS FOR ELECTRONIC COMPONENTS
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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10904601
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Filing Dt:
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11/18/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM
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