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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
03/17/2009
Application #:
10829741
Filing Dt:
04/21/2004
Publication #:
Pub Dt:
11/17/2005
Title:
SYSTEM AND METHOD OF WORKLOAD-DEPENDENT RELIABILITY PROJECTION AND MONITORING FOR MICROPROCESSOR CHIPS AND SYSTEMS
2
Patent #:
Issue Dt:
07/26/2005
Application #:
10830006
Filing Dt:
04/23/2004
Publication #:
Pub Dt:
10/07/2004
Title:
NARROW FIN FINFET
3
Patent #:
Issue Dt:
11/22/2005
Application #:
10832215
Filing Dt:
04/26/2004
Publication #:
Pub Dt:
10/07/2004
Title:
DIVOT REDUCTION IN SIMOX LAYERS
4
Patent #:
Issue Dt:
08/01/2006
Application #:
10832217
Filing Dt:
04/26/2004
Publication #:
Pub Dt:
11/18/2004
Title:
HIGH SPEED COMPOSITE P-CHANNEL SI/SIGE HETEROSTRUCTURE FOR FIELD EFFECT DEVICES
5
Patent #:
Issue Dt:
07/06/2010
Application #:
10832658
Filing Dt:
04/27/2004
Publication #:
Pub Dt:
10/27/2005
Title:
ASYNCHRONOUS PACKET BASED DUAL PORT LINK LIST HEADER AND DATA CREDIT MANAGEMENT STRUCTURE
6
Patent #:
Issue Dt:
04/11/2006
Application #:
10833651
Filing Dt:
04/28/2004
Publication #:
Pub Dt:
11/03/2005
Title:
DEVICE AND METHOD FOR DETERMINING AN ILLUMINATION INTENSITY PROFILE OF AN ILLUMINATOR FOR A LITHOGRAPHY SYSTEM
7
Patent #:
Issue Dt:
06/27/2006
Application #:
10835182
Filing Dt:
04/29/2004
Publication #:
Pub Dt:
12/02/2004
Title:
METHOD OF FORMING A METAL SILICIDE
8
Patent #:
Issue Dt:
10/05/2010
Application #:
10835411
Filing Dt:
04/29/2004
Publication #:
Pub Dt:
03/03/2005
Title:
METHOD OF FORMING A TEOS CAP LAYER AT LOW TEMPERATURE AND REDUCED DEPOSITION RATE
9
Patent #:
Issue Dt:
05/02/2006
Application #:
10835814
Filing Dt:
04/30/2004
Publication #:
Pub Dt:
11/03/2005
Title:
NON-PLANARIZED, SELF-ALIGNED, NON-VOLATILE PHASE-CHANGE MEMORY ARRAY AND METHOD OF FORMATION
10
Patent #:
Issue Dt:
06/12/2007
Application #:
10837395
Filing Dt:
04/30/2004
Title:
SPEED VERIFICATION OF AN EMBEDDED PROCESSOR IN A PROGRAMMABLE LOGIC DEVICE
11
Patent #:
Issue Dt:
07/04/2006
Application #:
10838229
Filing Dt:
05/05/2004
Title:
METHOD OF MAKING A TEST STRUCTURE FOR GATE-BODY CURRENT AND DIRECT EXTRACTION OF PHYSICAL GATE LENGTH USING CONVENTIONAL CMOS
12
Patent #:
Issue Dt:
11/11/2008
Application #:
10838378
Filing Dt:
05/04/2004
Publication #:
Pub Dt:
11/10/2005
Title:
SELF-ALIGNED METAL TO FORM CONTACTS TO GE CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY
13
Patent #:
Issue Dt:
01/02/2007
Application #:
10838830
Filing Dt:
05/04/2004
Title:
USE OF NON-LITHOGRAPHIC SHRINK TECHNIQUES FOR FABRICATION/MAKING OF IMPRINTS MASKS
14
Patent #:
Issue Dt:
07/17/2007
Application #:
10839072
Filing Dt:
05/05/2004
Title:
EFFICIENT MEMORY CHECK ARCHITECTURE AND METHOD
15
Patent #:
Issue Dt:
12/19/2006
Application #:
10839437
Filing Dt:
05/04/2004
Title:
CONVERSION OF TRANSITION METAL TO SILICIDE THROUGH BACK END PROCESSING IN INTEGRATED CIRCUIT TECHNOLOGY
16
Patent #:
Issue Dt:
08/28/2007
Application #:
10839474
Filing Dt:
05/05/2004
Publication #:
Pub Dt:
11/10/2005
Title:
SYSTEM AND METHOD FOR VALIDATING A MEMORY FILE THAT LINKS SPECULATIVE RESULTS OF LOAD OPERATIONS TO REGISTER VALUES
17
Patent #:
Issue Dt:
03/10/2009
Application #:
10839872
Filing Dt:
05/06/2004
Publication #:
Pub Dt:
11/17/2005
Title:
NETWORK INTERFACE WITH SECURITY ASSOCIATION DATA PREFETCH FOR HIGH SPEED OFFLOADED SECURITY PROCESSING
18
Patent #:
Issue Dt:
09/16/2008
Application #:
10842085
Filing Dt:
05/10/2004
Publication #:
Pub Dt:
11/10/2005
Title:
DESIGN VERIFICATION OF HIGHLY OPTIMIZED SYNCHRONOUS PIPELINES VIA RANDOM SIMULATION DRIVEN BY CRITICAL RESOURCE SCHEDULING
19
Patent #:
Issue Dt:
03/21/2006
Application #:
10842297
Filing Dt:
05/10/2004
Publication #:
Pub Dt:
07/28/2005
Title:
METHOD FOR INITIALIZING A SYSTEM INCLUDING A HOST AND PLURALITY OF MEMORY MODULES CONNECTED VIA A SERIAL MEMORY INTERCONNECT
20
Patent #:
Issue Dt:
05/25/2010
Application #:
10843255
Filing Dt:
05/10/2004
Title:
MEDIA ACCELERATOR INTERFACE API
21
Patent #:
Issue Dt:
04/14/2009
Application #:
10843607
Filing Dt:
05/11/2004
Publication #:
Pub Dt:
11/17/2005
Title:
POST INITIAL MICROCODE LOAD CO-SIMULATION METHOD, SYSTEM, AND PROGRAM PRODUCT
22
Patent #:
Issue Dt:
10/07/2008
Application #:
10844093
Filing Dt:
05/12/2004
Publication #:
Pub Dt:
11/17/2005
Title:
ASYNCHRONOUS HIDDEN MARKOV MODEL METHOD AND SYSTEM
23
Patent #:
Issue Dt:
10/31/2006
Application #:
10844794
Filing Dt:
05/13/2004
Publication #:
Pub Dt:
11/17/2005
Title:
FAST AND ACCURATE OPTICAL PROXIMITY CORRECTION ENGINE FOR INCORPORATING LONG RANGE FLARE EFFECTS
24
Patent #:
Issue Dt:
07/25/2006
Application #:
10849459
Filing Dt:
05/19/2004
Publication #:
Pub Dt:
11/25/2004
Title:
SELF-ALIGNED CORROSION STOP FOR COPPER C4 AND WIREBOND
25
Patent #:
Issue Dt:
07/07/2009
Application #:
10849847
Filing Dt:
05/21/2004
Title:
METHOD OF FORMING SEMICONDUCTOR DEVICES BY MICROWAVE CURING OF LOW-K DIELECTRIC FILMS
26
Patent #:
Issue Dt:
11/14/2006
Application #:
10851821
Filing Dt:
05/21/2004
Publication #:
Pub Dt:
11/24/2005
Title:
POLYCRYSTALLINE SIGE JUNCTIONS FOR ADVANCED DEVICES
27
Patent #:
Issue Dt:
10/03/2006
Application #:
10852142
Filing Dt:
05/25/2004
Publication #:
Pub Dt:
10/28/2004
Title:
METHOD TO SELECTIVELY CAP INTERCONNECTS WITH INDIUM OR TIN BRONZES AND/OR OXIDES THEREOF AND THE INTERCONNECT SO CAPPED
28
Patent #:
Issue Dt:
05/06/2008
Application #:
10853041
Filing Dt:
05/25/2004
Publication #:
Pub Dt:
12/15/2005
Title:
MODELING LANGUAGE AND METHOD FOR ADDRESS TRANSLATION DESIGN MECHANISMS IN TEST GENERATION
29
Patent #:
Issue Dt:
03/11/2008
Application #:
10855047
Filing Dt:
05/27/2004
Publication #:
Pub Dt:
12/01/2005
Title:
METHOD FOR DEFERRED DATA COLLECTION IN A CLOCK RUNNING SYSTEM
30
Patent #:
Issue Dt:
03/25/2008
Application #:
10855915
Filing Dt:
05/27/2004
Publication #:
Pub Dt:
12/23/2004
Title:
HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT
31
Patent #:
Issue Dt:
06/14/2005
Application #:
10856503
Filing Dt:
05/28/2004
Publication #:
Pub Dt:
11/11/2004
Title:
METHOD TO FABRICATE HIGH-PERFORMANCE NPN TRANSISTORS IN A BICMOS PROCESS
32
Patent #:
Issue Dt:
03/07/2006
Application #:
10856547
Filing Dt:
05/28/2004
Publication #:
Pub Dt:
12/01/2005
Title:
INDIRECT SWITCHING AND SENSING OF PHASE CHANGE MEMORY CELLS
33
Patent #:
Issue Dt:
11/11/2008
Application #:
10858605
Filing Dt:
06/02/2004
Title:
FEEDBACK CONTROL OF IMPRINT MASK FEATURE PROFILE USING SCATTEROMETRY AND SPACER ETCHBACK
34
Patent #:
Issue Dt:
11/14/2006
Application #:
10858739
Filing Dt:
06/01/2004
Title:
WAFER LEVEL GLOBAL BITMAP CHARACTERIZATION IN INTEGRATED CIRCUIT TECHNOLOGY DEVELOPMENT
35
Patent #:
Issue Dt:
05/29/2007
Application #:
10858759
Filing Dt:
06/02/2004
Title:
IN-SITU DEFECT MONITOR AND CONTROL SYSTEM FOR IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY
36
Patent #:
Issue Dt:
04/29/2008
Application #:
10858791
Filing Dt:
06/02/2004
Title:
METHOD FOR OPTIMIZING LOOP CONTROL OF MICROCODED INSTRUCTIONS
37
Patent #:
NONE
Issue Dt:
Application #:
10859031
Filing Dt:
06/01/2004
Publication #:
Pub Dt:
03/31/2005
Title:
Storage tank for process liquids with a reduced amount of bubbles
38
Patent #:
Issue Dt:
09/09/2008
Application #:
10859276
Filing Dt:
06/02/2004
Title:
OPTICAL PROXIMITY CORRECTION (OPC) TECHNIQUE TO COMPENSATE FOR FLARE
39
Patent #:
Issue Dt:
08/14/2007
Application #:
10859673
Filing Dt:
06/03/2004
Title:
METHODS AND FIXTURE FOR COUPLING A LID TO A SUPPORT SUBSTRATE
40
Patent #:
Issue Dt:
02/20/2007
Application #:
10860100
Filing Dt:
06/04/2004
Title:
METHOD FOR OFFSETTING A SILICIDE PROCESS FROM A GATE ELECTRODE OF A SEMICONDUCTOR DEVICE
41
Patent #:
Issue Dt:
02/08/2011
Application #:
10860966
Filing Dt:
06/04/2004
Title:
MUTI-GIGABIT PER SECOND CONCURRENT ENCRYPTION IN BLOCK CIPHER MODES
42
Patent #:
Issue Dt:
02/13/2007
Application #:
10862518
Filing Dt:
06/07/2004
Publication #:
Pub Dt:
05/05/2005
Title:
TECHNIQUE FOR FORMING TRANSISTORS HAVING RAISED DRAIN AND SOURCE REGIONS WITH DIFFERENT HEIGHTS
43
Patent #:
Issue Dt:
05/31/2005
Application #:
10865138
Filing Dt:
06/10/2004
Publication #:
Pub Dt:
11/11/2004
Title:
DIFFUSED EXTRINSIC BASE AND METHOD FOR FABRICATION
44
Patent #:
Issue Dt:
09/05/2006
Application #:
10865836
Filing Dt:
06/14/2004
Title:
BACK TO BACK CONNECTION OF PCI HOST BRIDGES ON A SINGLE PCI BUS
45
Patent #:
Issue Dt:
10/24/2006
Application #:
10865920
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
12/15/2005
Title:
MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER
46
Patent #:
Issue Dt:
08/05/2008
Application #:
10867094
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
12/15/2005
Title:
MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT
47
Patent #:
Issue Dt:
08/05/2008
Application #:
10867302
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
12/02/2004
Title:
SYSTEM FOR FACILITATING COVERAGE FEEDBACK TESTCASE GENERATION REPRODUCIBILITY
48
Patent #:
Issue Dt:
09/04/2007
Application #:
10867772
Filing Dt:
06/16/2004
Publication #:
Pub Dt:
01/06/2005
Title:
METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN
49
Patent #:
Issue Dt:
05/24/2005
Application #:
10868723
Filing Dt:
06/15/2004
Publication #:
Pub Dt:
11/18/2004
Title:
METHOD FOR CONTROLLING LOCAL CURRENT TO ACHIEVE UNIFORM PLATING THICKNESS
50
Patent #:
Issue Dt:
12/05/2006
Application #:
10868791
Filing Dt:
06/17/2004
Publication #:
Pub Dt:
11/25/2004
Title:
METHOD FOR MANUFACTURING DEVICE SUBSTRATE WITH METAL BACK-GATE AND STRUCTURE FORMED THEREBY
51
Patent #:
Issue Dt:
06/20/2006
Application #:
10869624
Filing Dt:
06/16/2004
Publication #:
Pub Dt:
11/11/2004
Title:
IMPLANTED ASYMMETRIC DOPED POLYSILICON GATE FINFET
52
Patent #:
Issue Dt:
10/09/2007
Application #:
10869658
Filing Dt:
06/16/2004
Publication #:
Pub Dt:
12/22/2005
Title:
HIGH-TEMPERATURE STABLE GATE STRUCTURE WITH METALLIC ELECTRODE
53
Patent #:
Issue Dt:
01/08/2013
Application #:
10870318
Filing Dt:
06/17/2004
Title:
NETWORK INTERFACE SYSTEMS AND METHODS FOR OFFLOADING SEGMENTATION AND/OR CHECKSUMMING WITH SECURITY PROCESSING
54
Patent #:
Issue Dt:
06/20/2006
Application #:
10872173
Filing Dt:
06/18/2004
Publication #:
Pub Dt:
11/18/2004
Title:
MOS ANTIFUSE WITH LOW POST-PROGRAM RESISTANCE
55
Patent #:
Issue Dt:
12/05/2006
Application #:
10873069
Filing Dt:
06/21/2004
Title:
ELECTRICALLY ADDRESSABLE MEMORY SWITCH
56
Patent #:
Issue Dt:
05/29/2007
Application #:
10873240
Filing Dt:
06/23/2004
Title:
MULTI-CHANNEL TRANSISTOR WITH TUNABLE HOT CARRIER EFFECT
57
Patent #:
Issue Dt:
10/03/2006
Application #:
10873733
Filing Dt:
06/22/2004
Publication #:
Pub Dt:
12/22/2005
Title:
METHOD OF FORMING METAL/HIGH-K GATE STACKS WITH HIGH MOBILITY
58
Patent #:
Issue Dt:
06/10/2008
Application #:
10874498
Filing Dt:
06/23/2004
Title:
POST FABRICATION CD MODIFICATION ON IMPRINT LITHOGRAPHY MASK
59
Patent #:
Issue Dt:
05/20/2008
Application #:
10874499
Filing Dt:
06/23/2004
Title:
TOPOGRAPHY COMPENSATION OF IMPRINT LITHOGRAPHY PATTERNING
60
Patent #:
Issue Dt:
03/06/2007
Application #:
10875727
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
12/29/2005
Title:
COMPRESSIVE SIGE <110> GROWTH AND STRUCTURE OF MOSFET DEVICES
61
Patent #:
Issue Dt:
04/12/2005
Application #:
10879538
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
01/06/2005
Title:
CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEFECTS
62
Patent #:
Issue Dt:
11/29/2005
Application #:
10879833
Filing Dt:
06/29/2004
Title:
DUAL GATED FINFET GAIN CELL
63
Patent #:
Issue Dt:
09/16/2008
Application #:
10880853
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD, SYSTEM AND PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING INCOMPLETELY SPECIFIED CONFIGURATION ENTITIES
64
Patent #:
Issue Dt:
02/22/2005
Application #:
10881449
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
12/09/2004
Title:
MOSFET DEVICE WITH IN-SITU DOPED, RAISED SOURCE AND DRAIN STRUCTURES
65
Patent #:
Issue Dt:
03/31/2009
Application #:
10881853
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
12/29/2005
Title:
WEAR GAUGE AND METHOD OF USE
66
Patent #:
Issue Dt:
12/27/2011
Application #:
10881932
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
02/03/2005
Title:
METHOD OF IMPROVING THE WAFER-TO-WAFER THICKNESS UNIFORMITY OF SILICON NITRIDE LAYERS
67
Patent #:
Issue Dt:
11/21/2006
Application #:
10883392
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
APPARATUS AND METHODS FOR MICROCHANNEL COOLING OF SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGES
68
Patent #:
Issue Dt:
08/01/2006
Application #:
10883434
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
02/03/2005
Title:
SI/SIGE OPTOELECTRONIC INTEGRATED CIRCUITS
69
Patent #:
Issue Dt:
02/06/2007
Application #:
10883887
Filing Dt:
07/02/2004
Publication #:
Pub Dt:
01/05/2006
Title:
STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED P+ SILICON GERMANIUM LAYER
70
Patent #:
Issue Dt:
04/27/2010
Application #:
10885462
Filing Dt:
07/06/2004
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS FOR THE FORMATION OF FULLY SILICIDED METAL GATES
71
Patent #:
Issue Dt:
03/15/2005
Application #:
10886341
Filing Dt:
07/07/2004
Title:
BUILT-IN SELF TIMING TEST METHOD AND APPARATUS
72
Patent #:
Issue Dt:
11/02/2010
Application #:
10887069
Filing Dt:
07/08/2004
Title:
DATA PROCESSOR HAVING A CACHE WITH EFFICIENT STORAGE OF PREDECODE INFORMATION, CACHE, AND METHOD
73
Patent #:
Issue Dt:
10/10/2006
Application #:
10887087
Filing Dt:
07/09/2004
Publication #:
Pub Dt:
01/12/2006
Title:
COPPER CONDUCTOR
74
Patent #:
Issue Dt:
12/13/2005
Application #:
10887983
Filing Dt:
07/08/2004
Title:
QUASI-STATIC RANDOM ACCESS MEMORY
75
Patent #:
Issue Dt:
04/28/2009
Application #:
10890045
Filing Dt:
07/13/2004
Title:
THROUGHPUT AND LATENCY OF INBOUND AND OUTBOUND IPSEC PROCESSING
76
Patent #:
Issue Dt:
08/06/2013
Application #:
10890649
Filing Dt:
07/14/2004
Title:
Network interface with secondary data and packet information storage and memory control systems to accommodate out-of-order data processing and split transactions on a host system bus
77
Patent #:
Issue Dt:
03/25/2008
Application #:
10892211
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
78
Patent #:
NONE
Issue Dt:
Application #:
10896398
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
12/22/2005
Title:
System for controlling a multipurpose media access data processing system
79
Patent #:
Issue Dt:
02/17/2009
Application #:
10896812
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
01/06/2005
Title:
CONTROL OF BURIED OXIDE IN SIMOX
80
Patent #:
Issue Dt:
03/17/2009
Application #:
10899199
Filing Dt:
07/26/2004
Publication #:
Pub Dt:
09/01/2005
Title:
ON-THE-FLY ENCRYPTION/DECRYPTION FOR WLAN COMMUNICATIONS
81
Patent #:
Issue Dt:
08/19/2014
Application #:
10899200
Filing Dt:
07/26/2004
Publication #:
Pub Dt:
08/04/2005
Title:
FAST CIPHERING KEY SEARCH FOR WLAN RECEIVERS
82
Patent #:
Issue Dt:
02/13/2007
Application #:
10899768
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
02/02/2006
Title:
TEMPERATURE SENSOR FOR HIGH POWER VERY LARGE SCALE INTEGRATION CIRCUITS
83
Patent #:
Issue Dt:
10/02/2007
Application #:
10899937
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
02/02/2006
Title:
DRAM ACCESS COMMAND QUEUING STRUCTURE
84
Patent #:
Issue Dt:
07/03/2007
Application #:
10900487
Filing Dt:
07/28/2004
Publication #:
Pub Dt:
01/13/2005
Title:
TUNNELING MAGNETORESISTIVE (TMR) SENSOR HAVING A MAGNESIUM OXIDE BARRIER LAYER FORMED BY A MULTI-LAYER PROCESS
85
Patent #:
Issue Dt:
06/20/2006
Application #:
10900832
Filing Dt:
07/28/2004
Title:
METHODS OF DETERMINING CHARACTERISTICS OF DOPED REGIONS ON DEVICE WAFERS, AND SYSTEM FOR ACCOMPLISHING SAME
86
Patent #:
Issue Dt:
11/14/2006
Application #:
10901868
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/03/2005
Title:
RELIABLE LOW-K INTERCONNECT STRUCTURE WITH HYBRID DIELECTRIC
87
Patent #:
Issue Dt:
04/27/2010
Application #:
10902601
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
AUTONOMIC CLIENT MIGRATION SYSTEM FOR SERVICE ENGAGEMENTS
88
Patent #:
Issue Dt:
05/29/2007
Application #:
10902653
Filing Dt:
07/28/2004
Publication #:
Pub Dt:
02/02/2006
Title:
ESD DISSIPATIVE COATING ON CABLES
89
Patent #:
Issue Dt:
07/31/2007
Application #:
10904056
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
04/27/2006
Title:
SIMULATION TESTING OF DIGITAL LOGIC CIRCUIT DESIGNS
90
Patent #:
Issue Dt:
08/29/2006
Application #:
10904059
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
05/11/2006
Title:
STRUCTURE FOR STRAINED CHANNEL FIELD EFFECT TRANSISTOR PAIR HAVING A MEMBER AND A CONTACT VIA
91
Patent #:
Issue Dt:
11/27/2007
Application #:
10904225
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/11/2006
Title:
TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
92
Patent #:
Issue Dt:
03/25/2008
Application #:
10904355
Filing Dt:
11/05/2004
Publication #:
Pub Dt:
05/11/2006
Title:
METHOD FOR IMPROVING OPTICAL PROXIMITY CORRECTION
93
Patent #:
Issue Dt:
09/25/2007
Application #:
10904357
Filing Dt:
11/05/2004
Publication #:
Pub Dt:
05/11/2006
Title:
FIN DEVICE WITH CAPACITOR INTEGRATED UNDER GATE ELECTRODE
94
Patent #:
Issue Dt:
06/12/2007
Application #:
10904391
Filing Dt:
11/08/2004
Publication #:
Pub Dt:
05/11/2006
Title:
SELF-ALIGNED LOW-K GATE CAP
95
Patent #:
Issue Dt:
08/14/2007
Application #:
10904397
Filing Dt:
11/08/2004
Publication #:
Pub Dt:
05/11/2006
Title:
METHOD AND APPARATUS FOR CONVERTING GLOBALLY CLOCK-GATED CIRCUITS TO LOCALLY CLOCK-GATED CIRCUITS
96
Patent #:
Issue Dt:
09/26/2006
Application #:
10904435
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
05/11/2006
Title:
APPARATUS AND METHOD FOR SINGLE DIE BACKSIDE PROBING OF SEMICONDUCTOR DEVICES
97
Patent #:
Issue Dt:
10/10/2006
Application #:
10904438
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
05/11/2006
Title:
IMPROVED ION DETECTOR FOR IONBEAM APPLICATIONS
98
Patent #:
Issue Dt:
01/15/2008
Application #:
10904528
Filing Dt:
11/15/2004
Publication #:
Pub Dt:
05/18/2006
Title:
STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT
99
Patent #:
Issue Dt:
07/18/2006
Application #:
10904555
Filing Dt:
11/16/2004
Publication #:
Pub Dt:
05/18/2006
Title:
FLUIDIC COOLING SYSTEMS AND METHODS FOR ELECTRONIC COMPONENTS
100
Patent #:
Issue Dt:
04/22/2008
Application #:
10904601
Filing Dt:
11/18/2004
Publication #:
Pub Dt:
05/18/2006
Title:
METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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