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Reel/Frame:	056987/0001			Pages:	1045
		Recorded:	05/12/2021
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 18026
Page 51 of 181
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Patent #:	7109584	Issue Dt:	09/19/2006	Application #:	10904680	Filing Dt:	11/23/2004
Publication #:	US20060110909	Pub Dt:	05/25/2006
Title:	DENDRITE GROWTH CONTROL CIRCUIT

Patent #:	7242072	Issue Dt:	07/10/2007	Application #:	10904681	Filing Dt:	11/23/2004
Publication #:	US20060108662	Pub Dt:	05/25/2006
Title:	AN ELECTRICALLY PROGRAMMABLE FUSE FOR SILICON-ON-INSULATOR (SOI) TECHNOLOGY

Patent #:	7193254	Issue Dt:	03/20/2007	Application #:	10904808	Filing Dt:	11/30/2004
Publication #:	US20060113568	Pub Dt:	06/01/2006
Title:	STRUCTURE AND METHOD OF APPLYING STRESSES TO PFET AND NFET TRANSISTOR CHANNELS FOR IMPROVED PERFORMANCE

Patent #:	7138717	Issue Dt:	11/21/2006	Application #:	10904827	Filing Dt:	12/01/2004
Publication #:	US20060113672	Pub Dt:	06/01/2006
Title:	IMPROVED HDP-BASED ILD CAPPING LAYER

Patent #:	7240310	Issue Dt:	07/03/2007	Application #:	10904950	Filing Dt:	12/07/2004
Publication #:	US20060123364	Pub Dt:	06/08/2006
Title:	METHOD, SYSTEM AND PROGRAM PRODUCT FOR EVALUATING A CIRCUIT

Patent #:	7257783	Issue Dt:	08/14/2007	Application #:	10905008	Filing Dt:	12/09/2004
Publication #:	US20060101357	Pub Dt:	05/11/2006
Title:	TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS

Patent #:	7306983	Issue Dt:	12/11/2007	Application #:	10905024	Filing Dt:	12/10/2004
Publication #:	US20060128086	Pub Dt:	06/15/2006
Title:	METHOD FOR FORMING DUAL ETCH STOP LINER AND PROTECTIVE LAYER IN A SEMICONDUCTOR DEVICE

Patent #:	7348635	Issue Dt:	03/25/2008	Application #:	10905025	Filing Dt:	12/10/2004
Publication #:	US20060128091	Pub Dt:	06/15/2006
Title:	DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS

Patent #:	7446062	Issue Dt:	11/04/2008	Application #:	10905027	Filing Dt:	12/10/2004
Publication #:	US20060128145	Pub Dt:	06/15/2006
Title:	DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS

Patent #:	7262087	Issue Dt:	08/28/2007	Application #:	10905062	Filing Dt:	12/14/2004
Publication #:	US20060125008	Pub Dt:	06/15/2006
Title:	DUAL STRESSED SOI SUBSTRATES

Patent #:	7326651	Issue Dt:	02/05/2008	Application #:	10905068	Filing Dt:	12/14/2004
Publication #:	US20050079701	Pub Dt:	04/14/2005
Title:	METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH COMPRESSIVE DIFFUSION BARRIER MATERIAL

Patent #:	7193262	Issue Dt:	03/20/2007	Application #:	10905094	Filing Dt:	12/15/2004
Publication #:	US20060124982	Pub Dt:	06/15/2006
Title:	LOW-COST DEEP TRENCH DECOUPLING CAPACITOR DEVICE AND PROCESS OF MANUFACTURE

Patent #:	7253106	Issue Dt:	08/07/2007	Application #:	10905230	Filing Dt:	12/22/2004
Publication #:	US20060134911	Pub Dt:	06/22/2006
Title:	MANUFACTURABLE COWP METAL CAP PROCESS FOR COPPER INTERCONNECTS

Patent #:	7269818	Issue Dt:	09/11/2007	Application #:	10905474	Filing Dt:	01/06/2005
Publication #:	US20060150139	Pub Dt:	07/06/2006
Title:	CIRCUIT ELEMENT FUNCTION MATCHING DESPITE AUTO-GENERATED DUMMY SHAPES

Patent #:	7288417	Issue Dt:	10/30/2007	Application #:	10905480	Filing Dt:	01/06/2005
Publication #:	US20060148106	Pub Dt:	07/06/2006
Title:	ON-CHIP SIGNAL TRANSFORMER FOR GROUND NOISE ISOLATION

Patent #:	7518215	Issue Dt:	04/14/2009	Application #:	10905486	Filing Dt:	01/06/2005
Publication #:	US20060145300	Pub Dt:	07/06/2006
Title:	ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT

Patent #:	7271442	Issue Dt:	09/18/2007	Application #:	10905586	Filing Dt:	01/12/2005
Publication #:	US20060151833	Pub Dt:	07/13/2006
Title:	TRANSISTOR STRUCTURE HAVING STRESSED REGIONS OF OPPOSITE TYPES UNDERLYING CHANNEL AND SOURCE/DRAIN REGIONS

Patent #:	7274084	Issue Dt:	09/25/2007	Application #:	10905589	Filing Dt:	01/12/2005
Publication #:	US20060151838	Pub Dt:	07/13/2006
Title:	ENHANCED PFET USING SHEAR STRESS

Patent #:	7345370	Issue Dt:	03/18/2008	Application #:	10905590	Filing Dt:	01/12/2005
Publication #:	US20060154463	Pub Dt:	07/13/2006
Title:	WIRING PATTERNS FORMED BY SELECTIVE METAL PLATING

Patent #:	7049695	Issue Dt:	05/23/2006	Application #:	10905643	Filing Dt:	01/14/2005
Title:	METHOD AND DEVICE FOR HEAT DISSIPATION IN SEMICONDUCTOR MODULES

Patent #:	7153737	Issue Dt:	12/26/2006	Application #:	10905684	Filing Dt:	01/17/2005
Publication #:	US20060160298	Pub Dt:	07/20/2006
Title:	SELF-ALIGNED, SILICIDED, TRENCH-BASED, DRAM/EDRAM PROCESSES WITH IMPROVED RETENTION

Patent #:	7354333	Issue Dt:	04/08/2008	Application #:	10905816	Filing Dt:	01/21/2005
Publication #:	US20060166607	Pub Dt:	07/27/2006
Title:	DETECTION OF DIAMOND CONTAMINATION IN POLISHING PAD

Patent #:	7177619	Issue Dt:	02/13/2007	Application #:	10905874	Filing Dt:	01/25/2005
Publication #:	US20060164180	Pub Dt:	07/27/2006
Title:	DUAL GATE FINFET RADIO FREQUENCY SWITCH AND MIXER

Patent #:	8018017	Issue Dt:	09/13/2011	Application #:	10905905	Filing Dt:	01/26/2005
Publication #:	US20060163685	Pub Dt:	07/27/2006
Title:	THERMO-MECHANICAL CLEAVABLE STRUCTURE

Patent #:	7071530	Issue Dt:	07/04/2006	Application #:	10905934	Filing Dt:	01/27/2005
Publication #:	US20060163688	Pub Dt:	07/27/2006
Title:	MULTIPLE LAYER STRUCTURE FOR SUBSTRATE NOISE ISOLATION

Patent #:	7225421	Issue Dt:	05/29/2007	Application #:	10905970	Filing Dt:	01/28/2005
Publication #:	US20060190899	Pub Dt:	08/24/2006
Title:	CLOCK TREE DISTRIBUTION GENERATION BY DETERMINING ALLOWED PLACEMENT REGIONS FOR CLOCKED ELEMENTS

Patent #:	7091542	Issue Dt:	08/15/2006	Application #:	10905973	Filing Dt:	01/28/2005
Publication #:	US20060170024	Pub Dt:	08/03/2006
Title:	METHOD OF FORMING A MIM CAPACITOR FOR CU BEOL APPLICATION

Patent #:	7535016	Issue Dt:	05/19/2009	Application #:	10906016	Filing Dt:	01/31/2005
Publication #:	US20060169972	Pub Dt:	08/03/2006
Title:	VERTICAL CARBON NANOTUBE TRANSISTOR INTEGRATION

Patent #:	7316572	Issue Dt:	01/08/2008	Application #:	10906111	Filing Dt:	02/03/2005
Publication #:	US20060172565	Pub Dt:	08/03/2006
Title:	COMPLIANT ELECTRICAL CONTACTS

Patent #:	7517790	Issue Dt:	04/14/2009	Application #:	10906189	Filing Dt:	02/08/2005
Publication #:	US20050116357	Pub Dt:	06/02/2005
Title:	METHOD AND STRUCTURE TO ENHANCE TEMPERATURE/HUMIDITY/BIAS PERFORMANCE OF SEMICONDUCTOR DEVICES BY SURFACE MODIFICATION

Patent #:	7439568	Issue Dt:	10/21/2008	Application #:	10906238	Filing Dt:	02/10/2005
Publication #:	US20060175660	Pub Dt:	08/10/2006
Title:	VERTICAL BODY-CONTACTED SOI TRANSISTOR

Patent #:	7531444	Issue Dt:	05/12/2009	Application #:	10906267	Filing Dt:	02/11/2005
Publication #:	US20060183315	Pub Dt:	08/17/2006
Title:	METHOD TO CREATE AIR GAPS USING NON-PLASMA PROCESSES TO DAMAGE ILD MATERIALS

Patent #:	7977032	Issue Dt:	07/12/2011	Application #:	10906268	Filing Dt:	02/11/2005
Publication #:	US20060183062	Pub Dt:	08/17/2006
Title:	METHOD TO CREATE REGION SPECIFIC EXPOSURE IN A LAYER

Patent #:	7224033	Issue Dt:	05/29/2007	Application #:	10906335	Filing Dt:	02/15/2005
Publication #:	US20060180866	Pub Dt:	08/17/2006
Title:	STRUCTURE AND METHOD FOR MANUFACTURING STRAINED FINFET

Patent #:	7271700	Issue Dt:	09/18/2007	Application #:	10906365	Filing Dt:	02/16/2005
Publication #:	US20060181388	Pub Dt:	08/17/2006
Title:	THIN FILM RESISTOR WITH CURRENT DENSITY ENHANCING LAYER (CDEL)

Patent #:	7205627	Issue Dt:	04/17/2007	Application #:	10906510	Filing Dt:	02/23/2005
Publication #:	US20060186505	Pub Dt:	08/24/2006
Title:	IMAGE SENSOR CELLS

Patent #:	7288805	Issue Dt:	10/30/2007	Application #:	10906547	Filing Dt:	02/24/2005
Publication #:	US20060197147	Pub Dt:	09/07/2006
Title:	IMPROVED DOUBLE GATE ISOLATION

Patent #:	7240306	Issue Dt:	07/03/2007	Application #:	10906553	Filing Dt:	02/24/2005
Publication #:	US20060190224	Pub Dt:	08/24/2006
Title:	INTEGRATED CIRCUIT LAYOUT CRITICAL AREA DETERMINATION USING VORONOI DIAGRAMS AND SHAPE BIASING

Patent #:	7914949	Issue Dt:	03/29/2011	Application #:	10906564	Filing Dt:	02/24/2005
Publication #:	US20060190196	Pub Dt:	08/24/2006
Title:	METHOD FOR TESTING A PHOTOMASK

Patent #:	7276748	Issue Dt:	10/02/2007	Application #:	10906625	Filing Dt:	02/28/2005
Publication #:	US20060192233	Pub Dt:	08/31/2006
Title:	BODY POTENTIAL IMAGER CELL

Patent #:	7288451	Issue Dt:	10/30/2007	Application #:	10906669	Filing Dt:	03/01/2005
Publication #:	US20060199326	Pub Dt:	09/07/2006
Title:	METHOD AND STRUCTURE FOR FORMING SELF-ALIGNED, DUAL STRESS LINER FOR CMOS DEVICES

Patent #:	7227207	Issue Dt:	06/05/2007	Application #:	10906718	Filing Dt:	03/03/2005
Publication #:	US20060197179	Pub Dt:	09/07/2006
Title:	DENSE SEMICONDUCTOR FUSE ARRAY

Patent #:	8053823	Issue Dt:	11/08/2011	Application #:	10906808	Filing Dt:	03/08/2005
Publication #:	US20060202249	Pub Dt:	09/14/2006
Title:	SIMPLIFIED BURIED PLATE STRUCTURE AND PROCESS FOR SEMICONDUCTOR-ON-INSULATOR CHIP

Patent #:	7518235	Issue Dt:	04/14/2009	Application #:	10906809	Filing Dt:	03/08/2005
Publication #:	US20060202325	Pub Dt:	09/14/2006
Title:	METHOD AND STRUCTURE TO PROVIDE BALANCED MECHANICAL LOADING OF DEVICES IN COMPRESSIVELY LOADED ENVIRONMENTS

Patent #:	7824933	Issue Dt:	11/02/2010	Application #:	10906826	Filing Dt:	03/08/2005
Publication #:	US20060205098	Pub Dt:	09/14/2006
Title:	METHOD OF DETERMINING N-WELL SCATTERING EFFECTS ON FETS

Patent #:	7585704	Issue Dt:	09/08/2009	Application #:	10907454	Filing Dt:	04/01/2005
Publication #:	US20060223290	Pub Dt:	10/05/2006
Title:	METHOD OF PRODUCING HIGHLY STRAINED PECVD SILICON NITRIDE THIN FILMS AT LOW TEMPERATURE

Patent #:	7049209	Issue Dt:	05/23/2006	Application #:	10907463	Filing Dt:	04/01/2005
Title:	DE-FLUORINATION OF WAFER SURFACE AND RELATED STRUCTURE

Patent #:	7290226	Issue Dt:	10/30/2007	Application #:	10907496	Filing Dt:	04/04/2005
Publication #:	US20060225005	Pub Dt:	10/05/2006
Title:	VIA REDUNDANCY BASED ON SUBNET TIMING INFORMATION, TARGET VIA DISTANT ALONG PATH FROM SOURCE AND/OR TARGET VIA NET/SUBNET CHARACTERISTIC

Patent #:	7259625	Issue Dt:	08/21/2007	Application #:	10907537	Filing Dt:	04/05/2005
Publication #:	US20060220737	Pub Dt:	10/05/2006
Title:	HIGH Q MONOLITHIC INDUCTORS FOR USE IN DIFFERENTIAL CIRCUITS

Patent #:	7205591	Issue Dt:	04/17/2007	Application #:	10907570	Filing Dt:	04/06/2005
Publication #:	US20060226456	Pub Dt:	10/12/2006
Title:	PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF

Patent #:	7451070	Issue Dt:	11/11/2008	Application #:	10907628	Filing Dt:	04/08/2005
Publication #:	US20060229858	Pub Dt:	10/12/2006
Title:	OPTIMAL BUS OPERATION PERFORMANCE IN A LOGIC SIMULATION ENVIRONMENT

Patent #:	7485910	Issue Dt:	02/03/2009	Application #:	10907630	Filing Dt:	04/08/2005
Publication #:	US20060226481	Pub Dt:	10/12/2006
Title:	SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/EDRAM INTEGRATION: METHOD AND STRUCTURE

Patent #:	7816728	Issue Dt:	10/19/2010	Application #:	10907686	Filing Dt:	04/12/2005
Publication #:	US20060226474	Pub Dt:	10/12/2006
Title:	STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS

Patent #:	7091551	Issue Dt:	08/15/2006	Application #:	10907712	Filing Dt:	04/13/2005
Title:	FOUR-BIT FINFET NVRAM MEMORY DEVICE

Patent #:	7084462	Issue Dt:	08/01/2006	Application #:	10907796	Filing Dt:	04/15/2005
Title:	PARALLEL FIELD EFFECT TRANSISTOR STRUCTURE HAVING A BODY CONTACT

Patent #:	7166913	Issue Dt:	01/23/2007	Application #:	10907873	Filing Dt:	04/19/2005
Publication #:	US20060231945	Pub Dt:	10/19/2006
Title:	HEAT DISSIPATION FOR HEAT GENERATING ELEMENT OF SEMICONDUCTOR DEVICE AND RELATED METHOD

Patent #:	7504700	Issue Dt:	03/17/2009	Application #:	10907935	Filing Dt:	04/21/2005
Publication #:	US20060237803	Pub Dt:	10/26/2006
Title:	METHOD OF FORMING AN ULTRA-THIN [[HFSIO]] METAL SILCATE FILM FOR HIGH PERFORMANCE CMOS APPLICATIONS AND SEMICONDUCTOR STRUCTURE FORMED IN SAID METHOD

Patent #:	7102181	Issue Dt:	09/05/2006	Application #:	10907971	Filing Dt:	04/22/2005
Title:	STRUCTURE AND METHOD FOR DUAL-GATE FET WITH SOI SUBSTRATE

Patent #:	7329951	Issue Dt:	02/12/2008	Application #:	10908083	Filing Dt:	04/27/2005
Publication #:	US20060244139	Pub Dt:	11/02/2006
Title:	SOLDER BUMPS IN FLIP-CHIP TECHNOLOGIES

Patent #:	7418689	Issue Dt:	08/26/2008	Application #:	10908102	Filing Dt:	04/27/2005
Publication #:	US20060248488	Pub Dt:	11/02/2006
Title:	METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION

Patent #:	7355249	Issue Dt:	04/08/2008	Application #:	10908117	Filing Dt:	04/28/2005
Publication #:	US20060244062	Pub Dt:	11/02/2006
Title:	SILICON-ON-INSULATOR BASED RADIATION DETECTION DEVICE AND METHOD

Patent #:	7482258	Issue Dt:	01/27/2009	Application #:	10908118	Filing Dt:	04/28/2005
Publication #:	US20060246682	Pub Dt:	11/02/2006
Title:	PRODUCT AND METHOD FOR INTEGRATION OF DEEP TRENCH MESH AND STRUCTURES UNDER A BOND PAD

Patent #:	7288482	Issue Dt:	10/30/2007	Application #:	10908252	Filing Dt:	05/04/2005
Publication #:	US20060252269	Pub Dt:	11/09/2006
Title:	SILICON NITRIDE ETCHING METHODS

Patent #:	7200257	Issue Dt:	04/03/2007	Application #:	10908284	Filing Dt:	05/05/2005
Publication #:	US20060253828	Pub Dt:	11/09/2006
Title:	STRUCTURE AND METHODOLOGY FOR FABRICATION AND INSPECTION OF PHOTOMASKS

Patent #:	7389480	Issue Dt:	06/17/2008	Application #:	10908342	Filing Dt:	05/09/2005
Publication #:	US20060253806	Pub Dt:	11/09/2006
Title:	CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS

Patent #:	7361993	Issue Dt:	04/22/2008	Application #:	10908346	Filing Dt:	05/09/2005
Publication #:	US20060249848	Pub Dt:	11/09/2006
Title:	TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME

Patent #:	7250363	Issue Dt:	07/31/2007	Application #:	10908357	Filing Dt:	05/09/2005
Publication #:	US20060252263	Pub Dt:	11/09/2006
Title:	ALIGNED DUMMY METAL FILL AND HOLE SHAPES

Patent #:	7122898	Issue Dt:	10/17/2006	Application #:	10908360	Filing Dt:	05/09/2005
Publication #:	US20060249846	Pub Dt:	11/09/2006
Title:	ELECTRICAL PROGRAMMABLE METAL RESISTOR

Patent #:	7262484	Issue Dt:	08/28/2007	Application #:	10908361	Filing Dt:	05/09/2005
Publication #:	US20060249813	Pub Dt:	11/09/2006
Title:	STRUCTURE AND METHOD FOR PERFORMANCE IMPROVEMENT IN VERTICAL BIPOLAR TRANSISTORS

Patent #:	7446350	Issue Dt:	11/04/2008	Application #:	10908394	Filing Dt:	05/10/2005
Publication #:	US20060255330	Pub Dt:	11/16/2006
Title:	EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER

Patent #:	7132322	Issue Dt:	11/07/2006	Application #:	10908411	Filing Dt:	05/11/2005
Publication #:	US20060258073	Pub Dt:	11/16/2006
Title:	METHOD FOR FORMING A SIGE OR SIGEC GATE SELECTIVELY IN A COMPLEMENTARY MIS/MOS FET DEVICE

Patent #:	7952149	Issue Dt:	05/31/2011	Application #:	10908442	Filing Dt:	05/12/2005
Publication #:	US20060255375	Pub Dt:	11/16/2006
Title:	ANTI-HALO COMPENSATION

Patent #:	7101763	Issue Dt:	09/05/2006	Application #:	10908556	Filing Dt:	05/17/2005
Title:	LOW CAPACITANCE JUNCTION-ISOLATION FOR BULK FINFET TECHNOLOGY

Patent #:	7087966	Issue Dt:	08/08/2006	Application #:	10908583	Filing Dt:	05/18/2005
Title:	DOUBLE-GATE FETS (FIELD EFFECT TRANSISTORS)

Patent #:	7308669	Issue Dt:	12/11/2007	Application #:	10908593	Filing Dt:	05/18/2005
Publication #:	US20060265684	Pub Dt:	11/23/2006
Title:	THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT

Patent #:	7305334	Issue Dt:	12/04/2007	Application #:	10908724	Filing Dt:	05/24/2005
Publication #:	US20060282246	Pub Dt:	12/14/2006
Title:	METHODOLOGY FOR IMAGE FIDELITY VERIFICATION

Patent #:	7319591	Issue Dt:	01/15/2008	Application #:	10908796	Filing Dt:	05/26/2005
Publication #:	US20060268521	Pub Dt:	11/30/2006
Title:	OPTIMIZED THERMALLY CONDUCTIVE PLATE AND ATTACHMENT METHOD FOR ENHANCED THERMAL PERFORMANCE AND RELIABILITY OF FLIP CHIP ORGANIC PACKAGES

Patent #:	7287468	Issue Dt:	10/30/2007	Application #:	10908883	Filing Dt:	05/31/2005
Publication #:	US20060269770	Pub Dt:	11/30/2006
Title:	NICKEL ALLOY PLATED STRUCTURE

Patent #:	7550787	Issue Dt:	06/23/2009	Application #:	10908884	Filing Dt:	05/31/2005
Publication #:	US20060270203	Pub Dt:	11/30/2006
Title:	VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES

Patent #:	7214603	Issue Dt:	05/08/2007	Application #:	10908931	Filing Dt:	06/01/2005
Publication #:	US20060183314	Pub Dt:	08/17/2006
Title:	METHOD FOR FABRICATING INTERCONNECT STRUCTURES WITH REDUCED PLASMA DAMAGE

Patent #:	7173310	Issue Dt:	02/06/2007	Application #:	10908961	Filing Dt:	06/02/2005
Publication #:	US20060273372	Pub Dt:	12/07/2006
Title:	LATERAL LUBISTOR STRUCTURE AND METHOD

Patent #:	7217578	Issue Dt:	05/15/2007	Application #:	10909497	Filing Dt:	08/02/2004
Title:	ADVANCED PROCESS CONTROL OF THERMAL OXIDATION PROCESSES, AND SYSTEMS FOR ACCOMPLISHING SAME

Patent #:	7186650	Issue Dt:	03/06/2007	Application #:	10909509	Filing Dt:	08/02/2004
Title:	CONTROL OF BOTTOM DIMENSION OF TAPERED CONTACT VIA VARIATION(S) OF ETCH PROCESS

Patent #:	7069098	Issue Dt:	06/27/2006	Application #:	10909606	Filing Dt:	08/02/2004
Publication #:	US20060025879	Pub Dt:	02/02/2006
Title:	METHOD AND SYSTEM FOR PRIORITIZING MATERIAL TO CLEAR EXCEPTION CONDITIONS

Patent #:	7295161	Issue Dt:	11/13/2007	Application #:	10912959	Filing Dt:	08/06/2004
Publication #:	US20060028378	Pub Dt:	02/09/2006
Title:	APPARATUS AND METHODS FOR CONSTRUCTING ANTENNAS USING WIRE BONDS AS RADIATING ELEMENTS

Patent #:	7179692	Issue Dt:	02/20/2007	Application #:	10913409	Filing Dt:	08/09/2004
Publication #:	US20050006666	Pub Dt:	01/13/2005
Title:	METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE

Patent #:	7129548	Issue Dt:	10/31/2006	Application #:	10916201	Filing Dt:	08/11/2004
Publication #:	US20060033165	Pub Dt:	02/16/2006
Title:	MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS

Patent #:	7638266	Issue Dt:	12/29/2009	Application #:	10916755	Filing Dt:	08/12/2004
Publication #:	US20060035167	Pub Dt:	02/16/2006
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100

Patent #:	7799517	Issue Dt:	09/21/2010	Application #:	10930432	Filing Dt:	08/31/2004
Title:	SINGLE/DOUBLE DIPOLE MASK FOR CONTACT HOLES

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

440 STONE BREAK ROAD EXTENSION

MALTA, NEW YORK 12020

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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