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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
03/18/2008
Application #:
10992072
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
05/25/2006
Title:
CUT-AND-PASTE IMPRINT LITHOGRAPHIC MOLD AND METHOD THEREFOR
2
Patent #:
Issue Dt:
02/05/2008
Application #:
10992399
Filing Dt:
11/18/2004
Publication #:
Pub Dt:
05/18/2006
Title:
METHOD AND STRUCTURE FOR CREATING PRINTED CIRCUIT BOARDS WITH STEPPED THICKNESS
3
Patent #:
Issue Dt:
09/27/2005
Application #:
10993244
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
04/28/2005
Title:
FULLY-DEPLETED-COLLECTOR SILICON-ON-INSULATOR (SOI) BIPOLAR TRANSISTOR USEFUL ALONE OR IN SOI BICMOS
4
Patent #:
Issue Dt:
01/08/2008
Application #:
10993270
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
04/28/2005
Title:
PATTERNED SOI BY OXYGEN IMPLANTATION AND ANNEALING
5
Patent #:
Issue Dt:
01/03/2012
Application #:
10993305
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
04/14/2005
Title:
OPTICAL ASSEMBLIES FOR TRANSMITTING AND MANIPULATING OPTICAL BEAMS
6
Patent #:
Issue Dt:
10/21/2008
Application #:
10993567
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
06/23/2005
Title:
METHOD FOR ESTIMATING STORAGE REQUIREMENTS FOR A MULTI-DIMENSIONAL CLUSTERING DATA CONFIGURATION
7
Patent #:
Issue Dt:
02/28/2006
Application #:
10993941
Filing Dt:
11/19/2004
Title:
GLOBAL PLANARIZATION OF WAFER SCALE PACKAGE WITH PRECISION DIE THICKNESS CONTROL
8
Patent #:
Issue Dt:
07/29/2008
Application #:
10994494
Filing Dt:
11/20/2004
Publication #:
Pub Dt:
05/25/2006
Title:
METHODS FOR FORMING CO-PLANAR WAFER-SCALE CHIP PACKAGES
9
Patent #:
Issue Dt:
10/28/2008
Application #:
10994574
Filing Dt:
11/22/2004
Publication #:
Pub Dt:
05/25/2006
Title:
METHODS TO ACHIEVE PRECISION ALIGNMENT FOR WAFER SCALE PACKAGES
10
Patent #:
NONE
Issue Dt:
Application #:
10994742
Filing Dt:
11/22/2004
Publication #:
Pub Dt:
05/25/2006
Title:
Timing bias compensation for a data receiver with decision-feedback equalizer
11
Patent #:
Issue Dt:
11/25/2008
Application #:
10996034
Filing Dt:
11/23/2004
Publication #:
Pub Dt:
05/12/2005
Title:
METHOD AND APPARATUS FOR CONTROLLING ETCH SELECTIVITY
12
Patent #:
Issue Dt:
08/15/2006
Application #:
10996284
Filing Dt:
11/22/2004
Publication #:
Pub Dt:
05/25/2006
Title:
SRAM WITH DYNAMICALLY ASYMMETRIC CELL
13
Patent #:
Issue Dt:
06/24/2008
Application #:
10996292
Filing Dt:
11/22/2004
Publication #:
Pub Dt:
05/25/2006
Title:
TECHNIQES FOR SUPER FAST BUFFER INSERTION
14
Patent #:
Issue Dt:
11/13/2007
Application #:
10996293
Filing Dt:
11/22/2004
Publication #:
Pub Dt:
02/09/2006
Title:
CLUSTERING TECHNIQUES FOR FASTER AND BETTER PLACEMENT OF VLSI CIRCUITS
15
Patent #:
Issue Dt:
02/20/2007
Application #:
10996311
Filing Dt:
11/22/2004
Publication #:
Pub Dt:
05/25/2006
Title:
HIGH PERFORMANCE REGISTER FILE WITH BOOTSTRAPPED STORAGE SUPPLY AND METHOD OF READING DATA THEREFORM
16
Patent #:
Issue Dt:
01/29/2008
Application #:
10997597
Filing Dt:
11/24/2004
Publication #:
Pub Dt:
04/28/2005
Title:
SOI DEVICE WITH REDUCED JUNCTION CAPACITANCE
17
Patent #:
Issue Dt:
10/07/2008
Application #:
10998840
Filing Dt:
11/30/2004
Publication #:
Pub Dt:
05/05/2005
Title:
SEMICONDUCTOR STRUCTURE INCLUDING MIXED RARE EARTH OXIDE FORMED ON SILICON
18
Patent #:
Issue Dt:
02/28/2012
Application #:
10999404
Filing Dt:
11/30/2004
Title:
METHOD OF LITHOGRAPHIC MASK CORRECTION USING LOCALIZED TRANSMISSION ADJUSTMENT
19
Patent #:
Issue Dt:
09/11/2007
Application #:
11000062
Filing Dt:
12/01/2004
Title:
ARRANGEMENT FOR RECEIVING AND TRANSMITTING PCI-X DATA ACCORDING TO SELECTED DATA MODES
20
Patent #:
Issue Dt:
10/30/2007
Application #:
11000654
Filing Dt:
12/01/2004
Title:
FRAME STRUCTURE FOR TURBULENCE CONTROL IN IMMERSION LITHOGRAPHY
21
Patent #:
Issue Dt:
11/13/2007
Application #:
11000869
Filing Dt:
12/01/2004
Title:
SYSTEMS AND METHODS OF IMPRINT LITHOGRAPHY WITH ADJUSTABLE MASK
22
Patent #:
Issue Dt:
05/27/2008
Application #:
11001151
Filing Dt:
12/01/2004
Title:
QUANTIFYING AND PREDICTING THE IMPACT OF LINE EDGE ROUGHNESS ON DEVICE RELIABILITY AND PERFORMANCE
23
Patent #:
Issue Dt:
10/09/2007
Application #:
11001483
Filing Dt:
12/01/2004
Title:
METHOD AND APPARATUS TO RECONCILE RECIPE MANAGER AND MANUFACTURING EXECUTION SYSTEM CONTEXT CONFIGURATIONS
24
Patent #:
Issue Dt:
08/16/2011
Application #:
11001491
Filing Dt:
12/01/2004
Title:
WIRELESS MODEM ARCHITECTURE FOR REDUCING MEMORY COMPONENTS
25
Patent #:
Issue Dt:
04/29/2008
Application #:
11002525
Filing Dt:
12/02/2004
Publication #:
Pub Dt:
06/08/2006
Title:
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFICATION OF DIGITAL DESIGNS USING CASE-SPLITTING VIA CONSTRAINED INTERNAL SIGNALS
26
Patent #:
Issue Dt:
10/09/2007
Application #:
11002586
Filing Dt:
12/03/2004
Publication #:
Pub Dt:
06/08/2006
Title:
METHOD FOR FORMING A SEMICONDUCTOR ARRANGEMENT WITH GATE SIDEWALL SPACERS OF SPECIFIC DIMENSIONS
27
Patent #:
Issue Dt:
09/25/2007
Application #:
11002686
Filing Dt:
12/02/2004
Publication #:
Pub Dt:
06/08/2006
Title:
METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR ENHANCING A POWER DISTRIBUTION SYSTEM IN A CERAMIC INTEGRATED CIRCUIT PACKAGE
28
Patent #:
Issue Dt:
05/30/2006
Application #:
11003574
Filing Dt:
12/03/2004
Title:
METHOD FOR FORMING WORDLINES HAVING IRREGULAR SPACING IN A MEMORY ARRAY
29
Patent #:
Issue Dt:
11/07/2006
Application #:
11003988
Filing Dt:
12/04/2004
Publication #:
Pub Dt:
05/12/2005
Title:
METHOD OF ASSESSING POTENTIAL FOR CHARGING DAMAGE IN SOI DESIGNS AND STRUCTURES FOR ELIMINATING POTENTIAL FOR DAMAGE
30
Patent #:
Issue Dt:
07/22/2008
Application #:
11004264
Filing Dt:
12/01/2004
Title:
METHOD AND SYSTEM FOR SELF-ASSEMBLING INSTRUCTION OPCODES FOR A CUSTOM RANDOM FUNCTIONAL TEST OF A MICROPROCESSOR
31
Patent #:
Issue Dt:
08/07/2007
Application #:
11004265
Filing Dt:
12/01/2004
Title:
METHOD AND SYSTEM FOR TESTING A MEMORY OF A MICROPROCESSOR
32
Patent #:
Issue Dt:
06/26/2007
Application #:
11004413
Filing Dt:
12/04/2004
Publication #:
Pub Dt:
06/08/2006
Title:
SYSTEM AND METHOD FOR TRANSFERRING DATA TO AND FROM A MAGNETIC SHIFT REGISTER WITH A SHIFTABLE DATA COLUMN
33
Patent #:
Issue Dt:
05/27/2008
Application #:
11004791
Filing Dt:
12/03/2004
Title:
SILICON-ON-INSULATOR CHIP HAVING AN ISOLATION BARRIER FOR RELIABILITY
34
Patent #:
Issue Dt:
08/14/2012
Application #:
11004845
Filing Dt:
12/07/2004
Publication #:
Pub Dt:
05/05/2005
Title:
SEMICONDUCTOR STRUCTURE HAVING REDUCED AMINE-BASED CONTAMINANTS
35
Patent #:
Issue Dt:
02/26/2008
Application #:
11004846
Filing Dt:
12/07/2004
Publication #:
Pub Dt:
06/09/2005
Title:
METHOD OF MAKING AN ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE
36
Patent #:
Issue Dt:
09/12/2006
Application #:
11004951
Filing Dt:
12/07/2004
Title:
SELECTIVE EPITAXIAL GROWTH FOR TUNABLE CHANNEL THICKNESS
37
Patent #:
Issue Dt:
10/16/2007
Application #:
11005659
Filing Dt:
12/07/2004
Publication #:
Pub Dt:
05/19/2005
Title:
METHOD OF FORMING FET WITH T-SHAPED GATE
38
Patent #:
Issue Dt:
09/09/2008
Application #:
11006747
Filing Dt:
12/08/2004
Publication #:
Pub Dt:
06/08/2006
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE COMPRISING MULTIPLE STACKED HYBRID ORIENTATION LAYERS
39
Patent #:
Issue Dt:
03/04/2008
Application #:
11008877
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
09/15/2005
Title:
TECHNIQUE FOR COMBINING SCAN TEST AND MEMORY BUILT-IN SELF TEST
40
Patent #:
Issue Dt:
10/18/2011
Application #:
11009575
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
07/28/2005
Title:
TECHNIQUE FOR FORMING EMBEDDED METAL LINES HAVING INCREASED RESISTANCE AGAINST STRESS-INDUCED MATERIAL TRANSPORT
41
Patent #:
Issue Dt:
03/04/2008
Application #:
11009825
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
08/04/2005
Title:
METHOD OF DEPOSITING A LAYER OF A MATERIAL ON A SUBSTRATE
42
Patent #:
Issue Dt:
01/22/2008
Application #:
11011245
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD FOR VERIFICATION USING REACHABILITY OVERAPPROXIMATION
43
Patent #:
Issue Dt:
05/06/2008
Application #:
11011246
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD FOR INCREMENTAL DESIGN REDUCTION VIA ITERATIVE OVERAPPROXIMATION AND RE-ENCODING STRATEGIES
44
Patent #:
Issue Dt:
08/14/2007
Application #:
11011511
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
03/02/2006
Title:
MESSAGE BASED INTERRUPT TABLE
45
Patent #:
Issue Dt:
01/27/2009
Application #:
11013728
Filing Dt:
12/16/2004
Publication #:
Pub Dt:
07/07/2005
Title:
MULTI NODAL COMPUTER SYSTEM AND METHOD FOR HANDLING CHECK STOPS IN THE MULTI NODAL COMPUTER SYSTEM
46
Patent #:
Issue Dt:
02/05/2008
Application #:
11013971
Filing Dt:
12/16/2004
Publication #:
Pub Dt:
06/22/2006
Title:
LOW REFRACTIVE INDEX POLYMERS AS UNDERLAYERS FOR SILICON-CONTAINING PHOTORESISTS
47
Patent #:
Issue Dt:
04/07/2009
Application #:
11021525
Filing Dt:
12/23/2004
Publication #:
Pub Dt:
06/29/2006
Title:
GENERATING TESTCASES BASED ON NUMBERS OF TESTCASES PREVIOUSLY GENERATED
48
Patent #:
Issue Dt:
09/05/2006
Application #:
11021681
Filing Dt:
12/23/2004
Title:
MEMORY ELEMENTS USING ORGANIC ACTIVE LAYER
49
Patent #:
Issue Dt:
07/14/2009
Application #:
11023677
Filing Dt:
12/28/2004
Publication #:
Pub Dt:
07/13/2006
Title:
METHODS AND APPARATUS FOR TESTING A MEMORY
50
Patent #:
Issue Dt:
10/27/2009
Application #:
11027980
Filing Dt:
01/03/2005
Title:
ESD PROTECTION CIRCUIT AND METHOD FOR LOWERING CAPACITANCE OF THE ESD PROTECTION CIRCUIT
51
Patent #:
Issue Dt:
11/04/2008
Application #:
11028174
Filing Dt:
01/03/2005
Publication #:
Pub Dt:
07/06/2006
Title:
DIFFERENCE SIGNAL PATH TEST AND CHARACTERIZATION CIRCUIT
52
Patent #:
Issue Dt:
02/08/2011
Application #:
11028798
Filing Dt:
01/04/2005
Publication #:
Pub Dt:
07/06/2006
Title:
METHOD AND APPARATUS FOR DIRECT REFERENCING OF TOP SURFACE OF WORKPIECE DURING IMPRINT LITHOGRAPHY
53
Patent #:
Issue Dt:
07/29/2008
Application #:
11029797
Filing Dt:
01/05/2005
Publication #:
Pub Dt:
07/06/2006
Title:
STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE
54
Patent #:
Issue Dt:
03/10/2009
Application #:
11029884
Filing Dt:
01/05/2005
Publication #:
Pub Dt:
07/06/2006
Title:
METHOD FOR GENERATING DESIGN RULES FOR A LITHOGRAPHIC MASK DESIGN THAT INCLUDES LONG RANGE FLARE EFFECTS
55
Patent #:
Issue Dt:
01/06/2009
Application #:
11029921
Filing Dt:
01/05/2005
Publication #:
Pub Dt:
09/22/2005
Title:
HIGH-QUALITY SGOI BY OXIDATION NEAR THE ALLOY MELTING TEMPERATURE
56
Patent #:
Issue Dt:
07/10/2007
Application #:
11029969
Filing Dt:
01/05/2005
Publication #:
Pub Dt:
06/09/2005
Title:
MANUFACTURING METHODS FOR PRINTED CIRCUIT BOARDS
57
Patent #:
Issue Dt:
10/24/2006
Application #:
11030191
Filing Dt:
01/07/2005
Publication #:
Pub Dt:
06/02/2005
Title:
MULTI-STEP CHEMICAL MECHANICAL POLISHING OF A GATE AREA IN A FINFET
58
Patent #:
Issue Dt:
06/01/2010
Application #:
11030787
Filing Dt:
01/07/2005
Publication #:
Pub Dt:
07/14/2005
Title:
A METHOD OF FORMING A MAGNETIC-FIELD SENSOR HAVING MAGNETIC NANOPARTICLES
59
Patent #:
Issue Dt:
11/20/2007
Application #:
11030863
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
09/01/2005
Title:
METHOD AND SYSTEM FOR CONTROLLING A PRODUCT PARAMETER OF A CIRCUIT ELEMENT
60
Patent #:
Issue Dt:
07/22/2008
Application #:
11031138
Filing Dt:
01/07/2005
Publication #:
Pub Dt:
06/09/2005
Title:
FLEXIBLE ROW REDUNDANCY SYSTEM
61
Patent #:
Issue Dt:
03/20/2012
Application #:
11031165
Filing Dt:
01/07/2005
Publication #:
Pub Dt:
07/13/2006
Title:
QUASI-HYDROPHOBIC SI-SI WAFER BONDING USING HYDROPHILIC SI SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE
62
Patent #:
Issue Dt:
10/06/2009
Application #:
11031168
Filing Dt:
01/07/2005
Publication #:
Pub Dt:
07/13/2006
Title:
SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS
63
Patent #:
Issue Dt:
06/12/2007
Application #:
11031418
Filing Dt:
01/07/2005
Publication #:
Pub Dt:
04/20/2006
Title:
POROUS ORGANOSILICATES WITH IMPROVED MECHANICAL PROPERTIES
64
Patent #:
Issue Dt:
11/20/2007
Application #:
11032878
Filing Dt:
01/11/2005
Publication #:
Pub Dt:
07/13/2006
Title:
PROBABILISTIC CONGESTION PREDICTION WITH PARTIAL BLOCKAGES
65
Patent #:
Issue Dt:
11/03/2009
Application #:
11033641
Filing Dt:
01/13/2005
Title:
BINARY CONTROLLED PHASE SELECTOR WITH OUTPUT DUTY CYCLE CORRECTION
66
Patent #:
Issue Dt:
12/26/2006
Application #:
11033754
Filing Dt:
01/13/2005
Title:
DUAL-MODE OUTPUT DRIVER CONFIGURED FOR OUTPUTTING A SIGNAL ACCORDING TO EITHER A SELECTED HIGH VOLTAGE/LOW SPEED MODE OR A LOW VOLTAGE/HIGH SPEED MODE
67
Patent #:
Issue Dt:
08/14/2007
Application #:
11033755
Filing Dt:
01/13/2005
Title:
ALIGNMENT OF LOCAL TRANSMIT CLOCK TO SYNCHRONOUS DATA TRANSFER CLOCK HAVING PROGRAMMABLE TRANSFER RATE
68
Patent #:
Issue Dt:
11/14/2006
Application #:
11033757
Filing Dt:
01/13/2005
Title:
VOLTAGE MODE TRANSCEIVER HAVING PROGRAMMABLE VOLTAGE SWING AND EXTERNAL REFERENCE-BASED CALIBRATION
69
Patent #:
Issue Dt:
06/17/2008
Application #:
11033926
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
06/09/2005
Title:
CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS
70
Patent #:
Issue Dt:
01/22/2008
Application #:
11034420
Filing Dt:
01/11/2005
Publication #:
Pub Dt:
07/13/2006
Title:
IMPACT CHECKING TECHNIQUE
71
Patent #:
Issue Dt:
04/15/2008
Application #:
11034479
Filing Dt:
01/13/2005
Publication #:
Pub Dt:
02/21/2008
Title:
ULTRALOW DIELECTRIC CONSTANT LAYER WITH CONTROLLED BIAXIAL STRESS
72
Patent #:
Issue Dt:
05/13/2008
Application #:
11034480
Filing Dt:
01/13/2005
Publication #:
Pub Dt:
07/13/2006
Title:
MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SICOH DIELECTRICS
73
Patent #:
Issue Dt:
11/04/2008
Application #:
11036148
Filing Dt:
01/14/2005
Publication #:
Pub Dt:
06/09/2005
Title:
ELECTRONIC COMPONENT AND TAPE HEAD HAVING A CLOSURE
74
Patent #:
Issue Dt:
12/23/2008
Application #:
11037694
Filing Dt:
01/18/2005
Publication #:
Pub Dt:
07/20/2006
Title:
SYSTEMS AND METHODS FOR MANAGING ERROR DEPENDENCIES
75
Patent #:
Issue Dt:
05/22/2007
Application #:
11037913
Filing Dt:
01/18/2005
Publication #:
Pub Dt:
07/20/2006
Title:
HETEROGENEOUS THERMAL INTERFACE FOR COOLING
76
Patent #:
Issue Dt:
07/24/2007
Application #:
11037970
Filing Dt:
01/18/2005
Publication #:
Pub Dt:
07/20/2006
Title:
ON-CHIP CU INTERCONNECTION USING 1 TO 5 NM THICK METAL CAP
77
Patent #:
Issue Dt:
03/21/2006
Application #:
11037995
Filing Dt:
01/18/2005
Publication #:
Pub Dt:
09/15/2005
Title:
LOW-K DIELECTRIC MATERIAL SYSTEM FOR IC APPLICATION
78
Patent #:
Issue Dt:
05/15/2007
Application #:
11038593
Filing Dt:
01/19/2005
Publication #:
Pub Dt:
07/20/2006
Title:
SRAM MEMORIES AND MICROPROCESSORS HAVING LOGIC PORTIONS IMPLEMENTED IN HIGH-PERFORMANCE SILICON SUBSTRATES AND SRAM ARRAY PORTIONS HAVING FIELD EFFECT TRANSISTORS WITH LINKED BODIES AND METHODS FOR MAKING SAME
79
Patent #:
Issue Dt:
07/04/2006
Application #:
11039103
Filing Dt:
01/20/2005
Publication #:
Pub Dt:
10/20/2005
Title:
METHOD OF FORMING A CONDUCTIVE BARRIER LAYER WITHIN CRITICAL OPENINGS BY A FINAL DEPOSITION STEP AFTER A RE-SPUTTER DEPOSITION
80
Patent #:
Issue Dt:
06/05/2007
Application #:
11040139
Filing Dt:
01/21/2005
Publication #:
Pub Dt:
08/24/2006
Title:
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AUTOMATICALLY ESTIMATING PIN LOCATIONS AND INTERCONNECT PARASITICS OF A CIRCUIT LAYOUT
81
Patent #:
Issue Dt:
09/07/2010
Application #:
11042218
Filing Dt:
01/25/2005
Publication #:
Pub Dt:
07/27/2006
Title:
SCRATCH PAD FOR STORING INTERMEDIATE LOOP FILTER DATA
82
Patent #:
Issue Dt:
04/25/2006
Application #:
11042426
Filing Dt:
01/25/2005
Title:
FABRICATION OF DUAL WORK-FUNCTION METAL GATE STRUCTURE FOR COMPLEMENTARY FIELD EFFECT TRANSISTORS
83
Patent #:
Issue Dt:
07/17/2007
Application #:
11042866
Filing Dt:
01/25/2005
Publication #:
Pub Dt:
06/16/2005
Title:
EEPROM DEVICE WITH SUBSTRATE HOT-ELECTRON INJECTOR FOR LOW-POWER PROGRAMMING
84
Patent #:
Issue Dt:
07/07/2009
Application #:
11044346
Filing Dt:
01/27/2005
Publication #:
Pub Dt:
08/04/2005
Title:
STORAGE DEVICE HAVING FLEXIBLE ARCHITECTURE AND FREE SCALABILITY
85
Patent #:
Issue Dt:
03/17/2009
Application #:
11044885
Filing Dt:
01/27/2005
Publication #:
Pub Dt:
07/27/2006
Title:
SELECTIVE PLACEMENT OF CARBON NANOTUBES ON OXIDE SURFACES
86
Patent #:
Issue Dt:
04/15/2014
Application #:
11046986
Filing Dt:
01/31/2005
Publication #:
Pub Dt:
11/03/2005
Title:
Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging
87
Patent #:
Issue Dt:
01/01/2008
Application #:
11047129
Filing Dt:
01/31/2005
Publication #:
Pub Dt:
12/01/2005
Title:
TECHIQUE FOR CONTROLLING MECHANICAL STRESS IN A CHANNEL REGION BY SPACER REMOVAL
88
Patent #:
Issue Dt:
08/25/2009
Application #:
11047250
Filing Dt:
01/31/2005
Publication #:
Pub Dt:
08/03/2006
Title:
METHOD AND APPARATUS TO SEPARATE MOLECULES ACCORDING TO THEIR MOBILITIES
89
Patent #:
Issue Dt:
03/11/2008
Application #:
11048001
Filing Dt:
01/31/2005
Publication #:
Pub Dt:
08/03/2006
Title:
TECHNIQUES SUPPORTING COLLABORATIVE PRODUCT DEVELOPMENT
90
Patent #:
Issue Dt:
02/19/2008
Application #:
11048578
Filing Dt:
02/01/2005
Publication #:
Pub Dt:
02/16/2006
Title:
FLUXLESS SOLDER TRANSFER AND REFLOW PROCESS
91
Patent #:
Issue Dt:
06/21/2011
Application #:
11048739
Filing Dt:
02/03/2005
Publication #:
Pub Dt:
07/28/2005
Title:
STRAINED SILICON ON RELAXED SIGE FILM WITH UNIFORM MISFIT DISLOCATION DENSITY
92
Patent #:
Issue Dt:
01/04/2011
Application #:
11049855
Filing Dt:
02/04/2005
Title:
NON-VOLATILE MEMORY DEVICE WITH IMPROVED ERASE SPEED
93
Patent #:
Issue Dt:
10/16/2007
Application #:
11050232
Filing Dt:
02/03/2005
Publication #:
Pub Dt:
08/24/2006
Title:
METHOD FOR RECONFIGURATION OF RANDOM BIASES IN A SYNTHESIZED DESIGN WITHOUT RECOMPILATION
94
Patent #:
Issue Dt:
01/11/2011
Application #:
11050325
Filing Dt:
02/03/2005
Publication #:
Pub Dt:
08/03/2006
Title:
METHOD AND APPARATUS FOR FREQUENCY INDEPENDENT PROCESSOR UTILIZATION RECORDING REGISTER IN A SIMULTANEOUSLY MULTI-THREADED PROCESSOR
95
Patent #:
Issue Dt:
08/21/2007
Application #:
11050572
Filing Dt:
02/03/2005
Publication #:
Pub Dt:
02/23/2006
Title:
INTEGRATED CIRCUIT WITH INCREASED HEAT TRANSFER
96
Patent #:
Issue Dt:
10/30/2007
Application #:
11050592
Filing Dt:
02/03/2005
Publication #:
Pub Dt:
08/24/2006
Title:
METHOD AND SYSTEM FOR OPTIMIZED HANDLING OF CONSTRAINTS DURING SYMBOLIC SIMULATION
97
Patent #:
Issue Dt:
09/02/2008
Application #:
11050602
Filing Dt:
02/03/2005
Publication #:
Pub Dt:
08/03/2006
Title:
METHOD FOR BALANCING POWER PLANE PIN CURRENTS IN A PRINTED WIRING BOARD USING COLLINEAR SLOTS
98
Patent #:
Issue Dt:
05/06/2008
Application #:
11050790
Filing Dt:
01/27/2005
Publication #:
Pub Dt:
07/27/2006
Title:
GATE STACK ENGINEERING BY ELECTROCHEMICAL PROCESSING UTILIZING THROUGH-GATE-DIELECTRIC CURRENT FLOW
99
Patent #:
Issue Dt:
05/08/2007
Application #:
11051703
Filing Dt:
02/04/2005
Publication #:
Pub Dt:
06/23/2005
Title:
ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH
100
Patent #:
Issue Dt:
11/20/2007
Application #:
11052675
Filing Dt:
02/07/2005
Publication #:
Pub Dt:
07/07/2005
Title:
METHOD OF MAKING STRAINED CHANNEL CMOS TRANSISTORS HAVING LATTICE-MISMATCHED EPITAXIAL EXTENSION AND SOURCE AND DRAIN REGIONS
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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