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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
05/18/1999
Application #:
08732951
Filing Dt:
10/17/1996
Title:
SET-ASSOCIATIVE CACHE MEMORY UTILIZING A SINGLE BANK OF PHYSICAL MEMORY
2
Patent #:
Issue Dt:
11/03/1998
Application #:
08733998
Filing Dt:
10/18/1996
Title:
ENABLING PCI CONFIGURATION SPACE FOR MULTIPLE FUNCTIONS
3
Patent #:
Issue Dt:
09/08/1998
Application #:
08735463
Filing Dt:
10/23/1996
Title:
METHOD OF MAKING A SELECTIVE EPITAXIAL GROWTH CIRCUIT LOAD ELEMENT
4
Patent #:
Issue Dt:
10/20/1998
Application #:
08735464
Filing Dt:
10/23/1996
Title:
METHOD OF MANUFACTURING A RAISED SOURCE/DRAIN MOSFET
5
Patent #:
Issue Dt:
04/13/1999
Application #:
08735466
Filing Dt:
10/23/1996
Title:
ADDRESS PATH ARCHITECTURE
6
Patent #:
Issue Dt:
09/19/2000
Application #:
08735683
Filing Dt:
10/23/1996
Title:
BUS BRIDGE WITH UNIFIED SERIAL BUS CONTROLLER HAVING POWER MANAGEMENT CAPABILITIES
7
Patent #:
Issue Dt:
05/26/1998
Application #:
08736623
Filing Dt:
10/24/1996
Title:
IDDQ TESTING OF INTEGRATED CIRCUITS
8
Patent #:
Issue Dt:
06/08/1999
Application #:
08736920
Filing Dt:
10/25/1996
Title:
METHOD FOR PERFORMING FLOORPLAN TIMING ANALYSIS USING MULTI-DIMENSIONAL FEEDBACK IN A SPREADSHEET WITH COMPUTED HYPERLINKS TO PHYSICAL LAYOUT GRAPHICS AND INTEGRATED CIRCUIT MADE USING SAME
9
Patent #:
Issue Dt:
04/20/1999
Application #:
08736928
Filing Dt:
10/25/1996
Title:
METHOD FOR PERFORMING FLOORPLAN TIMING ANALYSIS USING MULTI-DIMENSIONAL FEEDBACK IN A HISTOGRAM AND INTEGRATED CIRCUIT MADE USING SAME
10
Patent #:
Issue Dt:
05/11/1999
Application #:
08738301
Filing Dt:
10/25/1996
Title:
METHOD FOR PERFORMING FLOORPLAN TIMING ANALYSIS BY SELECTIVELY DISPLAYING SIGNAL PATHS BASED ON SLACK TIME CALCULATIONS AND INTEGRATED CIRCUIT MADE USING SAME
11
Patent #:
Issue Dt:
06/16/1998
Application #:
08739133
Filing Dt:
10/28/1996
Title:
INTEGRATED CIRCUIT AND PROCESS FOR ITS MANUFACTURE
12
Patent #:
Issue Dt:
06/30/1998
Application #:
08739137
Filing Dt:
10/28/1996
Title:
METHOD FOR CORRECTING PLACEMENT ERRORS IN A LITHOGRAPHY SYSTEM
13
Patent #:
Issue Dt:
09/11/2001
Application #:
08739343
Filing Dt:
10/28/1996
Title:
INTERCONNECTOR WITH CONTACT PADS HAVING ENHANCED DURABILITY
14
Patent #:
Issue Dt:
07/14/1998
Application #:
08739566
Filing Dt:
10/30/1996
Title:
METHOD OF FORMING TRENCH TRANSISTOR AND ISOLATION TRENCH
15
Patent #:
Issue Dt:
09/01/1998
Application #:
08739593
Filing Dt:
10/30/1996
Title:
METHOD OF FORMING TRENCH TRANSISTOR WITH METAL SPACERS
16
Patent #:
Issue Dt:
08/08/2000
Application #:
08739595
Filing Dt:
10/30/1996
Title:
METHOD OF FORMING A TRENCH TRANSISTOR WITH INSULATIVE SPACERS
17
Patent #:
Issue Dt:
03/30/1999
Application #:
08739596
Filing Dt:
10/30/1996
Title:
TRENCH TRANSISTOR WITH LOCALIZED SOURCE/DRAIN REGIONS IMPLANTED THROUGH SELECTIVELY GROWN OXIDE LAYER
18
Patent #:
Issue Dt:
04/10/2001
Application #:
08740017
Filing Dt:
10/23/1996
Title:
NOISE ELIMINATION IN A USB CODEC
19
Patent #:
Issue Dt:
06/22/1999
Application #:
08740019
Filing Dt:
10/23/1996
Title:
USB BASED MICROPHONE SYSTEM
20
Patent #:
Issue Dt:
11/10/1998
Application #:
08740119
Filing Dt:
10/23/1996
Title:
HIERARCHICAL SCAN LOGIC FOR OUT-OF-ORDER LOAD/STORE EXECUTION CONTROL
21
Patent #:
Issue Dt:
02/22/2000
Application #:
08740744
Filing Dt:
11/04/1996
Title:
A SYSTEM AND METHOD FOR NON-SEQUENTIAL PROGRAM STATEMENT EXECUTION WITH INCOMPLETE RUNTIME INFORMATION
22
Patent #:
Issue Dt:
07/13/1999
Application #:
08741159
Filing Dt:
10/29/1996
Title:
METHOD OF CONTROLLING DOPANT DIFFUSION AND METAL CONTAMINATION IN THIN POLYCIDE GATE CONDUCTOR OF MOSFET DEVICE
23
Patent #:
Issue Dt:
09/22/1998
Application #:
08742221
Filing Dt:
10/31/1996
Title:
CACHE SUB-ARRAY METHOD AND APPARATUS FOR USE IN MICROPROCESSOR INTEGRATED CIRCUITS
24
Patent #:
Issue Dt:
03/09/2004
Application #:
08743049
Filing Dt:
09/16/1996
Title:
OPTIMIZED MII FOR 802.3U (100 BASE-T) FAST ETHERNET PHYS
25
Patent #:
Issue Dt:
06/09/1998
Application #:
08743522
Filing Dt:
11/04/1996
Title:
HIGH PERFORMANCE ASYMMETRICAL MOSFET STRUCTURE AND METHOD OF MAKING THE SAME
26
Patent #:
Issue Dt:
12/07/1999
Application #:
08745475
Filing Dt:
11/12/1996
Title:
SILICIDATION AND DEEP SOURCE-DRAIN FORMATION PRIOR TO SOURCE-DRAIN EXTENSION FORMATION
27
Patent #:
Issue Dt:
04/15/2003
Application #:
08745584
Filing Dt:
11/07/1996
Title:
EFFICIENT, FLEXIBLE MOTION ESTIMATION ARCHITECTURE FOR REAL TIME MPEG2 COMPLIANT ENCODING
28
Patent #:
Issue Dt:
04/14/1998
Application #:
08746915
Filing Dt:
11/19/1996
Title:
LOW-VOLTAGE RAIL-TO-RAIL OPERATIONAL AMPLIFIER
29
Patent #:
Issue Dt:
06/15/1999
Application #:
08748815
Filing Dt:
11/14/1996
Title:
ALTERNATIVE PROCESS FOR BPTEOS/BPSG LAYER FORMATION
30
Patent #:
Issue Dt:
07/14/1998
Application #:
08751465
Filing Dt:
11/19/1996
Title:
PAGE BOUNDARY CACHES
31
Patent #:
Issue Dt:
10/29/2002
Application #:
08752100
Filing Dt:
11/20/1996
Title:
METHOD FOR CONTROLLING A MANUFACTURING PROCESS UTILIZING CONTROL CHARTS WITH SPECIFIED CONFIDENCE INTERVALS
32
Patent #:
Issue Dt:
04/25/2000
Application #:
08752469
Filing Dt:
11/19/1996
Title:
FOAMED ELASTOMERS FOR WAFER PROBING APPLICATIONS AND INTERPOSER CONNECTORS
33
Patent #:
Issue Dt:
04/27/1999
Application #:
08752647
Filing Dt:
11/19/1996
Title:
MULTIMEDIA DEVICES IN COMPUTER SYSTEM THAT SELECTIVELY EMPLOY A COMMUNICATIONS PROTOCOL BY DETERMINING THE PRESENCE OF THE QUATERNARY INTERFACE
34
Patent #:
Issue Dt:
11/30/1999
Application #:
08752691
Filing Dt:
11/19/1996
Title:
BRANCH PREDICTION MECHANISM EMPLOYING BRANCH SELECTORS TO SELECT A BRANCH PREDICTION
35
Patent #:
Issue Dt:
08/18/1998
Application #:
08752807
Filing Dt:
11/20/1996
Title:
SELF ALIGNED VIA DUAL DAMASCENE
36
Patent #:
Issue Dt:
02/15/2000
Application #:
08753137
Filing Dt:
11/20/1996
Title:
REDUNDANT VIAS
37
Patent #:
Issue Dt:
03/26/2002
Application #:
08754564
Filing Dt:
11/21/1996
Title:
BORDERLESS VIAS ON BOTTOM METAL
38
Patent #:
Issue Dt:
10/20/1998
Application #:
08756360
Filing Dt:
11/27/1996
Title:
DIGITALLY STEPPED DEFLECTION RASTER SYSTEM AND METHOD OF USE THEREOF
39
Patent #:
Issue Dt:
08/29/2000
Application #:
08756361
Filing Dt:
11/27/1996
Title:
DUAL-VALENT RARE EARTH ADDITIVES TO POLISHING SLURRIES
40
Patent #:
Issue Dt:
07/14/1998
Application #:
08756494
Filing Dt:
11/26/1996
Title:
ADJUSTABLE BLADE RETICLE ASSEMBLY
41
Patent #:
Issue Dt:
04/06/1999
Application #:
08757115
Filing Dt:
12/02/1996
Title:
SYSTEM AND METHOD FOR ROUTING OPERANDS WITHIN PARTITIONS OF A SOURCE REGISTER TO PARTITIONS WITHIN A DESTINATION REGISTER
42
Patent #:
Issue Dt:
06/01/1999
Application #:
08759025
Filing Dt:
12/02/1996
Title:
SYSTEM AND METHOD FOR CONDITIONALLY MOVING AN OPERAND FROM A SOURCE REGISTER TO A DESTINATION REGISTER
43
Patent #:
Issue Dt:
11/24/1998
Application #:
08760029
Filing Dt:
12/04/1996
Title:
INDIVIDUALLY CONTROLLABLE RADIATION SOURCES FOR PROVIDING AN IMAGE PATTERN IN A PHOTOLITHOGRAPHIC SYSTEM
44
Patent #:
Issue Dt:
03/30/1999
Application #:
08760031
Filing Dt:
12/04/1996
Title:
METHOD OF MAKING RETICLE THAT COMPENSATES FOR RADIATION-INDUCED LENS ERROR IN A PHOTOLITHOGRAPHIC SYSTEM
45
Patent #:
Issue Dt:
10/19/1999
Application #:
08760723
Filing Dt:
12/05/1996
Title:
SEMICONDUCTOR DEVICE HAVING A THIN GATE OXIDE AND METHOD OF MANUFACTURE THEREOF
46
Patent #:
Issue Dt:
02/06/2001
Application #:
08761027
Filing Dt:
12/05/1996
Title:
MULTILAYER PRINTED CIRCUIT BOARD HAVING A CONCAVE METAL PORTION
47
Patent #:
Issue Dt:
04/25/2000
Application #:
08761332
Filing Dt:
12/10/1996
Title:
TRANSISTOR AND PROCESS OF MAKING A TRANSISTOR HAVING AN IMPROVED LDD MASKING MATERIAL
48
Patent #:
Issue Dt:
06/16/1998
Application #:
08761398
Filing Dt:
12/06/1996
Title:
NULTIPLE SPACER FORMATION/REMOVAL TECHNIQUE FOR FORMING A GRADED JUNCTION
49
Patent #:
Issue Dt:
06/22/1999
Application #:
08761586
Filing Dt:
12/06/1996
Title:
MULTIPLE BUS MASTER COMPUTER SYSTEM EMPLOYING A SHARED ADDRESS TRANSLATION UNIT
50
Patent #:
Issue Dt:
03/07/2000
Application #:
08761890
Filing Dt:
12/09/1996
Title:
IDENTIFYING CANDIDATE NODES FOR PHASE ASSIGNMENT IN A LOGIC NETWORK
51
Patent #:
Issue Dt:
05/11/1999
Application #:
08763980
Filing Dt:
12/10/1996
Title:
SELECTING PHASE ASSIGNMENTS FOR CANDIDATE NODES IN A LOGIC NETWORK
52
Patent #:
Issue Dt:
07/28/1998
Application #:
08764212
Filing Dt:
12/13/1996
Title:
MULTIPLE PARALLEL IDENTICAL FINITE STATE MACHINES WHICH SHARE COMBINATORIAL LOGIC
53
Patent #:
Issue Dt:
10/05/1999
Application #:
08766259
Filing Dt:
12/13/1996
Title:
PHOTORESIST COMPOSITION COMPRISING A COPOLYMER OF A HYDROXYSTYRENE AND A (METH) ACRYLATE SUBSTITUTED WITH AN ALICYCLIC ESTER SUBSTITUENT
54
Patent #:
Issue Dt:
07/28/1998
Application #:
08767465
Filing Dt:
12/16/1996
Title:
ELECTRONIC PACKAGE WITH COMPRESSIBLE HEATSINK STRUCTURE
55
Patent #:
Issue Dt:
06/30/1998
Application #:
08767916
Filing Dt:
12/17/1996
Title:
METHOD FOR MAKING SINGLE AND DOUBLE GATE FIELD EFFECT TRANSISTORS WITH SIDEWALL SOURCE-DRAIN CONTACTS
56
Patent #:
Issue Dt:
06/16/1998
Application #:
08768010
Filing Dt:
12/13/1996
Title:
OXIDE STRIP THAT IMPROVES PLANARITY
57
Patent #:
Issue Dt:
12/08/1998
Application #:
08769009
Filing Dt:
12/20/1996
Title:
NON-VOLATILE MEMORY ARRAY THAT ENABLES SIMULTANEOUS READ AND WRITE OPERATIONS
58
Patent #:
Issue Dt:
10/27/1998
Application #:
08769065
Filing Dt:
12/18/1996
Title:
LATCHUP-PROOF I/O CIRCUIT IMPLEMENTATION
59
Patent #:
Issue Dt:
04/20/1999
Application #:
08770012
Filing Dt:
12/19/1996
Title:
COMPUTER SYSTEM AND METHOD FOR IMPLEMENTING DELAY-BASED EFFECTS USING SYSTEM MEMORY
60
Patent #:
Issue Dt:
07/07/1998
Application #:
08770016
Filing Dt:
12/19/1996
Title:
METHOD AND APPARATUS FOR CLOCK SYNCHRONIZATION ACROSS AN ISOCHRONOUS BUS BY ADJUSTMENT OF FRAME CLOCK RATES
61
Patent #:
Issue Dt:
08/04/1998
Application #:
08770364
Filing Dt:
12/20/1996
Title:
SYSTEM INTEGRATION OF DRAM MACROS AND LOGIC CORES IN A SINGLE CHIP ARCHITECTURE
62
Patent #:
Issue Dt:
08/18/1998
Application #:
08771131
Filing Dt:
12/20/1996
Title:
SEMICONDUCTOR DEVICE HAVING A GROUP OF HIGH PERFORMANCE TRANSISTORS AND METHOD OF MANUFACTURE THEREOF
63
Patent #:
Issue Dt:
06/09/1998
Application #:
08772841
Filing Dt:
12/24/1996
Title:
METHOD OF MAKING A MACHINE STRUCTURES FABRICATED OF MULTIPLE MICRO- STRUCTURE LAYERS
64
Patent #:
Issue Dt:
03/02/1999
Application #:
08774581
Filing Dt:
12/31/1996
Title:
VIRTUAL HARD MASK FOR ETCHING
65
Patent #:
Issue Dt:
11/02/1999
Application #:
08775262
Filing Dt:
02/04/1997
Title:
SYSTEM FOR PERFORMING DMA TRANSFERS WHERE AN INTERRUPT REQUEST SIGNAL IS GENERATED BASED ON THE LAST OF A PLURALITY OF DATA BITS TRANSMITTED
66
Patent #:
Issue Dt:
09/08/1998
Application #:
08780615
Filing Dt:
01/08/1997
Title:
SEMICONDUCTOR DEVICE HAVING REDUCED OVERLAP CAPACITANCE AND METHOD OF MANUFACTURE THEREOF
67
Patent #:
Issue Dt:
11/10/1998
Application #:
08781301
Filing Dt:
01/13/1997
Title:
CROSS-LINKED BIOBASED MATERIALS AND USES THEREOF
68
Patent #:
Issue Dt:
08/11/1998
Application #:
08781443
Filing Dt:
01/10/1997
Title:
GRADED MOS TRANSISTOR JUNCTION FORMED BY ALIGNING A SEQUENCE OF IMPLANTS TO A SELECTIVELY REMOVABLE POLYSILICON SIDEWALL SPACE AND OXIDE THERMALLY GROWN THEREON
69
Patent #:
Issue Dt:
08/11/1998
Application #:
08781445
Filing Dt:
01/10/1997
Title:
INTEGRATED CIRCUIT HAVING MULTIPLE LDD AND/OR SOURCE/DRAIN IMPLANT STEPS TO ENHANCE CIRCUIT PERFORMANCE
70
Patent #:
Issue Dt:
11/17/1998
Application #:
08781461
Filing Dt:
01/10/1997
Title:
CMOS INTEGRATED CIRCUIT FORMED BY USING REMOVABLE SPACERS TO PRODUCE ASYMMETRICAL NMOS JUNCTIONS BEFORE ASYMMETRICAL PMOS JUNCTIONS FOR OPTIMIZING THERMAL DIFFUSIVITY OF DOPANTS IMPLANTED THEREIN
71
Patent #:
Issue Dt:
09/22/1998
Application #:
08781966
Filing Dt:
12/20/1996
Title:
INTEGRATED HIGH-PERFORMANCE DECOUPLING CAPACITOR
72
Patent #:
Issue Dt:
08/03/1999
Application #:
08782271
Filing Dt:
01/13/1997
Title:
ADAPTIVE PRIORITY DETERMINATION FOR SERVICING TRANSMIT AND RECEIVE IN NETWORK CONTROLLERS
73
Patent #:
Issue Dt:
03/30/1999
Application #:
08782462
Filing Dt:
01/10/1997
Title:
BULK SILICON VOLTAGE PLANE FOR SOI APPLICATIONS
74
Patent #:
Issue Dt:
05/18/1999
Application #:
08783887
Filing Dt:
01/16/1997
Title:
SYSTEM AND METHOD OF ROUTING COMMUNICATIONS DATA WITH MULTIPLE PROTOCOLS USING CROSSBAR SWITCHES
75
Patent #:
Issue Dt:
06/16/1998
Application #:
08784619
Filing Dt:
01/21/1997
Title:
CHEMICAL-MECHANICAL POLISHING USING CURVED CARRIERS
76
Patent #:
Issue Dt:
05/18/1999
Application #:
08785213
Filing Dt:
01/17/1997
Title:
METHOD OF FORMING ASYMMETRICALLY DOPED SOURCE/DRAIN REGIONS
77
Patent #:
Issue Dt:
03/02/1999
Application #:
08785355
Filing Dt:
01/17/1997
Title:
METHOD OF FORMING ULTRA-THIN OXIDES WITH LOW TEMPERATURE OXIDATION
78
Patent #:
Issue Dt:
01/11/2000
Application #:
08785389
Filing Dt:
01/21/1997
Title:
ORGANIZATION OF AN INTEGRATED CACHE UNIT FOR FLEXIBLE USAGE IN SUPPORTING MULTIPROCESSOR OPERATIONS
79
Patent #:
Issue Dt:
10/03/2000
Application #:
08785491
Filing Dt:
01/17/1997
Title:
INSTALLING OPERATING SYSTEMS CHANGES ON A COMPUTER SYSTEM
80
Patent #:
Issue Dt:
02/01/2000
Application #:
08785909
Filing Dt:
01/21/1997
Title:
METHOD AND SYSTEM FOR USING N2 PLASMA TREATMENT TO ELIMINATE THE OUTGASSING DEFECTS AT THE INTERFACE OF A STOP LAYER AND AN OXIDE LAYER
81
Patent #:
Issue Dt:
06/15/1999
Application #:
08786004
Filing Dt:
01/21/1997
Title:
METHOD FOR FABRICATING COOPER-ALUMINUM METALLIZATION
82
Patent #:
Issue Dt:
12/26/2000
Application #:
08786061
Filing Dt:
01/21/1997
Title:
METHODS FOR REPAIR OF PHOTOMASKS
83
Patent #:
Issue Dt:
08/11/1998
Application #:
08786428
Filing Dt:
01/21/1997
Title:
STATIC RANDOM ACCESS MEMORY CELL UTILIZING ENHANCEMENT MODE N-CHANNEL TRANSISTORS AS LOAD ELEMENTS
84
Patent #:
Issue Dt:
02/22/2000
Application #:
08787036
Filing Dt:
01/28/1997
Title:
METHOD OF MAKING AN IGFET WITH A NON-UNIFORM LATERAL DOPING PROFILE IN THE CHANNEL REGION
85
Patent #:
Issue Dt:
04/21/1998
Application #:
08787069
Filing Dt:
01/22/1997
Title:
HEATER FOR MEMBRANE MASK IN AN ELECTRON-BEAM LITHOGRAPHY SYSTEM
86
Patent #:
Issue Dt:
11/30/1999
Application #:
08787152
Filing Dt:
01/31/1997
Title:
REVERSIBLE MEDIA INDEPENDENT CIRCUIT
87
Patent #:
Issue Dt:
05/05/1998
Application #:
08788124
Filing Dt:
01/23/1997
Title:
METHOD AND APPARATUS FOR WAFER-FOCUSING
88
Patent #:
Issue Dt:
04/27/1999
Application #:
08788509
Filing Dt:
01/24/1997
Title:
HYBRID ORGANIC-INORGANIC SEMICONDUCTOR LIGHT EMITTING DIODES
89
Patent #:
Issue Dt:
06/16/1998
Application #:
08789599
Filing Dt:
01/24/1997
Title:
SURFACE CONDITIONING INSULATING LAYER FOR FINE LINE CONDUCTIVE PATTERN
90
Patent #:
Issue Dt:
10/06/1998
Application #:
08789978
Filing Dt:
01/28/1997
Title:
PERFORMING CHEMICAL MECHANICAL POLISHING OF OXIDES AND METALS USING SEQUENTIAL REMOVAL ON MULTIPLE POLISH PLATENS TO INCREASE EQUIPMENT THROUGHPUT
91
Patent #:
Issue Dt:
08/25/1998
Application #:
08790245
Filing Dt:
01/28/1997
Title:
POLYTETRAFLUOROETHYLENE THIN FILM CHIP CARRIER
92
Patent #:
Issue Dt:
04/06/1999
Application #:
08790393
Filing Dt:
01/29/1997
Title:
DISTRIBUTED GATED CLOCK DRIVER
93
Patent #:
Issue Dt:
10/13/1998
Application #:
08790394
Filing Dt:
01/29/1997
Title:
METHOD AND APPARATUS FOR PREDECODING VARIABLE BYTE-LENGTH INSTRUCTIONS WITHIN A SUPERSCALAR MICROPROCESSOR
94
Patent #:
Issue Dt:
07/14/1998
Application #:
08790886
Filing Dt:
02/03/1997
Title:
BACKSIDE WAFER POLISHING FOR IMPROVED PHOTOLITHOGRAPHY
95
Patent #:
Issue Dt:
12/22/1998
Application #:
08792714
Filing Dt:
01/30/1997
Title:
SEMICONDUCTOR GATE CONDUCTOR WITH A SUBSTANTIALLY UNIFORM DOPING PROFILE HAVING MINIMAL SUSCEPTIBILITY TO DOPANT PENETRATION INTO THE UNDERLYING GATE DIELECTRIC
96
Patent #:
Issue Dt:
07/14/1998
Application #:
08794526
Filing Dt:
02/03/1997
Title:
INTERRUPT TRANSMISSION VIA SPECIALIZED BUS CYCLE WITHIN A SYMMETRICAL MULTIPROCESSING SYSTEM
97
Patent #:
Issue Dt:
06/09/1998
Application #:
08797434
Filing Dt:
02/10/1997
Title:
RESYNCHRONIZATION OF A SUPERSCALAR PROCESSOR
98
Patent #:
Issue Dt:
01/19/1999
Application #:
08798249
Filing Dt:
02/11/1997
Title:
"MICROCONTROLLER WITH IMPROVED DEBUG CAPABILITY FOR INTERNAL MEMORY"
99
Patent #:
Issue Dt:
01/18/2000
Application #:
08798581
Filing Dt:
02/10/1997
Title:
METHOD OF FABRICATING CMOS DEVICES WITH ULTRA-SHALLOW JUNCTIONS AND REDUCED DRAIN AREA
100
Patent #:
Issue Dt:
06/29/1999
Application #:
08798991
Filing Dt:
02/11/1997
Title:
POWER SUPPLY SOLUTION FOR MIXED SIGNAL CIRCUITS
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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