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06/15/2010
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01/15/2009
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12/29/2009
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07/11/2007
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06/05/2008
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01/13/2009
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11776710
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07/12/2007
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01/15/2009
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PROCESS FOR FINFET SPACER FORMATION
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12/21/2010
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11776738
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11/08/2007
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09/13/2011
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11776810
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07/12/2007
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01/15/2009
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DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA
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02/22/2011
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11776986
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07/12/2007
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01/15/2009
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MECHANISM FOR USING PERFORMANCE COUNTERS TO IDENTIFY REASONS AND DELAY TIMES FOR INSTRUCTIONS THAT ARE STALLED DURING RETIREMENT
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06/16/2009
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11777329
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07/13/2007
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01/15/2009
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APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PRODUCED BY AN INTEGRATED CIRCUIT
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02/08/2011
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11777837
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07/13/2007
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01/15/2009
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THERMALLY PUMPED LIQUID/GAS HEAT EXCHANGER FOR COOLING HEAT-GENERATING DEVICES
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03/29/2011
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07/16/2007
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01/22/2009
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ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
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06/08/2010
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11778209
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07/16/2007
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01/22/2009
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GRAPHENE-BASED TRANSISTOR
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04/06/2010
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11778217
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07/16/2007
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01/22/2009
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04/29/2014
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11778238
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07/16/2007
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01/17/2008
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METHOD FOR FABRICATING A NITRIDED SILICON-OXIDE GATE DIELECTRIC
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08/31/2010
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11778644
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07/16/2007
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05/29/2008
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AUTONOMIC PARITY EXCHANGE
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05/18/2010
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11778852
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07/17/2007
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01/22/2009
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INVERSE SELF-ALIGNED SPACER LITHOGRAPHY
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10/12/2010
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11778876
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07/17/2007
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01/22/2009
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INTEGRATED WAFER PROCESSING SYSTEM FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS
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02/18/2014
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11778930
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07/17/2007
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07/31/2008
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METHOD FOR FORMING SILICON/GERMANIUM CONTAINING DRAIN/SOURCE REGIONS IN TRANSISTORS WITH REDUCED SILICON/GERMANIUM LOSS
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04/19/2011
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11780283
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07/19/2007
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01/22/2009
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SPECULATIVE MEMORY PREFETCH
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03/15/2011
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11780519
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07/20/2007
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01/22/2009
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THIN GATE ELECTRODE CMOS DEVICES AND METHODS OF FABRICATING SAME
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09/13/2011
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11780530
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07/20/2007
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01/22/2009
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METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT
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10/19/2010
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11780712
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07/20/2007
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01/31/2008
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ARCHITECTURAL LEVEL THROUGHPUT BASED POWER MODELING METHODOLOGY AND APPARATUS FOR PERVASIVELY CLOCK-GATED PROCESSOR CORES
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10/11/2011
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11781363
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07/23/2007
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01/29/2009
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MODELING HOMOGENEOUS PARALLELISM
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07/15/2008
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11781370
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07/23/2007
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11/15/2007
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ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
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10/11/2011
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11781833
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07/23/2007
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12/13/2007
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METHODS OF CREATING A DICTIONARY FOR DATA COMPRESSION
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04/28/2009
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11781850
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07/23/2007
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12/13/2007
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CABLE HAVING TRANSLUCENT, SEMI-TRANSPARENT OR TRANSPARENT ESD DISSIPATIVE LAYER AND/OR METALLIC LAYER
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07/06/2010
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11782071
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07/24/2007
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01/29/2009
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HALF-SELECT COMPLIANT MEMORY CELL PRECHARGE CIRCUIT
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12/28/2010
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11782079
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07/24/2007
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01/29/2009
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PARTIALLY GATED FINFET WITH GATE DIELECTRIC ON ONLY ONE SIDEWALL
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04/27/2010
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11782734
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07/25/2007
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07/03/2008
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TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS WITH INCREASED ROBUSTNESS WITH RESPECT TO BARRIER DEFECTS IN VIAS
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NONE
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11782987
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07/25/2007
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07/31/2008
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METHOD OF FORMING A METAL LAYER OVER A PATTERNED DIELECTRIC BY ELECTROLESS DEPOSITION USING A SELECTIVELY PROVIDED ACTIVATION LAYER
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10/19/2010
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11788215
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04/18/2007
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10/23/2008
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TOKEN BASED POWER CONTROL MECHANISM
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06/23/2009
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11789902
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04/25/2007
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08/30/2007
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FLUORINATED SILSESQUIOXANE POLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
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02/12/2013
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11796073
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04/26/2007
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10/30/2008
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MEMORY DEVICE WITH IMPROVED PERFORMANCE
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06/17/2008
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11799261
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04/10/2007
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09/20/2007
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INTEGRATION OF STRAINED GE INTO ADVANCED CMOS TECHNOLOGY
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11/26/2013
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11811418
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06/07/2007
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12/11/2008
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METHOD FOR DEPOSITING A CONDUCTIVE CAPPING LAYER ON METAL LINES
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01/04/2011
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11819748
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06/28/2007
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09/04/2008
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SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION
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03/25/2008
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11820713
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06/19/2007
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10/25/2007
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METHOD OF FORMING SILICON-ON-INSULATOR WAFER HAVING REENTRANT SHAPE DIELECTRIC TRENCHES
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07/01/2008
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11820862
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06/20/2007
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11/08/2007
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NEGATIVE RESISTS BASED ON ACID-CATALYZED ELIMINATION OF POLAR MOLECULES
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02/01/2011
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11828382
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07/26/2007
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01/29/2009
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METHOD AND APPARATUS FOR HANDLING EXCESS DATA DURING MEMORY ACCESS
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03/31/2009
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11828390
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07/26/2007
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06/26/2008
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METHOD AND APPARATUS FOR GENERATING RANDOM JITTER
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01/13/2009
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11828666
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07/26/2007
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01/31/2008
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Title:
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OPTICAL SPOT GEOMETRIC PARAMETER DETERMINATION USING CALIBRATION TARGETS
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07/20/2010
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11828705
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07/26/2007
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Pub Dt:
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01/29/2009
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Title:
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METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS
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04/19/2011
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11829187
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07/27/2007
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01/24/2008
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Title:
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ENABLING MEMORY REDUNDANCY DURING TESTING
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10/20/2009
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11830116
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07/30/2007
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02/05/2009
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Title:
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SHRINK TEST MODE TO IDENTIFY NTH ORDER SPEED PATHS
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02/24/2009
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11830200
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07/30/2007
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Pub Dt:
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01/24/2008
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Title:
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APPARATUS AND METHODS FOR INTEGRALLY PACKAGING OPTOELECTRONIC DEVICES, IC CHIPS AND OPTICAL TRANSMISSION LINES
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04/19/2011
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11830213
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07/30/2007
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12/25/2008
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Title:
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ELECTROLYTIC DEVICE BASED ON A SOLUTION-PROCESSED ELECTROLYTE
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12/02/2008
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11830221
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07/30/2007
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Pub Dt:
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02/07/2008
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Title:
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CIRCUITS AND METHODS FOR IMPLEMENTING TRANSFORMER-COUPLED AMPLIFIERS AT MILLIMETER WAVE FREQUENCIES
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02/19/2013
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11830239
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07/30/2007
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Pub Dt:
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01/17/2013
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Title:
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APPARATUS AND METHODS FOR PACKAGING ANTENNAS WITH INTEGRATED CIRCUIT CHIPS FOR MILLIMETER WAVE APPLICATIONS
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02/07/2012
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11830316
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07/30/2007
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02/05/2009
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Title:
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FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE
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Issue Dt:
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11/17/2009
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11830328
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07/30/2007
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02/05/2009
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Title:
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FINFET FLASH MEMORY DEVICE WITH AN EXTENDED FLOATING BACK GATE
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09/09/2008
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11830464
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07/30/2007
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Pub Dt:
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11/15/2007
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Title:
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STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS
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09/16/2008
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11830489
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07/30/2007
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Pub Dt:
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11/22/2007
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Title:
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STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PERFORMANCE HYBRID-ORIENTATION SILICON-ON-INSULATOR CMOS DEVICES
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05/26/2009
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11830872
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07/31/2007
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11/22/2007
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Title:
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DOUBLE GATE ISOLATION
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06/14/2011
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11831005
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07/31/2007
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02/05/2009
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Title:
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SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
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04/12/2011
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11831099
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07/31/2007
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Pub Dt:
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02/05/2009
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Title:
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LAYER PATTERNING USING DOUBLE EXPOSURE PROCESSES IN A SINGLE PHOTORESIST LAYER
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10/04/2011
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11831119
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07/31/2007
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Pub Dt:
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02/05/2009
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PLACING VIRTUAL MACHINE MONITOR (VMM) CODE IN GUEST CONTEXT TO SPEED MEMORY MAPPED INPUT/OUTPUT VIRTUALIZATION
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02/07/2012
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11831137
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07/31/2007
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01/24/2008
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METHOD FOR PERFORMING CHEMICAL SHRINK PROCESS OVER BARC (BOTTOM ANTI-REFLECTIVE COATING)
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08/09/2011
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11831138
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07/31/2007
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Pub Dt:
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02/05/2009
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MICROELECTRONIC STRUCTURE INCLUDING DUAL DAMASCENE STRUCTURE AND HIGH CONTRAST ALIGNMENT MARK
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07/28/2009
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11831149
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07/31/2007
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Pub Dt:
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02/05/2009
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Title:
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INTERCONNECT STRUCTURE WITH GRAIN GROWTH PROMOTION LAYER AND METHOD FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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11832220
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Filing Dt:
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08/01/2007
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Publication #:
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Pub Dt:
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12/20/2007
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Title:
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DRAM ACCESS COMMAND QUEUING
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Patent #:
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Issue Dt:
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03/29/2011
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Application #:
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11832453
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Filing Dt:
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08/01/2007
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Publication #:
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Pub Dt:
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01/24/2008
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Title:
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ENHANCING A POWER DISTRIBUTION SYSTEM IN A CERAMIC INTEGRATED CIRCUIT PACKAGE
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Patent #:
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Issue Dt:
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03/08/2011
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Application #:
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11833112
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Filing Dt:
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08/02/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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SMALL AREA, ROBUST SILICON VIA STRUCTURE AND PROCESS
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Patent #:
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Issue Dt:
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09/25/2012
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Application #:
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11833274
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Filing Dt:
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08/03/2007
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Publication #:
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Pub Dt:
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03/06/2008
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Title:
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DATA STORAGE SYSTEMS
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Patent #:
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Issue Dt:
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06/28/2011
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Application #:
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11833321
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Filing Dt:
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08/03/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL
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Patent #:
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Issue Dt:
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04/26/2011
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Application #:
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11833538
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Filing Dt:
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08/03/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT
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Patent #:
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Issue Dt:
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05/10/2011
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Application #:
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11834110
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Filing Dt:
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08/06/2007
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
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Patent #:
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Issue Dt:
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07/06/2010
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Application #:
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11834552
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Filing Dt:
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08/06/2007
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Publication #:
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Pub Dt:
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02/12/2009
| | | | |
Title:
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HEAT SINK WITH THERMALLY COMPLIANT BEAMS
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Patent #:
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Issue Dt:
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12/21/2010
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Application #:
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11834752
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Filing Dt:
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08/07/2007
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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BIDIRECTIONAL AND EXPANDABLE HEAT FLOW MEASUREMENT TOOL FOR UNITS OF AIR COOLED ELECTRICAL EQUIPMENT
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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11834956
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Filing Dt:
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08/07/2007
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Publication #:
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Pub Dt:
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02/12/2009
| | | | |
Title:
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ON-CHIP DECOUPLING CAPACITOR STRUCTURES
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Patent #:
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Issue Dt:
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06/28/2011
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Application #:
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11834961
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Filing Dt:
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08/07/2007
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Publication #:
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Pub Dt:
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02/12/2009
| | | | |
Title:
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ON-CHIP DECOUPLING CAPACITOR STRUCTURES
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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11834971
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Filing Dt:
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08/07/2007
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Publication #:
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Pub Dt:
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02/12/2009
| | | | |
Title:
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APPARATUS AND METHOD OF ELECTROLYTIC REMOVAL OF METALS FROM A WAFER SURFACE
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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11834979
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Filing Dt:
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08/07/2007
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Publication #:
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Pub Dt:
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02/12/2009
| | | | |
Title:
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MULTIPLE EXPOSURE TECHNIQUE USING OPC TO CORRECT DISTORTION
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Patent #:
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Issue Dt:
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12/22/2009
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Application #:
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11835167
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Filing Dt:
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08/07/2007
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Publication #:
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Pub Dt:
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01/24/2008
| | | | |
Title:
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VERTICAL NANOTUBE FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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09/21/2010
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Application #:
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11835182
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Filing Dt:
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08/07/2007
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Publication #:
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Pub Dt:
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02/28/2008
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Title:
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METHODS FOR MANUFACTURING A FINFET USING A CONVENTIONAL WAFER AND APPARATUS MANUFACTURED THEREFROM
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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11835310
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Filing Dt:
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08/07/2007
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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SIMPLE LOW POWER CIRCUIT STRUCTURE WITH METAL GATE AND HIGH-K DIELECTRIC
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Patent #:
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Issue Dt:
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06/23/2009
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Application #:
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11835800
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Filing Dt:
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08/08/2007
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Publication #:
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Pub Dt:
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02/12/2009
| | | | |
Title:
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ELECTRICAL FUSE WITH A THINNED FUSELINK MIDDLE PORTION
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Patent #:
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Issue Dt:
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06/22/2010
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Application #:
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11836259
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Filing Dt:
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08/09/2007
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Publication #:
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Pub Dt:
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01/03/2008
| | | | |
Title:
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METHOD AND DEVICE FOR FLOWING A LIQUID ON A SURFACE
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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11836842
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Filing Dt:
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08/10/2007
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Publication #:
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Pub Dt:
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11/29/2007
| | | | |
Title:
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AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX
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Patent #:
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Issue Dt:
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01/26/2010
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Application #:
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11837057
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Filing Dt:
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08/10/2007
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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EXTREMELY-THIN SILICON-ON-INSULATOR TRANSISTOR WITH RAISED SOURCE/DRAIN
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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11837785
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Filing Dt:
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08/13/2007
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Publication #:
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Pub Dt:
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02/19/2009
| | | | |
Title:
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SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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11838507
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Filing Dt:
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08/14/2007
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Publication #:
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Pub Dt:
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02/19/2009
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Title:
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MICROELECTRONIC LITHOGRAPHIC ALIGNMENT USING HIGH CONTRAST ALIGNMENT MARK
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Patent #:
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Issue Dt:
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07/13/2010
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Application #:
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11838663
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Filing Dt:
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08/14/2007
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Publication #:
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Pub Dt:
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02/19/2009
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Title:
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METHOD AND APPARATUS FOR FABRICATING SUB-LITHOGRAPHY DATA TRACKS FOR USE IN MAGNETIC SHIFT REGISTER MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/17/2008
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Application #:
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11838931
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Filing Dt:
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08/15/2007
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Publication #:
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Pub Dt:
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11/29/2007
| | | | |
Title:
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CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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11838939
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Filing Dt:
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08/15/2007
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Publication #:
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Pub Dt:
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01/24/2008
| | | | |
Title:
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FORMATION OF METAL-INSULATOR-METAL CAPACITOR SIMULTANEOUSLY WITH ALUMINUM METAL WIRING LEVEL USING A HARDMASK
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Patent #:
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Issue Dt:
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10/04/2011
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Application #:
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11839106
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Filing Dt:
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08/15/2007
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Publication #:
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Pub Dt:
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11/29/2007
| | | | |
Title:
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VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES
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Patent #:
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Issue Dt:
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09/06/2011
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Application #:
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11839585
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Filing Dt:
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08/16/2007
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Publication #:
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Pub Dt:
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02/19/2009
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Title:
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TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION
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Patent #:
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Issue Dt:
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10/13/2009
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Application #:
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11839611
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Filing Dt:
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08/16/2007
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Publication #:
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Pub Dt:
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02/19/2009
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Title:
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LEVEL SHIFTER CIRCUIT WITH PRE-CHARGE/PRE-DISCHARGE
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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11839714
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Filing Dt:
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08/16/2007
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Publication #:
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Pub Dt:
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02/19/2009
| | | | |
Title:
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METHOD FOR REPORTING THE STATUS OF A CONTROL APPLICATION IN AN AUTOMATED MANUFACTURING ENVIRONMENT
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Patent #:
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Issue Dt:
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11/16/2010
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Application #:
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11839749
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Filing Dt:
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08/16/2007
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Publication #:
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Pub Dt:
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02/19/2009
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Title:
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TOOL FOR REPORTING THE STATUS AND DRILL-DOWN OF A CONTROL APPLICATION IN AN AUTOMATED MANUFACTURING ENVIRONMENT
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Patent #:
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Issue Dt:
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03/29/2011
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Application #:
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11839767
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Filing Dt:
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08/16/2007
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Publication #:
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Pub Dt:
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04/24/2008
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Title:
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METHOD OF FORMING DAMASCENE FILAMENT WIRES
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Patent #:
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Issue Dt:
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05/03/2011
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Application #:
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11839934
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Filing Dt:
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08/16/2007
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Publication #:
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Pub Dt:
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02/19/2009
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Title:
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RESIST STRIPPING METHODS USING BACKFILLING MATERIAL LAYER
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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11840029
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Filing Dt:
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08/16/2007
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Publication #:
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Pub Dt:
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12/06/2007
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Title:
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HETERO-INTEGRATED STRAINED SILICON N- AND P- MOSFETS
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Patent #:
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Issue Dt:
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07/19/2011
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Application #:
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11841161
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Filing Dt:
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08/20/2007
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Pub Dt:
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02/26/2009
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Title:
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MOS STRUCTURES THAT EXHIBIT LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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05/26/2009
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Application #:
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11841163
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Filing Dt:
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08/20/2007
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Publication #:
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Pub Dt:
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12/06/2007
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Title:
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METHOD FOR FACILITATING FORWARDING OF DATA PACKETS THROUGH A NODE OF A DATA TRANSFER NETWORK USING MULTIPLE TYPES OF FORWARDING TABLES
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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11841179
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Filing Dt:
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08/31/2007
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Pub Dt:
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03/05/2009
| | | | |
Title:
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METHOD AND APPARATUS FOR CLOCK CYCLE STEALING
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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11842206
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Filing Dt:
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08/21/2007
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Pub Dt:
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02/26/2009
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Title:
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MULTICORE PROCESSOR HAVING STORAGE FOR CORE-SPECIFIC OPERATIONAL DATA
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Patent #:
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Issue Dt:
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06/22/2010
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Application #:
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11842437
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Filing Dt:
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08/21/2007
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Publication #:
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Pub Dt:
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02/26/2009
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Title:
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SELF-ALIGNED SUPER STRESSED PFET
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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11842515
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Filing Dt:
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08/21/2007
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Publication #:
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Pub Dt:
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02/26/2009
| | | | |
Title:
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METHODS FOR NORMALIZING ERROR IN PHOTOLITHOGRAPHIC PROCESSES
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Patent #:
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Issue Dt:
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04/15/2008
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Application #:
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11842533
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Filing Dt:
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08/21/2007
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Publication #:
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Pub Dt:
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12/13/2007
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Title:
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METHOD AND APPARATUS FOR CHARACTERISTIC IMPEDANCE DISCONTINUITY REDUCTION IN HIGH-SPEED FLEXIBLE CIRCUIT APPLICATIONS
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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11843434
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Filing Dt:
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08/22/2007
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Publication #:
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Pub Dt:
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02/26/2009
| | | | |
Title:
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OPTIMAL SOLUTION TO CONTROL DATA CHANNELS
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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11843784
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Filing Dt:
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08/23/2007
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Title:
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CONNECTIVITY MANAGER TO MANAGE CONNECTIVITY SERVICES
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Patent #:
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Issue Dt:
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09/07/2010
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Application #:
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11843791
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Filing Dt:
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08/23/2007
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Publication #:
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Pub Dt:
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02/26/2009
| | | | |
Title:
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DETECTION AND CORRECTION OF DROPPED WRITE ERRORS IN A DATA STORAGE SYSTEM
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