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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
01/18/2011
Application #:
12014850
Filing Dt:
01/16/2008
Publication #:
Pub Dt:
05/15/2008
Title:
A METHOD OF FORMING A DUAL-PLANE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
2
Patent #:
Issue Dt:
04/26/2011
Application #:
12014977
Filing Dt:
01/16/2008
Publication #:
Pub Dt:
07/16/2009
Title:
METHOD TO IMPROVE WETTABILITY BY REDUCING LIQUID POLYMER MACROMOLECULE MOBILITY THROUGH FORMING POLYMER BLEND SYSTEM
3
Patent #:
Issue Dt:
10/11/2011
Application #:
12015047
Filing Dt:
01/16/2008
Publication #:
Pub Dt:
07/16/2009
Title:
FLUORINE-FREE HETEROAROMATIC PHOTOACID GENERATORS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME
4
Patent #:
Issue Dt:
11/30/2010
Application #:
12015254
Filing Dt:
01/16/2008
Publication #:
Pub Dt:
07/16/2009
Title:
IMPLEMENTING ENHANCED LBIST TESTING OF PATHS INCLUDING ARRAYS
5
Patent #:
Issue Dt:
04/17/2012
Application #:
12015631
Filing Dt:
01/17/2008
Publication #:
Pub Dt:
06/05/2008
Title:
LOGIC TRANSFORMATION AND GATE PLACEMENT TO AVOID ROUTING CONGESTION
6
Patent #:
Issue Dt:
01/18/2011
Application #:
12015692
Filing Dt:
01/17/2008
Publication #:
Pub Dt:
12/04/2008
Title:
TECHNIQUE FOR STRAIN ENGINEERING IN SILICON-BASED TRANSISTORS BY USING IMPLANTATION TECHNIQUES FOR FORMING A STRAIN-INDUCING LAYER UNDER THE CHANNEL REGION
7
Patent #:
Issue Dt:
04/02/2013
Application #:
12015789
Filing Dt:
01/17/2008
Publication #:
Pub Dt:
07/23/2009
Title:
MONITORING STAGE ALIGNMENT AND RELATED STAGE AND CALIBRATION TARGET
8
Patent #:
Issue Dt:
12/20/2011
Application #:
12015795
Filing Dt:
01/17/2008
Publication #:
Pub Dt:
07/23/2009
Title:
CHARACTERIZING FILMS USING OPTICAL FILTER PSEUDO SUBSTRATE
9
Patent #:
Issue Dt:
09/13/2011
Application #:
12015825
Filing Dt:
01/17/2008
Publication #:
Pub Dt:
07/23/2009
Title:
METHOD AND MATERIAL FOR A THERMALLY CROSSLINKABLE RANDOM COPOLYMER
10
Patent #:
Issue Dt:
04/10/2012
Application #:
12016039
Filing Dt:
01/17/2008
Publication #:
Pub Dt:
07/23/2009
Title:
TRANSFER OF DATA FROM POSITIONAL DATA SOURCES TO PARTITIONED DATABASES IN RESTARTABLE ENVIRONMENTS
11
Patent #:
Issue Dt:
02/15/2011
Application #:
12016312
Filing Dt:
01/18/2008
Publication #:
Pub Dt:
07/23/2009
Title:
DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP
12
Patent #:
Issue Dt:
09/06/2011
Application #:
12016453
Filing Dt:
01/18/2008
Publication #:
Pub Dt:
07/23/2009
Title:
SYSTEM AND METHOD FOR CREATING A LOGICAL REPRESENTATION OF A FUNCTIONAL LOGIC SYSTEM FROM A PHYSICAL REPRESENTATION
13
Patent #:
Issue Dt:
02/01/2011
Application #:
12017134
Filing Dt:
01/21/2008
Publication #:
Pub Dt:
07/23/2009
Title:
METHOD TO CONTROL SEMICONDUCTOR DEVICE OVERLAY USING POST ETCH IMAGE METROLOGY
14
Patent #:
Issue Dt:
02/22/2011
Application #:
12017141
Filing Dt:
01/21/2008
Publication #:
Pub Dt:
07/23/2009
Title:
VIA GOUGING METHODS AND RELATED SEMICONDUCTOR STRUCTURE
15
Patent #:
Issue Dt:
04/15/2014
Application #:
12017175
Filing Dt:
01/21/2008
Publication #:
Pub Dt:
12/04/2008
Title:
ENHANCED TRANSISTOR PERFORMANCE OF N-CHANNEL TRANSISTORS BY USING AN ADDITIONAL LAYER ABOVE A DUAL STRESS LINER IN A SEMICONDUCTOR DEVICE
16
Patent #:
Issue Dt:
03/20/2012
Application #:
12017404
Filing Dt:
01/22/2008
Publication #:
Pub Dt:
07/23/2009
Title:
ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACCESS TRANSISTORS AND DESIGN STRUCTURE FOR SAME
17
Patent #:
Issue Dt:
06/26/2012
Application #:
12017598
Filing Dt:
01/22/2008
Publication #:
Pub Dt:
05/24/2012
Title:
TWO-DIMENSIONAL PATTERNING EMPLOYING SELF-ASSEMBLED MATERIAL
18
Patent #:
Issue Dt:
09/04/2012
Application #:
12017779
Filing Dt:
01/22/2008
Publication #:
Pub Dt:
07/23/2009
Title:
MULTI-MODAL DATA ANALYSIS FOR DEFECT IDENTIFICATION
19
Patent #:
Issue Dt:
01/22/2013
Application #:
12018030
Filing Dt:
01/22/2008
Publication #:
Pub Dt:
07/23/2009
Title:
PROVIDING A MEMORY DEVICE HAVING A SHARED ERROR FEEDBACK PIN
20
Patent #:
Issue Dt:
02/01/2011
Application #:
12018316
Filing Dt:
01/23/2008
Publication #:
Pub Dt:
07/23/2009
Title:
SUB-LITHOGRAPHIC PRINTING METHOD
21
Patent #:
Issue Dt:
07/19/2011
Application #:
12018421
Filing Dt:
01/23/2008
Publication #:
Pub Dt:
07/23/2009
Title:
FILL HEAD FOR FULL-FIELD SOLDER COVERAGE WITH A ROTATABLE MEMBER
22
Patent #:
Issue Dt:
03/16/2010
Application #:
12018440
Filing Dt:
01/23/2008
Publication #:
Pub Dt:
07/23/2009
Title:
STRUCTURE AND METHOD FOR IMPROVED SRAM INTERCONNECT
23
Patent #:
Issue Dt:
11/02/2010
Application #:
12018492
Filing Dt:
01/23/2008
Publication #:
Pub Dt:
07/23/2009
Title:
FINFET DEVICES AND METHODS FOR MANUFACTURING THE SAME
24
Patent #:
Issue Dt:
01/27/2009
Application #:
12018915
Filing Dt:
01/24/2008
Publication #:
Pub Dt:
05/22/2008
Title:
MEMORY DEVICES USING CARBON NANOTUBE (CNT) TECHNOLOGIES
25
Patent #:
Issue Dt:
07/05/2011
Application #:
12019125
Filing Dt:
01/24/2008
Publication #:
Pub Dt:
07/30/2009
Title:
METHODOLOGY AND SYSTEM FOR DETERMINING NUMERICAL ERRORS IN PIXEL-BASED IMAGING SIMULATION IN DESIGNING LITHOGRAPHIC MASKS
26
Patent #:
Issue Dt:
08/14/2012
Application #:
12019153
Filing Dt:
01/24/2008
Publication #:
Pub Dt:
07/30/2009
Title:
SYSTEM AND METHOD FOR A DEVICE SOUND INTERFACE MANAGER
27
Patent #:
Issue Dt:
09/04/2012
Application #:
12020534
Filing Dt:
01/26/2008
Publication #:
Pub Dt:
07/30/2009
Title:
CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD
28
Patent #:
Issue Dt:
08/14/2012
Application #:
12020565
Filing Dt:
01/27/2008
Publication #:
Pub Dt:
07/30/2009
Title:
CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES
29
Patent #:
Issue Dt:
07/12/2011
Application #:
12020643
Filing Dt:
01/28/2008
Publication #:
Pub Dt:
07/30/2009
Title:
FLEXIBLE MULTILAYER PRINTED CIRCUIT ASSEMBLY WITH REDUCED EMI EMISSIONS
30
Patent #:
Issue Dt:
02/07/2012
Application #:
12020879
Filing Dt:
01/28/2008
Publication #:
Pub Dt:
06/12/2008
Title:
AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX
31
Patent #:
Issue Dt:
03/16/2010
Application #:
12020916
Filing Dt:
01/28/2008
Publication #:
Pub Dt:
07/30/2009
Title:
LOCAL STRESS ENGINEERING FOR CMOS DEVICES
32
Patent #:
Issue Dt:
08/16/2011
Application #:
12021316
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
NOBLE METAL CAP FOR INTERCONNECT STRUCTURES
33
Patent #:
Issue Dt:
02/12/2013
Application #:
12021321
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
FINE PITCH SOLDER BUMP STRUCTURE WITH BUILT-IN STRESS BUFFER
34
Patent #:
Issue Dt:
02/08/2011
Application #:
12021333
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
MODIFYING LAYOUT OF IC BASED ON FUNCTION OF INTERCONNECT AND RELATED CIRCUIT AND DESIGN STRUCTURE
35
Patent #:
Issue Dt:
03/20/2012
Application #:
12021339
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
ON-CHIP INTEGRATED VOLTAGE-CONTROLLED VARIABLE INDUCTOR, METHODS OF MAKING AND TUNING SUCH VARIABLE INDUCTORS, AND DESIGN STRUCTURES INTEGRATING SUCH VARIABLE INDUCTORS
36
Patent #:
Issue Dt:
01/24/2012
Application #:
12021455
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
TEST ACCESS MECHANISM FOR MULTI-CORE PROCESSOR OR OTHER INTEGRATED CIRCUIT
37
Patent #:
Issue Dt:
01/05/2010
Application #:
12021459
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS TEMPERATURE INSTABILITY) EFFECT AND/OR PBTI (POSITIVE BIAS TEMPERATURE INSTABILITY) EFFECT
38
Patent #:
Issue Dt:
06/14/2011
Application #:
12021577
Filing Dt:
01/29/2008
Publication #:
Pub Dt:
07/30/2009
Title:
PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR
39
Patent #:
Issue Dt:
03/22/2011
Application #:
12022292
Filing Dt:
01/30/2008
Publication #:
Pub Dt:
07/30/2009
Title:
COMPLEMENTARY METAL GATE DENSE INTERCONNECT AND METHOD OF MANUFACTURING
40
Patent #:
NONE
Issue Dt:
Application #:
12022446
Filing Dt:
01/30/2008
Publication #:
Pub Dt:
07/30/2009
Title:
COMPUTER SYSTEM INCLUDING A MAIN PROCESSOR AND A BOUND SECURITY COPROCESSOR
41
Patent #:
Issue Dt:
08/30/2011
Application #:
12022448
Filing Dt:
01/30/2008
Publication #:
Pub Dt:
07/30/2009
Title:
METHOD AND SYSTEM OF MONITORING MANUFACTURING EQUIPMENT
42
Patent #:
Issue Dt:
12/06/2011
Application #:
12022869
Filing Dt:
01/30/2008
Publication #:
Pub Dt:
07/30/2009
Title:
METHOD AND APPARATUS FOR TESTING A FULL SYSTEM INTEGRATED CIRCUIT DESIGN BY STATISTICAL FAULT INJECTION USING HARDWARE-BASED SIMULATION
43
Patent #:
Issue Dt:
01/24/2012
Application #:
12022951
Filing Dt:
01/30/2008
Publication #:
Pub Dt:
07/30/2009
Title:
REGULAR LOCAL CLOCK BUFFER PLACEMENT AND LATCH CLUSTERING BY ITERATIVE OPTIMIZATION
44
Patent #:
Issue Dt:
11/04/2008
Application #:
12023175
Filing Dt:
01/31/2008
Publication #:
Pub Dt:
05/29/2008
Title:
TRENCH MEMORY
45
Patent #:
Issue Dt:
07/20/2010
Application #:
12023347
Filing Dt:
01/31/2008
Publication #:
Pub Dt:
08/06/2009
Title:
MULTI-GATED, HIGH-MOBILITY, DENSITY IMPROVED DEVICES
46
Patent #:
Issue Dt:
05/24/2011
Application #:
12023887
Filing Dt:
01/31/2008
Publication #:
Pub Dt:
05/14/2009
Title:
METHOD AND APPARATUS FOR MAKING COPLANAR ISOLATED REGIONS OF DIFFERENT SEMICONDUCTOR MATERIALS ON A SUBSTRATE
47
Patent #:
Issue Dt:
02/12/2013
Application #:
12024078
Filing Dt:
01/31/2008
Publication #:
Pub Dt:
08/06/2009
Title:
DATA TRANSMISSION SYSTEM AND METHOD OF CORRECTING AN ERROR IN PARALLEL DATA PATHS OF A DATA TRANSMISSION SYSTEM
48
Patent #:
Issue Dt:
01/04/2011
Application #:
12024188
Filing Dt:
02/01/2008
Publication #:
Pub Dt:
08/06/2009
Title:
ELECTRICALLY DRIVEN OPTICAL PROXIMITY CORRECTION
49
Patent #:
Issue Dt:
07/06/2010
Application #:
12024394
Filing Dt:
02/01/2008
Publication #:
Pub Dt:
08/06/2009
Title:
INTEGRATED MODULE FOR DATA PROCESSING SYSTEM
50
Patent #:
Issue Dt:
10/04/2011
Application #:
12024985
Filing Dt:
02/01/2008
Publication #:
Pub Dt:
08/06/2009
Title:
AMORPHOUS NITRIDE RELEASE LAYERS FOR IMPRINT LITHOGRAPHY, AND METHOD OF USE
51
Patent #:
Issue Dt:
02/01/2011
Application #:
12025213
Filing Dt:
02/04/2008
Publication #:
Pub Dt:
01/01/2009
Title:
WAFER LAYOUT OPTIMIZATION METHOD AND SYSTEM
52
Patent #:
Issue Dt:
12/07/2010
Application #:
12025297
Filing Dt:
02/04/2008
Publication #:
Pub Dt:
08/06/2009
Title:
INTERCONNECT STRUCTURE AND METHOD FOR CU/ULTRA LOW K INTEGRATION
53
Patent #:
Issue Dt:
07/10/2012
Application #:
12026123
Filing Dt:
02/05/2008
Publication #:
Pub Dt:
06/07/2012
Title:
PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL
54
Patent #:
Issue Dt:
02/01/2011
Application #:
12026273
Filing Dt:
02/05/2008
Publication #:
Pub Dt:
01/01/2009
Title:
BLOCKING PRE-AMORPHIZATION OF A GATE ELECTRODE OF A TRANSISTOR
55
Patent #:
Issue Dt:
07/28/2009
Application #:
12026843
Filing Dt:
02/06/2008
Publication #:
Pub Dt:
08/06/2009
Title:
LOCK AND KEY STRUCTURE FOR THREE-DIMENTIONAL CHIP CONNECTION AND PROCESS THEREOF
56
Patent #:
Issue Dt:
04/19/2011
Application #:
12027085
Filing Dt:
02/06/2008
Publication #:
Pub Dt:
05/29/2008
Title:
INCREMENTAL DESIGN REDUCTION VIA ITERATIVE OVERAPPROXIMATION AND RE-ENCODING STRATEGIES
57
Patent #:
Issue Dt:
07/06/2010
Application #:
12027444
Filing Dt:
02/07/2008
Publication #:
Pub Dt:
08/13/2009
Title:
GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH
58
Patent #:
Issue Dt:
08/09/2011
Application #:
12027563
Filing Dt:
02/07/2008
Publication #:
Pub Dt:
06/05/2008
Title:
BACKSIDE UNLAYERING OF MOSFET DEVICES FOR ELECTRICAL AND PHYSICAL CHARACTERIZATION
59
Patent #:
Issue Dt:
04/24/2012
Application #:
12028038
Filing Dt:
02/08/2008
Publication #:
Pub Dt:
08/13/2009
Title:
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFYING ADDRESS GENERATION, INTERLOCKS AND BYPASSES
60
Patent #:
Issue Dt:
08/02/2011
Application #:
12028145
Filing Dt:
02/08/2008
Publication #:
Pub Dt:
08/13/2009
Title:
HIGHLY TUNABLE METAL-ON-SEMICONDUCTOR TRENCH VARACTOR
61
Patent #:
Issue Dt:
11/23/2010
Application #:
12028191
Filing Dt:
02/08/2008
Publication #:
Pub Dt:
06/05/2008
Title:
RAISED STI STRUCTURE AND SUPERDAMASCENE TECHNIQUE FOR NMOSFET PERFORMANCE ENHANCEMENT WITH EMBEDDED SILICON CARBON
62
Patent #:
Issue Dt:
01/15/2013
Application #:
12028466
Filing Dt:
02/08/2008
Publication #:
Pub Dt:
08/13/2009
Title:
METHOD FOR DETECTING HIGH IMPEDANCE FAULTS BY ANALYZING A LOCAL DEVIATION FROM A REGULARIZATION
63
Patent #:
Issue Dt:
01/26/2010
Application #:
12028767
Filing Dt:
02/08/2008
Publication #:
Pub Dt:
06/05/2008
Title:
DISCRETE NANO-TEXTURED STRUCTURES IN BIOMOLECULAR ARRAYS, AND METHOD OF USE
64
Patent #:
Issue Dt:
05/03/2011
Application #:
12028847
Filing Dt:
02/11/2008
Publication #:
Pub Dt:
11/04/2010
Title:
METHOD OF MAKING SMALL GEOMETRY FEATURES
65
Patent #:
Issue Dt:
01/06/2009
Application #:
12028850
Filing Dt:
02/11/2008
Publication #:
Pub Dt:
06/05/2008
Title:
DEVICE FOR MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS
66
Patent #:
Issue Dt:
06/14/2011
Application #:
12028861
Filing Dt:
02/11/2008
Publication #:
Pub Dt:
08/13/2009
Title:
SUBLITHOGRAPHIC PATTERNING METHOD INCORPORATING A SELF-ALIGNED SINGLE MASK PROCESS
67
Patent #:
Issue Dt:
08/23/2011
Application #:
12028973
Filing Dt:
02/11/2008
Publication #:
Pub Dt:
08/13/2009
Title:
PHASE INTERPOLATOR SYSTEM AND ASSOCIATED METHODS
68
Patent #:
Issue Dt:
08/30/2011
Application #:
12029305
Filing Dt:
02/11/2008
Publication #:
Pub Dt:
08/13/2009
Title:
CHIP PACKAGE WITH CHANNEL STIFFENER FRAME
69
Patent #:
Issue Dt:
06/14/2011
Application #:
12029575
Filing Dt:
02/12/2008
Publication #:
Pub Dt:
09/04/2008
Title:
DUAL WIRED INTEGRATED CIRCUIT CHIPS
70
Patent #:
Issue Dt:
05/10/2011
Application #:
12029589
Filing Dt:
02/12/2008
Publication #:
Pub Dt:
06/05/2008
Title:
DUAL WIRED INTEGRATED CIRCUIT CHIPS
71
Patent #:
Issue Dt:
11/30/2010
Application #:
12030917
Filing Dt:
02/14/2008
Publication #:
Pub Dt:
08/20/2009
Title:
STRESS-MODIFIED DEVICE STRUCTURES, METHODS OF FABRICATING SUCH STRESS-MODIFIED DEVICE STRUCTURES, AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT
72
Patent #:
Issue Dt:
06/02/2009
Application #:
12030927
Filing Dt:
02/14/2008
Publication #:
Pub Dt:
06/05/2008
Title:
MEMORY DEVICE AND METHOD OF MANUFACTURING THE DEVICE BY SIMULATANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS
73
Patent #:
Issue Dt:
05/17/2011
Application #:
12031084
Filing Dt:
02/14/2008
Publication #:
Pub Dt:
08/20/2009
Title:
DESIGN STRUCTURE AND METHOD FOR A SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE FOR SOI TECHNOLOGY
74
Patent #:
Issue Dt:
06/10/2008
Application #:
12031093
Filing Dt:
02/14/2008
Title:
METHODS INVOLVING SILICON-ON-INSULATOR TRENCH MEMORY WITH IMPLANTED PLATE
75
Patent #:
Issue Dt:
05/31/2011
Application #:
12031282
Filing Dt:
02/14/2008
Publication #:
Pub Dt:
01/15/2009
Title:
PLANAR CIRCULARLY POLARIZED ANTENNAS
76
Patent #:
Issue Dt:
10/19/2010
Application #:
12031374
Filing Dt:
02/14/2008
Publication #:
Pub Dt:
08/20/2009
Title:
METHODS TO SELECT GOLDEN DEVICES FOR DEVICE MODEL EXTRACTIONS
77
Patent #:
Issue Dt:
12/14/2010
Application #:
12031493
Filing Dt:
02/14/2008
Publication #:
Pub Dt:
07/03/2008
Title:
METHODS AND STRUCTURES FOR PROMOTING STABLE SYNTHESIS OF CARBON NANOTUBES
78
Patent #:
Issue Dt:
07/24/2012
Application #:
12031530
Filing Dt:
02/14/2008
Publication #:
Pub Dt:
06/12/2008
Title:
RELAXED LOW-DEFECT SGOI FOR STRAINED SI CMOS APPLICATIONS
79
Patent #:
Issue Dt:
02/08/2011
Application #:
12031760
Filing Dt:
02/15/2008
Publication #:
Pub Dt:
08/20/2009
Title:
METHOD OF FORMING COPLANAR ACTIVE AND ISOLATION REGIONS AND STRUCTURES THEREOF
80
Patent #:
Issue Dt:
05/03/2011
Application #:
12031761
Filing Dt:
02/15/2008
Publication #:
Pub Dt:
08/20/2009
Title:
ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD
81
Patent #:
Issue Dt:
12/27/2011
Application #:
12032276
Filing Dt:
02/15/2008
Publication #:
Pub Dt:
08/20/2009
Title:
EFFICIENT POWER REGION CHECKING OF MULTI-SUPPLY VOLTAGE MICROPROCESSORS
82
Patent #:
Issue Dt:
11/02/2010
Application #:
12032316
Filing Dt:
02/15/2008
Publication #:
Pub Dt:
06/19/2008
Title:
METHOD OF FORMING A LAND GRID ARRAY INTERPOSER
83
Patent #:
Issue Dt:
09/27/2011
Application #:
12032417
Filing Dt:
02/15/2008
Publication #:
Pub Dt:
08/20/2009
Title:
AUTOMATED METHOD AND APPARATUS FOR VERY EARLY VALIDATION OF CHIP POWER DISTRIBUTION NETWORKS IN SEMICONDUCTOR CHIP DESIGNS
84
Patent #:
Issue Dt:
12/07/2010
Application #:
12032420
Filing Dt:
02/15/2008
Publication #:
Pub Dt:
08/20/2009
Title:
DYNAMIC TAPE DRIVE CALIBRATION
85
Patent #:
Issue Dt:
07/12/2011
Application #:
12032517
Filing Dt:
02/15/2008
Publication #:
Pub Dt:
08/20/2009
Title:
METHOD OF AUTOMATING CREATION OF A CLOCK CONTROL DISTRIBUTION NETWORK IN AN INTEGRATED CIRCUIT FLOORPLAN
86
Patent #:
Issue Dt:
08/23/2011
Application #:
12032542
Filing Dt:
02/15/2008
Publication #:
Pub Dt:
08/20/2009
Title:
OPTIMIZATION METHOD OF INTEGRATED CIRCUIT DESIGN FOR REDUCTION OF GLOBAL CLOCK LOAD AND BALANCING CLOCK SKEW
87
Patent #:
Issue Dt:
08/16/2011
Application #:
12032610
Filing Dt:
02/15/2008
Publication #:
Pub Dt:
08/20/2009
Title:
APPARATUS FOR STABILIZING CONVERGENCE OF AN ADAPTIVE LINE EQUALIZER
88
Patent #:
Issue Dt:
03/22/2011
Application #:
12032643
Filing Dt:
02/16/2008
Publication #:
Pub Dt:
08/20/2009
Title:
ACCURATE PARASITICS ESTIMATION FOR HIERARCHICAL CUSTOMIZED VLSI DESIGN
89
Patent #:
Issue Dt:
07/09/2013
Application #:
12032647
Filing Dt:
02/16/2008
Publication #:
Pub Dt:
08/20/2009
Title:
METHOD AND APPARATUS OF HANDLING INSTRUCTION REJECTS, PARTIAL REJECTS, STALLS AND BRANCH WRONG IN A SIMULATION MODEL
90
Patent #:
Issue Dt:
08/30/2011
Application #:
12032762
Filing Dt:
02/18/2008
Publication #:
Pub Dt:
08/20/2009
Title:
AUTOMATED METHOD FOR BUFFERING IN A VLSI DESIGN
91
Patent #:
Issue Dt:
06/28/2011
Application #:
12032841
Filing Dt:
02/18/2008
Publication #:
Pub Dt:
08/20/2009
Title:
VERIFICATION OF SPARE LATCH PLACEMENT IN SYNTHESIZED MACROS
92
Patent #:
Issue Dt:
12/21/2010
Application #:
12033200
Filing Dt:
02/19/2008
Publication #:
Pub Dt:
08/20/2009
Title:
HEAT SINK
93
Patent #:
Issue Dt:
06/14/2016
Application #:
12033280
Filing Dt:
02/19/2008
Publication #:
Pub Dt:
08/20/2009
Title:
SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING
94
Patent #:
Issue Dt:
01/18/2011
Application #:
12033322
Filing Dt:
02/19/2008
Publication #:
Pub Dt:
08/20/2009
Title:
METHOD AND STRUCTURE FOR RELIEVING TRANSISTOR PERFORMANCE DEGRADATION DUE TO SHALLOW TRENCH ISOLATION INDUCED STRESS
95
Patent #:
Issue Dt:
02/15/2011
Application #:
12033325
Filing Dt:
02/19/2008
Publication #:
Pub Dt:
08/20/2009
Title:
MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR WITH TAILORED DRIVE CURRENT
96
Patent #:
Issue Dt:
09/20/2011
Application #:
12033359
Filing Dt:
02/19/2008
Publication #:
Pub Dt:
08/20/2009
Title:
METHOD OF FORMING A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR WITH TAILORED DRIVE CURRENT
97
Patent #:
Issue Dt:
02/22/2011
Application #:
12033974
Filing Dt:
02/20/2008
Publication #:
Pub Dt:
08/20/2009
Title:
SYSTEM AND METHOD FOR PROVIDING A COMMON INSTRUCTION TABLE
98
Patent #:
Issue Dt:
04/06/2010
Application #:
12034023
Filing Dt:
02/20/2008
Publication #:
Pub Dt:
08/20/2009
Title:
RADIO FREQUENCY (RF) INTEGRATED CIRCUIT (IC) PACKAGES WITH INTEGRATED APERTURE-COUPLED PATCH ANTENNA(S)
99
Patent #:
Issue Dt:
03/26/2013
Application #:
12034210
Filing Dt:
02/20/2008
Publication #:
Pub Dt:
08/20/2009
Title:
METHOD AND APPARATUS FOR FABRICATING A HETEROJUNCTION BIPOLAR TRANSISTOR
100
Patent #:
Issue Dt:
11/11/2008
Application #:
12034296
Filing Dt:
02/20/2008
Publication #:
Pub Dt:
06/19/2008
Title:
STRUCTURE AND METHOD FOR IMPROVED STRESS AND YIELD IN PFETS WITH EMBEDDED SIGE SOURCE/DRAIN REGIONS
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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