skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 76 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
7951424
Issue Dt:
05/31/2011
Application #:
12122981
Filing Dt:
05/19/2008
Publication #:
US20090117277
Pub Dt:
05/07/2009
Title:
SELECTIVE PLACEMENT OF CARBON NANOTUBES ON OXIDE SURFACES
2
Patent #:
7923838
Issue Dt:
04/12/2011
Application #:
12122984
Filing Dt:
05/19/2008
Publication #:
US20080211100
Pub Dt:
09/04/2008
Title:
METHOD AND STRUCTURE FOR REDUCING CONTACT RESISTANCE BETWEEN SILICIDE CONTACT AND OVERLYING METALLIZATION
3
Patent #:
7486107
Issue Dt:
02/03/2009
Application #:
12123487
Filing Dt:
05/20/2008
Title:
METHOD FOR EXTENDING LIFETIME RELIABILITY OF DIGITAL LOGIC DEVICES THROUGH REVERSAL OF AGING MECHANISMS
4
Patent #:
7897451
Issue Dt:
03/01/2011
Application #:
12123524
Filing Dt:
05/20/2008
Publication #:
US20090142900
Pub Dt:
06/04/2009
Title:
METHOD FOR CREATING TENSILE STRAIN BY SELECTIVELY APPLYING STRESS MEMORIZATION TECHNIQUES TO NMOS TRANSISTORS
5
Patent #:
8228112
Issue Dt:
07/24/2012
Application #:
12123735
Filing Dt:
05/20/2008
Publication #:
US20090102542
Pub Dt:
04/23/2009
Title:
SWITCH WITH REDUCED INSERTION LOSS
6
Patent #:
8225255
Issue Dt:
07/17/2012
Application #:
12124472
Filing Dt:
05/21/2008
Publication #:
US20090290401
Pub Dt:
11/26/2009
Title:
PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS
7
Patent #:
8108822
Issue Dt:
01/31/2012
Application #:
12124551
Filing Dt:
05/21/2008
Publication #:
US20090070718
Pub Dt:
03/12/2009
Title:
METHODOLOGY FOR PLACEMENT BASED ON CIRCUIT FUNCTION AND LATCHUP SENSITIVITY
8
Patent #:
7480888
Issue Dt:
01/20/2009
Application #:
12124771
Filing Dt:
05/21/2008
Title:
DESIGN STRUCTURE FOR FACILITATING ENGINEERING CHANGES IN INTEGRATED CIRCUITS
9
Patent #:
8405950
Issue Dt:
03/26/2013
Application #:
12125007
Filing Dt:
05/21/2008
Publication #:
US20090290278
Pub Dt:
11/26/2009
Title:
CABLE HAVING ESD DISSIPATIVE LAYER ELECTRICALLY COUPLED TO LEADS THEREOF
10
Patent #:
8017499
Issue Dt:
09/13/2011
Application #:
12125175
Filing Dt:
05/22/2008
Publication #:
US20080220588
Pub Dt:
09/11/2008
Title:
STRAINED SI MOSFET ON TENSILE-STRAINED SIGE-ON-INSULATOR (SGOI)
11
Patent #:
7904872
Issue Dt:
03/08/2011
Application #:
12125255
Filing Dt:
05/22/2008
Publication #:
US20090292828
Pub Dt:
11/26/2009
Title:
SYSTEM-ON-CHIP (SOC), DESIGN STRUCTURE AND METHOD
12
Patent #:
7904873
Issue Dt:
03/08/2011
Application #:
12125269
Filing Dt:
05/22/2008
Publication #:
US20090291533
Pub Dt:
11/26/2009
Title:
SYSTEM-ON-CHIP (SOC), DESIGN STRUCTURE AND METHOD
13
Patent #:
8003453
Issue Dt:
08/23/2011
Application #:
12125501
Filing Dt:
05/22/2008
Publication #:
US20080227259
Pub Dt:
09/18/2008
Title:
SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS
14
Patent #:
7750418
Issue Dt:
07/06/2010
Application #:
12125508
Filing Dt:
05/22/2008
Publication #:
US20080217747
Pub Dt:
09/11/2008
Title:
INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES
15
Patent #:
7826251
Issue Dt:
11/02/2010
Application #:
12125637
Filing Dt:
05/22/2008
Publication #:
US20090290439
Pub Dt:
11/26/2009
Title:
HIGH PERFORMANCE METAL GATE POLYGATE 8 TRANSISTOR SRAM CELL WITH REDUCED VARIABILITY
16
Patent #:
7595554
Issue Dt:
09/29/2009
Application #:
12125971
Filing Dt:
05/23/2008
Publication #:
US20080217731
Pub Dt:
09/11/2008
Title:
AN INTERCONNECT STRUCTURE WITH DIELECTRIC AIR GAPS
17
Patent #:
7932514
Issue Dt:
04/26/2011
Application #:
12126015
Filing Dt:
05/23/2008
Publication #:
US20090289638
Pub Dt:
11/26/2009
Title:
MICROWAVE READOUT FOR FLUX-BIASED QUBITS
18
Patent #:
8563225
Issue Dt:
10/22/2013
Application #:
12126245
Filing Dt:
05/23/2008
Publication #:
US20090291388
Pub Dt:
11/26/2009
Title:
FORMING A SELF-ALIGNED HARD MASK FOR CONTACT TO A TUNNEL JUNCTION
19
Patent #:
7919225
Issue Dt:
04/05/2011
Application #:
12126287
Filing Dt:
05/23/2008
Publication #:
US20090291389
Pub Dt:
11/26/2009
Title:
PHOTOPATTERNABLE DIELECTRIC MATERIALS FOR BEOL APPLICATIONS AND METHODS FOR USE
20
Patent #:
7538006
Issue Dt:
05/26/2009
Application #:
12126866
Filing Dt:
05/24/2008
Title:
ANNULAR DAMASCENE VERTICAL NATURAL CAPACITOR
21
Patent #:
8054736
Issue Dt:
11/08/2011
Application #:
12126967
Filing Dt:
05/26/2008
Publication #:
US20080225677
Pub Dt:
09/18/2008
Title:
STORAGE DEVICE HAVING FLEXIBLE ARCHITECTURE AND FREE SCALABILITY
22
Patent #:
7781273
Issue Dt:
08/24/2010
Application #:
12127033
Filing Dt:
05/27/2008
Publication #:
US20080224258
Pub Dt:
09/18/2008
Title:
SEMICONDUCTOR STRUCTUE WITH MULTIPLE FINS HAVING DIFFERENT CHANNEL REGION HEIGHTS AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE
23
Patent #:
7911025
Issue Dt:
03/22/2011
Application #:
12127080
Filing Dt:
05/27/2008
Publication #:
US20080224261
Pub Dt:
09/18/2008
Title:
FUSE/ANTI-FUSE STRUCTURE AND METHODS OF MAKING AND PROGRAMMING SAME
24
Patent #:
8010927
Issue Dt:
08/30/2011
Application #:
12127245
Filing Dt:
05/27/2008
Publication #:
US20090089719
Pub Dt:
04/02/2009
Title:
STRUCTURE FOR A STACKED POWER CLAMP HAVING A BIGFET GATE PULL-UP CIRCUIT
25
Patent #:
7900179
Issue Dt:
03/01/2011
Application #:
12127392
Filing Dt:
05/27/2008
Publication #:
US20090300565
Pub Dt:
12/03/2009
Title:
METHOD FOR PRIORITIZING NODES FOR REROUTING AND DEVICE THEREFOR
26
Patent #:
7771208
Issue Dt:
08/10/2010
Application #:
12127418
Filing Dt:
05/27/2008
Publication #:
US20090053908
Pub Dt:
02/26/2009
Title:
METALIZED ELASTOMERIC ELECTRICAL CONTACTS
27
Patent #:
7832095
Issue Dt:
11/16/2010
Application #:
12127432
Filing Dt:
05/27/2008
Publication #:
US20090049688
Pub Dt:
02/26/2009
Title:
METHOD OF FORMING A LAND GRID ARRAY (LGA) INTERPOSER ARRANGEMENT UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
28
Patent #:
8385207
Issue Dt:
02/26/2013
Application #:
12127631
Filing Dt:
05/27/2008
Publication #:
US20090296577
Pub Dt:
12/03/2009
Title:
METHOD AND APPARATUS FOR END-TO-END NETWORK CONGESTION MANAGEMENT
29
Patent #:
8010934
Issue Dt:
08/30/2011
Application #:
12127900
Filing Dt:
05/28/2008
Publication #:
US20080301596
Pub Dt:
12/04/2008
Title:
METHOD AND SYSTEM FOR TESTING BIT FAILURES IN ARRAY ELEMENTS OF AN ELECTRONIC CIRCUIT
30
Patent #:
8048330
Issue Dt:
11/01/2011
Application #:
12127921
Filing Dt:
05/28/2008
Publication #:
US20090170319
Pub Dt:
07/02/2009
Title:
METHOD OF FORMING AN INTERLAYER DIELECTRIC MATERIAL HAVING DIFFERENT REMOVAL RATES DURING CMP
31
Patent #:
8138546
Issue Dt:
03/20/2012
Application #:
12127946
Filing Dt:
05/28/2008
Publication #:
US20080224172
Pub Dt:
09/18/2008
Title:
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
32
Patent #:
8244391
Issue Dt:
08/14/2012
Application #:
12127972
Filing Dt:
05/28/2008
Publication #:
US20090299510
Pub Dt:
12/03/2009
Title:
METHOD FOR MINIMIZING PRODUCTIVITY LOSS WHILE USING A MANUFACTURING SCHEDULER
33
Patent #:
7491965
Issue Dt:
02/17/2009
Application #:
12127994
Filing Dt:
05/28/2008
Publication #:
US20080224118
Pub Dt:
09/18/2008
Title:
HEAT-SHIELDED LOW POWER PCM-BASED REPROGRAMMABLE EFUSE DEVICE
34
Patent #:
7968459
Issue Dt:
06/28/2011
Application #:
12128040
Filing Dt:
05/28/2008
Publication #:
US20080258220
Pub Dt:
10/23/2008
Title:
ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS
35
Patent #:
7915884
Issue Dt:
03/29/2011
Application #:
12128058
Filing Dt:
05/28/2008
Publication #:
US20090024346
Pub Dt:
01/22/2009
Title:
IMPORTATION OF VIRTUAL SIGNALS INTO ELECTRONIC TEST EQUIPMENT TO FACILITATE TESTING OF AN ELECTRONIC COMPONENT
36
Patent #:
7838913
Issue Dt:
11/23/2010
Application #:
12128134
Filing Dt:
05/28/2008
Publication #:
US20090294800
Pub Dt:
12/03/2009
Title:
HYBRID FET INCORPORATING A FINFET AND A PLANAR FET
37
Patent #:
7620510
Issue Dt:
11/17/2009
Application #:
12128526
Filing Dt:
05/28/2008
Publication #:
US20080225615
Pub Dt:
09/18/2008
Title:
PULSED RING OSCILLATOR CIRCUIT FOR STORAGE CELL READ TIMING EVALUATION
38
Patent #:
7877222
Issue Dt:
01/25/2011
Application #:
12128654
Filing Dt:
05/29/2008
Publication #:
US20090021314
Pub Dt:
01/22/2009
Title:
STRUCTURE FOR A PHASE LOCKED LOOP WITH ADJUSTABLE VOLTAGE BASED ON TEMPERATURE
39
Patent #:
7958469
Issue Dt:
06/07/2011
Application #:
12128678
Filing Dt:
05/29/2008
Publication #:
US20090007047
Pub Dt:
01/01/2009
Title:
DESIGN STRUCTURE FOR A PHASE LOCKED LOOP WITH STABILIZED DYNAMIC RESPONSE
40
Patent #:
7913199
Issue Dt:
03/22/2011
Application #:
12128754
Filing Dt:
05/29/2008
Publication #:
US20080229270
Pub Dt:
09/18/2008
Title:
DESIGN STRUCTURE FOR A DUTY CYCLE CORRECTION CIRCUIT
41
Patent #:
7733144
Issue Dt:
06/08/2010
Application #:
12128761
Filing Dt:
05/29/2008
Publication #:
US20090295448
Pub Dt:
12/03/2009
Title:
RADIATION HARDENED CMOS MASTER LATCH WITH REDUNDANT CLOCK INPUT CIRCUITS AND DESIGN STRUCTURE THEREFOR
42
Patent #:
7883941
Issue Dt:
02/08/2011
Application #:
12128908
Filing Dt:
05/29/2008
Publication #:
US20090298238
Pub Dt:
12/03/2009
Title:
METHODS FOR FABRICATING MEMORY CELLS AND MEMORY DEVICES INCORPORATING THE SAME
43
Patent #:
8232186
Issue Dt:
07/31/2012
Application #:
12128955
Filing Dt:
05/29/2008
Publication #:
US20090294801
Pub Dt:
12/03/2009
Title:
METHODS OF INTEGRATING REVERSE ESIGE ON NFET AND SIGE CHANNEL ON PFET, AND RELATED STRUCTURE
44
Patent #:
8056039
Issue Dt:
11/08/2011
Application #:
12128973
Filing Dt:
05/29/2008
Publication #:
US20090294973
Pub Dt:
12/03/2009
Title:
INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS
45
Patent #:
7768006
Issue Dt:
08/03/2010
Application #:
12129033
Filing Dt:
05/29/2008
Publication #:
US20090294873
Pub Dt:
12/03/2009
Title:
FIELD EFFECT STRUCTURE AND METHOD INCLUDING SPACER SHAPED METAL GATE WITH ASYMMETRIC SOURCE AND DRAIN REGIONS
46
Patent #:
7883916
Issue Dt:
02/08/2011
Application #:
12129714
Filing Dt:
05/30/2008
Publication #:
US20090294812
Pub Dt:
12/03/2009
Title:
OPTICAL SENSOR INCLUDING STACKED PHOTOSENSITIVE DIODES
47
Patent #:
7893468
Issue Dt:
02/22/2011
Application #:
12129716
Filing Dt:
05/30/2008
Publication #:
US20090294813
Pub Dt:
12/03/2009
Title:
OPTICAL SENSOR INCLUDING STACKED PHOTODIODES
48
Patent #:
8321762
Issue Dt:
11/27/2012
Application #:
12129778
Filing Dt:
05/30/2008
Publication #:
US20080244353
Pub Dt:
10/02/2008
Title:
METHOD FOR CREATING AN ERROR CORRECTION CODING SCHEME
49
Patent #:
7617085
Issue Dt:
11/10/2009
Application #:
12129813
Filing Dt:
05/30/2008
Publication #:
US20080229193
Pub Dt:
09/18/2008
Title:
PROGRAM PRODUCT SUPPORTING SPECIFICATION OF SIGNALS FOR SIMULATION RESULT VIEWING
50
Patent #:
8037085
Issue Dt:
10/11/2011
Application #:
12129976
Filing Dt:
05/30/2008
Publication #:
US20080228694
Pub Dt:
09/18/2008
Title:
PREDICATE SELECTION IN BIT-LEVEL COMPOSITIONAL TRANSFORMATIONS
51
Patent #:
8037215
Issue Dt:
10/11/2011
Application #:
12130167
Filing Dt:
05/30/2008
Publication #:
US20090144738
Pub Dt:
06/04/2009
Title:
PERFORMANCE EVALUATION OF ALGORITHMIC TASKS AND DYNAMIC PARAMETERIZATION ON MULTI-CORE PROCESSING SYSTEMS
52
Patent #:
8185779
Issue Dt:
05/22/2012
Application #:
12130216
Filing Dt:
05/30/2008
Publication #:
US20080228687
Pub Dt:
09/18/2008
Title:
CONTROLLING COMPUTER STORAGE SYSTEMS
53
Patent #:
7738284
Issue Dt:
06/15/2010
Application #:
12130408
Filing Dt:
05/30/2008
Publication #:
US20080225574
Pub Dt:
09/18/2008
Title:
MEMORY CELL WITH INDEPENDENT-GATE CONTROLLED ACCESS DEVICES AND MEMORY USING THE CELL
54
Patent #:
8278197
Issue Dt:
10/02/2012
Application #:
12130460
Filing Dt:
05/30/2008
Publication #:
US20090294850
Pub Dt:
12/03/2009
Title:
METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE
55
Patent #:
8010932
Issue Dt:
08/30/2011
Application #:
12130476
Filing Dt:
05/30/2008
Publication #:
US20080229260
Pub Dt:
09/18/2008
Title:
STRUCTURE FOR AUTOMATED TRANSISTOR TUNING IN AN INTEGRATED CIRCUIT DESIGN
56
Patent #:
8018384
Issue Dt:
09/13/2011
Application #:
12130562
Filing Dt:
05/30/2008
Publication #:
US20090015485
Pub Dt:
01/15/2009
Title:
METHOD AND APPARATUS FOR PACKAGING AN INTEGRATED CHIP AND ANTENNA
57
Patent #:
7982274
Issue Dt:
07/19/2011
Application #:
12130563
Filing Dt:
05/30/2008
Publication #:
US20080230849
Pub Dt:
09/25/2008
Title:
DEVICE COMPRISING DOPED NANO-COMPONENT
58
Patent #:
7913201
Issue Dt:
03/22/2011
Application #:
12130644
Filing Dt:
05/30/2008
Publication #:
US20080288910
Pub Dt:
11/20/2008
Title:
STRUCTURE FOR ESTIMATING POWER CONSUMPTION OF INTEGRATED CIRCUITRY
59
Patent #:
8027825
Issue Dt:
09/27/2011
Application #:
12130675
Filing Dt:
05/30/2008
Publication #:
US20080288230
Pub Dt:
11/20/2008
Title:
STRUCTURE FOR TESTING AN OPERATION OF INTEGRATED CIRCUITRY
60
Patent #:
7782995
Issue Dt:
08/24/2010
Application #:
12130724
Filing Dt:
05/30/2008
Publication #:
US20090116610
Pub Dt:
05/07/2009
Title:
LOW LATENCY COUNTER EVENT INDICATION
61
Patent #:
7913041
Issue Dt:
03/22/2011
Application #:
12130752
Filing Dt:
05/30/2008
Publication #:
US20080263278
Pub Dt:
10/23/2008
Title:
CACHE RECONFIGURATION BASED ON ANALYZING ONE OR MORE CHARACTERISTICS OF RUN-TIME PERFORMANCE DATA OR SOFTWARE HINT
62
Patent #:
7831816
Issue Dt:
11/09/2010
Application #:
12130990
Filing Dt:
05/30/2008
Publication #:
US20090300332
Pub Dt:
12/03/2009
Title:
NON-DESTRUCTIVE SIDEBAND READING OF PROCESSOR STATE INFORMATION
63
Patent #:
7755159
Issue Dt:
07/13/2010
Application #:
12131330
Filing Dt:
06/02/2008
Publication #:
US20080230875
Pub Dt:
09/25/2008
Title:
DUV LASER ANNEALING AND STABILIZATION OF SICOH FILMS
64
Patent #:
8020138
Issue Dt:
09/13/2011
Application #:
12131476
Filing Dt:
06/02/2008
Publication #:
US20090295402
Pub Dt:
12/03/2009
Title:
VOLTAGE ISLAND PERFORMANCE/LEAKAGE SCREEN MONITOR FOR IP CHARACTERIZATION
65
Patent #:
7737032
Issue Dt:
06/15/2010
Application #:
12131973
Filing Dt:
06/03/2008
Publication #:
US20080268600
Pub Dt:
10/30/2008
Title:
MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS
66
Patent #:
7897428
Issue Dt:
03/01/2011
Application #:
12131988
Filing Dt:
06/03/2008
Publication #:
US20090294814
Pub Dt:
12/03/2009
Title:
THREE-DIMENSIONAL INTEGRATED CIRCUITS AND TECHNIQUES FOR FABRICATION THEREOF
67
Patent #:
7955887
Issue Dt:
06/07/2011
Application #:
12132029
Filing Dt:
06/03/2008
Publication #:
US20090297091
Pub Dt:
12/03/2009
Title:
TECHNIQUES FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION
68
Patent #:
NONE
Issue Dt:
Application #:
12132166
Filing Dt:
06/03/2008
Publication #:
US20090166861
Pub Dt:
07/02/2009
Title:
WIRE BONDING OF ALUMINUM-FREE METALLIZATION LAYERS BY SURFACE CONDITIONING
69
Patent #:
7737528
Issue Dt:
06/15/2010
Application #:
12132337
Filing Dt:
06/03/2008
Publication #:
US20090294901
Pub Dt:
12/03/2009
Title:
STRUCTURE AND METHOD OF FORMING ELECTRICALLY BLOWN METAL FUSES FOR INTEGRATED CIRCUITS
70
Patent #:
9183286
Issue Dt:
11/10/2015
Application #:
12132561
Filing Dt:
06/03/2008
Publication #:
US20080235220
Pub Dt:
09/25/2008
Title:
METHODOLOGIES AND ANALYTICS TOOLS FOR IDENTIFYING WHITE SPACE OPPORTUNITIES IN A GIVEN INDUSTRY
71
Patent #:
7816237
Issue Dt:
10/19/2010
Application #:
12132698
Filing Dt:
06/04/2008
Publication #:
US20080233687
Pub Dt:
09/25/2008
Title:
ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION
72
Patent #:
8067805
Issue Dt:
11/29/2011
Application #:
12132705
Filing Dt:
06/04/2008
Publication #:
US20080230840
Pub Dt:
09/25/2008
Title:
ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION
73
Patent #:
7552417
Issue Dt:
06/23/2009
Application #:
12132710
Filing Dt:
06/04/2008
Publication #:
US20080232675
Pub Dt:
09/25/2008
Title:
SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS
74
Patent #:
7737563
Issue Dt:
06/15/2010
Application #:
12132734
Filing Dt:
06/04/2008
Publication #:
US20090302427
Pub Dt:
12/10/2009
Title:
SEMICONDUCTOR CHIP WITH REINFORCEMENT STRUCTURE
75
Patent #:
7838355
Issue Dt:
11/23/2010
Application #:
12132798
Filing Dt:
06/04/2008
Publication #:
US20090302374
Pub Dt:
12/10/2009
Title:
DIFFERENTIAL NITRIDE PULLBACK TO CREATE DIFFERENTIAL NFET TO PFET DIVOTS FOR IMPROVED PERFORMANCE VERSUS LEAKAGE
76
Patent #:
7902000
Issue Dt:
03/08/2011
Application #:
12132865
Filing Dt:
06/04/2008
Publication #:
US20090302402
Pub Dt:
12/10/2009
Title:
MUGFET WITH STUB SOURCE AND DRAIN REGIONS
77
Patent #:
7928527
Issue Dt:
04/19/2011
Application #:
12132875
Filing Dt:
06/04/2008
Publication #:
US20090302406
Pub Dt:
12/10/2009
Title:
DELAMINATION AND CRACK RESISTANT IMAGE SENSOR STRUCTURES AND METHODS
78
Patent #:
7839221
Issue Dt:
11/23/2010
Application #:
12132960
Filing Dt:
06/04/2008
Publication #:
US20080246522
Pub Dt:
10/09/2008
Title:
PHASE LOCKED LOOP AND METHOD FOR ADJUSTING THE FREQUENCY AND PHASE IN THE PHASE LOCKED LOOP
79
Patent #:
8709855
Issue Dt:
04/29/2014
Application #:
12133379
Filing Dt:
06/05/2008
Publication #:
US20090305499
Pub Dt:
12/10/2009
Title:
INTRALEVEL CONDUCTIVE LIGHT SHIELD
80
Patent #:
8158988
Issue Dt:
04/17/2012
Application #:
12133380
Filing Dt:
06/05/2008
Publication #:
US20090303366
Pub Dt:
12/10/2009
Title:
INTERLEVEL CONDUCTIVE LIGHT SHIELD
81
Patent #:
8390038
Issue Dt:
03/05/2013
Application #:
12133425
Filing Dt:
06/05/2008
Publication #:
US20080232025
Pub Dt:
09/25/2008
Title:
MIM CAPACITOR AND METHOD OF MAKING SAME
82
Patent #:
NONE
Issue Dt:
Application #:
12133480
Filing Dt:
06/05/2008
Publication #:
US20090307636
Pub Dt:
12/10/2009
Title:
SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS
83
Patent #:
8049526
Issue Dt:
11/01/2011
Application #:
12133724
Filing Dt:
06/05/2008
Publication #:
US20090306815
Pub Dt:
12/10/2009
Title:
ENHANCED SPEED SORTING OF MICROPROCESSORS AT WAFER TEST
84
Patent #:
7821081
Issue Dt:
10/26/2010
Application #:
12133817
Filing Dt:
06/05/2008
Publication #:
US20090302369
Pub Dt:
12/10/2009
Title:
METHOD AND APPARATUS FOR FLATBAND VOLTAGE TUNING OF HIGH-K FIELD EFFECT TRANSISTORS
85
Patent #:
8023655
Issue Dt:
09/20/2011
Application #:
12134113
Filing Dt:
06/05/2008
Publication #:
US20090327717
Pub Dt:
12/31/2009
Title:
SYSTEM, METHOD, AND SERVICE FOR TRACING TRAITORS FROM CONTENT PROTECTION CIRCUMVENTION DEVICES
86
Patent #:
7728614
Issue Dt:
06/01/2010
Application #:
12134748
Filing Dt:
06/06/2008
Publication #:
US20090302860
Pub Dt:
12/10/2009
Title:
OPERATING CHARACTERISTIC MEASUREMENT DEVICE AND METHODS THEREOF
87
Patent #:
7948077
Issue Dt:
05/24/2011
Application #:
12134883
Filing Dt:
06/06/2008
Publication #:
US20080315403
Pub Dt:
12/25/2008
Title:
INTEGRATED CIRCUIT CHIP MODULE WITH MICROCHANNEL COOLING DEVICE HAVING SPECIFIC FLUID CHANNEL ARRANGEMENT
88
Patent #:
7886237
Issue Dt:
02/08/2011
Application #:
12135231
Filing Dt:
06/09/2008
Publication #:
US20080235639
Pub Dt:
09/25/2008
Title:
METHOD OF GENERATING A FUNCTIONAL DESIGN STRUCTURE
89
Patent #:
7962322
Issue Dt:
06/14/2011
Application #:
12135232
Filing Dt:
06/09/2008
Publication #:
US20080234997
Pub Dt:
09/25/2008
Title:
DESIGN STRUCTURE FOR COMPENSATING FOR VARIANCES OF A BURIED RESISTOR IN AN INTEGRATED CIRCUIT
90
Patent #:
8101505
Issue Dt:
01/24/2012
Application #:
12135242
Filing Dt:
06/09/2008
Publication #:
US20090302416
Pub Dt:
12/10/2009
Title:
PROGRAMMABLE ELECTRICAL FUSE
91
Patent #:
7955160
Issue Dt:
06/07/2011
Application #:
12135315
Filing Dt:
06/09/2008
Publication #:
US20090305616
Pub Dt:
12/10/2009
Title:
GLASS MOLD POLISHING METHOD AND STRUCTURE
92
Patent #:
7763507
Issue Dt:
07/27/2010
Application #:
12135478
Filing Dt:
06/09/2008
Publication #:
US20090140396
Pub Dt:
06/04/2009
Title:
STRESSED INTERLAYER DIELECTRIC WITH REDUCED PROBABILITY FOR VOID GENERATION IN A SEMICONDUCTOR DEVICE BY USING AN INTERMEDIATE ETCH CONTROL LAYER OF INCREASED THICKNESS
93
Patent #:
7707238
Issue Dt:
04/27/2010
Application #:
12135498
Filing Dt:
06/09/2008
Publication #:
US20080275933
Pub Dt:
11/06/2008
Title:
SYSTEMS AND METHODS FOR STORAGE AREA NETWORK DESIGN
94
Patent #:
7962234
Issue Dt:
06/14/2011
Application #:
12135522
Filing Dt:
06/09/2008
Publication #:
US20090306807
Pub Dt:
12/10/2009
Title:
MULTIDIMENSIONAL PROCESS WINDOW OPTIMIZATION IN SEMICONDUCTOR MANUFACTURING
95
Patent #:
8494784
Issue Dt:
07/23/2013
Application #:
12135551
Filing Dt:
06/09/2008
Publication #:
US20090012720
Pub Dt:
01/08/2009
Title:
System and Method for Identification of MicroRNA Target Sites and Corresponding Targeting MicroRNA Sequences
96
Patent #:
7795068
Issue Dt:
09/14/2010
Application #:
12136158
Filing Dt:
06/10/2008
Publication #:
US20080248624
Pub Dt:
10/09/2008
Title:
METHOD OF MAKING INTEGRATED CIRCUIT (IC) INCLUDING AT LEAST ONE STORAGE CELL
97
Patent #:
8115659
Issue Dt:
02/14/2012
Application #:
12136187
Filing Dt:
06/10/2008
Publication #:
US20090307697
Pub Dt:
12/10/2009
Title:
METHOD AND APPARATUS FOR EFFICIENT GATHERING OF INFORMATION IN A MULTICORE SYSTEM
98
Patent #:
8013419
Issue Dt:
09/06/2011
Application #:
12136246
Filing Dt:
06/10/2008
Publication #:
US20090302417
Pub Dt:
12/10/2009
Title:
STRUCTURE AND METHOD TO FORM DUAL SILICIDE E-FUSE
99
Patent #:
7890831
Issue Dt:
02/15/2011
Application #:
12136458
Filing Dt:
06/10/2008
Publication #:
US20090307549
Pub Dt:
12/10/2009
Title:
PROCESSOR TEST SYSTEM UTILIZING FUNCTIONAL REDUNDANCY
100
Patent #:
8234646
Issue Dt:
07/31/2012
Application #:
12136478
Filing Dt:
06/10/2008
Publication #:
US20080243850
Pub Dt:
10/02/2008
Title:
FAULT TOLERANT MUTUAL EXCLUSION LOCKS FOR SHARED MEMORY SYSTEMS
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

Search Results as of: 05/09/2024 03:57 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT