|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
12757433
|
Filing Dt:
|
04/09/2010
|
Publication #:
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|
Pub Dt:
|
10/13/2011
| | | | |
Title:
|
NANOPORE CAPTURE SYSTEM
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|
|
Patent #:
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|
Issue Dt:
|
08/09/2011
|
Application #:
|
12757567
|
Filing Dt:
|
04/09/2010
|
Publication #:
|
|
Pub Dt:
|
08/05/2010
| | | | |
Title:
|
MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
08/02/2011
|
Application #:
|
12757648
|
Filing Dt:
|
04/09/2010
|
Publication #:
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|
Pub Dt:
|
08/05/2010
| | | | |
Title:
|
METHOD OF OPERATING A MEMORY CIRCUIT USING MEMORY CELLS WITH INDEPENDENT-GATE CONTROLLED ACCESS DEVICES
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|
Patent #:
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|
Issue Dt:
|
12/04/2012
|
Application #:
|
12758939
|
Filing Dt:
|
04/13/2010
|
Publication #:
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|
Pub Dt:
|
10/13/2011
| | | | |
Title:
|
NANOWIRE CIRCUITS IN MATCHED DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
01/04/2011
|
Application #:
|
12759015
|
Filing Dt:
|
04/13/2010
|
Publication #:
|
|
Pub Dt:
|
08/05/2010
| | | | |
Title:
|
CIRCUIT AND DESIGN STRUCTURE FOR SYNCHRONIZING MULTIPLE DIGITAL SIGNALS
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|
Patent #:
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|
Issue Dt:
|
10/30/2012
|
Application #:
|
12759785
|
Filing Dt:
|
04/14/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
SEMICONDUCTOR DEVICE COMPRISING METAL GATES AND A SILICON CONTAINING RESISTOR FORMED ON AN ISOLATION STRUCTURE
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12759969
|
Filing Dt:
|
04/14/2010
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
Title:
|
ETSOI CMOS ARCHITECTURE WITH DUAL BACKSIDE STRESSORS
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|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12760047
|
Filing Dt:
|
04/14/2010
|
Publication #:
|
|
Pub Dt:
|
08/05/2010
| | | | |
Title:
|
OPERATING CHARACTERISTIC MEASUREMENT DEVICE AND METHODS THEREOF
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12760101
|
Filing Dt:
|
04/14/2010
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
Title:
|
ANALYTICS FOR SETTING UP STRATEGIC INVENTORY SYSTEMS TO HANDLE SMALL LOT ORDERS IN THE STEEL INDUSTRY
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|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
12760250
|
Filing Dt:
|
04/14/2010
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
Title:
|
RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER
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|
|
Patent #:
|
|
Issue Dt:
|
08/21/2012
|
Application #:
|
12760368
|
Filing Dt:
|
04/14/2010
|
Publication #:
|
|
Pub Dt:
|
12/16/2010
| | | | |
Title:
|
OPTICAL WAVELENGTH SWITCH
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
12761394
|
Filing Dt:
|
04/16/2010
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
Title:
|
HEAD COMPRISING A CRYSTALLINE ALUMINA LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
12761780
|
Filing Dt:
|
04/16/2010
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
Title:
|
PROGRAMMABLE ANTI-FUSE STRUCTURES WITH CONDUCTIVE MATERIAL ISLANDS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12762427
|
Filing Dt:
|
04/19/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
FINFET TRANSISTOR AND CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12762832
|
Filing Dt:
|
04/19/2010
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
Title:
|
SOURCE/DRAIN TECHNOLOGY FOR THE CARBON NANO-TUBE/GRAPHENE CMOS WITH A SINGLE SELF-ALIGNED METAL SILICIDE PROCESS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12763324
|
Filing Dt:
|
04/20/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12763550
|
Filing Dt:
|
04/20/2010
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
Title:
|
CMP-FIRST DAMASCENE PROCESS SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12764329
|
Filing Dt:
|
04/21/2010
|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
Title:
|
MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2011
|
Application #:
|
12765483
|
Filing Dt:
|
04/22/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
GRAPHENE-BASED TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12765646
|
Filing Dt:
|
04/22/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12765950
|
Filing Dt:
|
04/23/2010
|
Publication #:
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|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
SEMICONDUCTOR DIODE STRUCTURE OPERATION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12766342
|
Filing Dt:
|
04/23/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
ON-CHIP HEATER AND METHODS FOR FABRICATION THEREOF AND USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12766859
|
Filing Dt:
|
04/24/2010
|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
Title:
|
THIN BODY SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12767261
|
Filing Dt:
|
04/26/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12767375
|
Filing Dt:
|
04/26/2010
|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
Title:
|
HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12768031
|
Filing Dt:
|
04/27/2010
|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
Title:
|
EFFICIENTLY APPLYING A SINGLE TIMING ASSERTION TO MULTIPLE TIMING POINTS IN A CIRCUIT USING CREATING A DEFFINITION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
12768267
|
Filing Dt:
|
04/27/2010
|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
Title:
|
STRUCTURES AND METHODS FOR AIR GAP INTEGRATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12769124
|
Filing Dt:
|
04/28/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
ENHANCED ELECTROMIGRATION PERFORMANCE OF COPPER LINES IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY SURFACE ALLOYING
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|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12770254
|
Filing Dt:
|
04/29/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
MICROELECTRONIC STRUCTURE INCLUDING AIR GAP
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|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12770791
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
DECOMPOSITION WITH MULTIPLE EXPOSURES IN A PROCESS WINDOW BASED OPC FLOW USING TOLERANCE BANDS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12770792
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
METHOD TO OPTIMIZE WORK FUNCTION IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
12770948
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
THERMAL INTERFACE MATERIAL, TEST STRUCTURE AND METHOD OF USE
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|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
12771293
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
NON-VOLATILE MEMORY BASED RELIABILITY AND AVAILABILITY MECHANISMS FOR A COMPUTING DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
12771387
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
ON-CHIP NON-VOLATILE STORAGE OF A TEST-TIME PROFILE FOR EFFICIENCY AND PERFORMANCE CONTROL
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|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12771404
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
ENHANCED ANALYSIS OF ARRAY-BASED NETLISTS VIA PHASE ABSTRACTION
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|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
12771479
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
Tracking Array Data Contents Across Three-Valued Read and Write Operations
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|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
12771697
|
Filing Dt:
|
04/30/2010
|
Publication #:
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|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
High Performance Compliant Wafer Test Probe
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|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
12772436
|
Filing Dt:
|
05/03/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE
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|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12772451
|
Filing Dt:
|
05/03/2010
|
Publication #:
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|
Pub Dt:
|
08/19/2010
| | | | |
Title:
|
SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
12772560
|
Filing Dt:
|
05/03/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
SESSION LIFE-CYCLE QUALITY-OF-EXPERIENCE ORCHESTRATION FOR VOD FLOWS IN WIRELESS BROADBAND NETWORKS
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|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12773306
|
Filing Dt:
|
05/04/2010
|
Publication #:
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|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
STRUCTURE AND METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES HAVING SELF-ALIGNED DIELECTRIC CAPS
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|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
12774766
|
Filing Dt:
|
05/06/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
Method for Supporting Multiple Libraries Characterized at Different Process, Voltage, and Temperature Points
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|
|
Patent #:
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|
Issue Dt:
|
08/16/2011
|
Application #:
|
12775084
|
Filing Dt:
|
05/06/2010
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
Title:
|
OPTOELECTRONIC DEVICE WITH GERMANIUM PHOTODETECTOR
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|
|
Patent #:
|
|
Issue Dt:
|
11/20/2012
|
Application #:
|
12775107
|
Filing Dt:
|
05/06/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ENHANCING INVESTIGATION OF VARIABILITY BY INCLUSION OF SIMILAR OBJECTS WITH KNOWN DIFFERENCES TO THE ORIGINAL ONES
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|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12775532
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM
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|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
12775607
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
MINIMIZING MEMORY ARRAY REPRESENTATIONS FOR ENHANCED SYNTHESIS AND VERIFICATION
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|
|
Patent #:
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|
Issue Dt:
|
12/18/2012
|
Application #:
|
12775622
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ELIMINATING, COALESCING, OR BYPASSING PORTS IN MEMORY ARRAY REPRESENTATIONS
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|
|
Patent #:
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|
Issue Dt:
|
12/04/2012
|
Application #:
|
12775863
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY AN IN SITU ETCH PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
12775939
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
METHOD AND STRUCTURE OF PHOTOVOLTAIC GRID STACKS BY SOLUTION BASED PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12775970
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS
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|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
12776369
|
Filing Dt:
|
05/08/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12776444
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
MILLIMETER-WAVE SWITCHES AND ATTENUATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
12776512
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
ENHANCING UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING STI STRUCTURES AFTER THE GROWTH PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12776742
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
REDUCED SILICON THICKNESS OF N-CHANNEL TRANSISTORS IN SOI CMOS DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
12776829
|
Filing Dt:
|
05/10/2010
|
Publication #:
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|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12776861
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12777177
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
Computer system wafer integrating different dies in stacked master-slave structures
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
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12777715
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Filing Dt:
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05/11/2010
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Publication #:
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Pub Dt:
|
11/17/2011
| | | | |
Title:
|
EFFECTIVE CYCLE TIME MANAGEMENT EMPLOYING A MULTI-HORIZON MODEL
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Patent #:
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Issue Dt:
|
01/01/2013
|
Application #:
|
12777881
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Filing Dt:
|
05/11/2010
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Publication #:
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Pub Dt:
|
11/17/2011
| | | | |
Title:
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TFET WITH NANOWIRE SOURCE
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|
Patent #:
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|
Issue Dt:
|
12/04/2012
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Application #:
|
12778315
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Filing Dt:
|
05/12/2010
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Publication #:
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Pub Dt:
|
11/17/2011
| | | | |
Title:
|
NANOWIRE TUNNEL FIELD EFFECT TRANSISTORS
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Patent #:
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|
Issue Dt:
|
05/14/2013
|
Application #:
|
12778319
|
Filing Dt:
|
05/12/2010
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Publication #:
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Pub Dt:
|
11/17/2011
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES USING REPLACEMENT GATE AND METHODS OF MANUFACTURE
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Patent #:
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|
Issue Dt:
|
05/06/2014
|
Application #:
|
12778457
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Filing Dt:
|
05/12/2010
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Publication #:
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Pub Dt:
|
11/17/2011
| | | | |
Title:
|
COMPREHENSIVE ANALYSIS OF QUEUE TIMES IN MICROELECTRONIC MANUFACTURING
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Patent #:
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Issue Dt:
|
05/21/2013
|
Application #:
|
12778517
|
Filing Dt:
|
05/12/2010
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Publication #:
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|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
GENERATION OF MUTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
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|
Patent #:
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|
Issue Dt:
|
08/27/2013
|
Application #:
|
12778526
|
Filing Dt:
|
05/12/2010
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Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
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|
Patent #:
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|
Issue Dt:
|
05/20/2014
|
Application #:
|
12778897
|
Filing Dt:
|
05/12/2010
|
Publication #:
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|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL
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|
Patent #:
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|
Issue Dt:
|
04/30/2013
|
Application #:
|
12779087
|
Filing Dt:
|
05/13/2010
|
Publication #:
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|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS
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|
Patent #:
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|
Issue Dt:
|
06/07/2011
|
Application #:
|
12780029
|
Filing Dt:
|
05/14/2010
|
Publication #:
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|
Pub Dt:
|
12/23/2010
| | | | |
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
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|
Patent #:
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|
Issue Dt:
|
05/13/2014
|
Application #:
|
12780138
|
Filing Dt:
|
05/14/2010
|
Publication #:
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|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
METHOD AND SYSTEM TO PREDICT A NUMBER OF ELECTROMIGRATION CRITICAL ELEMENTS
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
12780242
|
Filing Dt:
|
05/14/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
METHOD OF PATTERNING THIN METAL FILMS
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|
|
Patent #:
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|
Issue Dt:
|
09/09/2014
|
Application #:
|
12781514
|
Filing Dt:
|
05/17/2010
|
Publication #:
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|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
FET Nanopore Sensor
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|
|
Patent #:
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|
Issue Dt:
|
08/23/2011
|
Application #:
|
12781851
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12782320
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
BODY CONTACT STRUCTURES AND METHODS OF MANUFACTURING THE SAME
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|
|
Patent #:
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|
Issue Dt:
|
04/16/2013
|
Application #:
|
12782337
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
METHODS AND SYSTEMS TO MEET TECHNOLOGY PATTERN DENSITY REQUIREMENTS OF SEMICONDUCTOR FABRICATION PROCESSES
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|
Patent #:
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|
Issue Dt:
|
06/14/2011
|
Application #:
|
12782388
|
Filing Dt:
|
05/18/2010
|
Publication #:
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|
Pub Dt:
|
09/09/2010
| | | | |
Title:
|
PARTIALLY AND FULLY SILICIDED GATE STACKS
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|
Patent #:
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|
Issue Dt:
|
01/01/2013
|
Application #:
|
12782407
|
Filing Dt:
|
05/18/2010
|
Publication #:
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|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
EQUATION BASED RETARGETING OF DESIGN LAYOUTS
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|
Patent #:
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|
Issue Dt:
|
05/21/2013
|
Application #:
|
12783676
|
Filing Dt:
|
05/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
GRAPHENE CHANNEL-BASED DEVICES AND METHODS FOR FABRICATION THEREOF
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|
|
Patent #:
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|
Issue Dt:
|
02/17/2015
|
Application #:
|
12783914
|
Filing Dt:
|
05/20/2010
|
Publication #:
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|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
SHALLOW TRENCH ISOLATION EXTENSION
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|
|
Patent #:
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|
Issue Dt:
|
05/28/2013
|
Application #:
|
12784150
|
Filing Dt:
|
05/20/2010
|
Publication #:
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|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
ELECTRICAL DESIGN SPACE EXPLORATION
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|
|
Patent #:
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|
Issue Dt:
|
06/18/2013
|
Application #:
|
12784583
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
ASYMMETRIC SILICON-ON-INSULATOR (SOI) JUNCTION FIELD EFFECT TRANSISTOR (JFET) AND A METHOD OF FORMING THE ASYMMETRICAL SOI JFET
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|
Patent #:
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|
Issue Dt:
|
08/21/2012
|
Application #:
|
12784688
|
Filing Dt:
|
05/21/2010
|
Publication #:
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|
Pub Dt:
|
12/09/2010
| | | | |
Title:
|
THIN SUBSTRATE FABRICATION USING STRESS-INDUCED SUBSTRATE SPALLING
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|
|
Patent #:
|
|
Issue Dt:
|
11/22/2011
|
Application #:
|
12784819
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
STRAIN TRANSFORMATION IN BIAXIALLY STRAINED SOI SUBSTRATES FOR PERFORMANCE ENHANCEMENT OF P-CHANNEL AND N-CHANNEL TRANSISTORS
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|
|
Patent #:
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|
Issue Dt:
|
04/26/2011
|
Application #:
|
12785007
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
ELECTRO-OPTICAL MEMORY CELL
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|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12785185
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12785435
|
Filing Dt:
|
05/22/2010
|
Publication #:
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|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
METHOD TO IMPROVE REQUIREMENTS, DESIGN MANUFACTURING, AND TRANSPORTATION IN MASS MANUFACTURING INDUSTRIES THROUGH ANALYSIS OF DEFECT DATA
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12785726
|
Filing Dt:
|
05/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
HIGH-ASPECT RATIO CONTACT ELEMENT WITH SUPERIOR SHAPE IN A SEMICONDUCTOR DEVICE FOR IMPROVING LINER DEPOSITION
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|
|
Patent #:
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|
Issue Dt:
|
10/09/2012
|
Application #:
|
12785849
|
Filing Dt:
|
05/24/2010
|
Publication #:
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|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
ENHANCED ETCH STOP CAPABILITY DURING PATTERNING OF SILICON NITRIDE INCLUDING LAYER STACKS BY PROVIDING A CHEMICALLY FORMED OXIDE LAYER DURING SEMICONDUCTOR PROCESSING
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|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
12786019
|
Filing Dt:
|
05/24/2010
|
Publication #:
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|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS FORMED BASED ON A SACRIFICIAL MATERIAL
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12786117
|
Filing Dt:
|
05/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
RE-ESTABLISHING A HYDROPHOBIC SURFACE OF SENSITIVE LOW-K DIELECTRICS IN MICROSTRUCTURE DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12786572
|
Filing Dt:
|
05/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
COMPUTING RESISTANCE SENSITIVITIES WITH RESPECT TO GEOMETRIC PARAMETERS OF CONDUCTORS WITH ARBITRARY SHAPES
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|
Patent #:
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|
Issue Dt:
|
04/22/2014
|
Application #:
|
12786956
|
Filing Dt:
|
05/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
ELECTRICALLY PROGRAMMABLE FLOATING COMMON GATE CMOS DEVICE AND APPLICATIONS THEREOF
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|
Patent #:
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|
Issue Dt:
|
03/20/2012
|
Application #:
|
12787417
|
Filing Dt:
|
05/26/2010
|
Publication #:
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|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR TONE INVERTING OF RESIDUAL LAYER TOLERANT IMPRINT LITHOGRAPHY
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|
Patent #:
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|
Issue Dt:
|
03/20/2012
|
Application #:
|
12787429
|
Filing Dt:
|
05/26/2010
|
Publication #:
|
|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR TONE INVERTING OF RESIDUAL LAYER TOLERANT IMPRINT LITHOGRAPHY
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12787919
|
Filing Dt:
|
05/26/2010
|
Publication #:
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|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY
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|
Patent #:
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|
Issue Dt:
|
05/28/2013
|
Application #:
|
12787988
|
Filing Dt:
|
05/26/2010
|
Publication #:
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|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
SELECTING A DATA RESTORE POINT WITH AN OPTIMAL RECOVERY TIME AND RECOVERY POINT
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|
|
Patent #:
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|
Issue Dt:
|
02/08/2011
|
Application #:
|
12788486
|
Filing Dt:
|
05/27/2010
|
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12788832
|
Filing Dt:
|
05/27/2010
|
Publication #:
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|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
HANDLER ATTACHMENT FOR INTEGRATED CIRCUIT FABRICATION
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|
|
Patent #:
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|
Issue Dt:
|
03/25/2014
|
Application #:
|
12788839
|
Filing Dt:
|
05/27/2010
|
Publication #:
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|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
Laser Ablation of Adhesive for Integrated Circuit Fabrication
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|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12788910
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
Differential Cross-Coupled Power Combiner or Divider
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|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12788987
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
SELF-ADJUSTING CRITICAL PATH TIMING OF MULTI-CORE VLSI CHIP
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|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12789013
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH FINFETS AND MIM FIN CAPACITOR
|
|