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Reel/Frame:056987/0001   Pages: 1045
Recorded: 05/12/2021
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18026
Page 95 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
8957519
Issue Dt:
02/17/2015
Application #:
12910075
Filing Dt:
10/22/2010
Publication #:
US20120098133
Pub Dt:
04/26/2012
Title:
STRUCTURE AND METALLIZATION PROCESS FOR ADVANCED TECHNOLOGY NODES
2
Patent #:
8458637
Issue Dt:
06/04/2013
Application #:
12910127
Filing Dt:
10/22/2010
Publication #:
US20120102445
Pub Dt:
04/26/2012
Title:
IMPLEMENTING ENHANCED RLM CONNECTIVITY ON A HIERARCHICAL DESIGN WITH TOP LEVEL PIPELINE REGISTERS
3
Patent #:
8284627
Issue Dt:
10/09/2012
Application #:
12910144
Filing Dt:
10/22/2010
Publication #:
US20120102350
Pub Dt:
04/26/2012
Title:
REDUCING ENERGY CONSUMPTION AND OPTIMIZING WORKLOAD AND PERFORMANCE IN MULTI-TIER STORAGE SYSTEMS USING EXTENT-LEVEL DYNAMIC TIERING
4
Patent #:
8448123
Issue Dt:
05/21/2013
Application #:
12910214
Filing Dt:
10/22/2010
Publication #:
US20120102446
Pub Dt:
04/26/2012
Title:
IMPLEMENTING NET ROUTING WITH ENHANCED CORRELATION OF PRE-BUFFERED AND POST-BUFFERED ROUTES
5
Patent #:
8324009
Issue Dt:
12/04/2012
Application #:
12910236
Filing Dt:
10/22/2010
Publication #:
US20110039020
Pub Dt:
02/17/2011
Title:
MAGNETIC MATERIALS HAVING SUPERPARAMAGNETIC PARTICLES
6
Patent #:
8495547
Issue Dt:
07/23/2013
Application #:
12910336
Filing Dt:
10/22/2010
Publication #:
US20110113398
Pub Dt:
05/12/2011
Title:
PROVIDING SECONDARY POWER PINS IN INTEGRATED CIRCUIT DESIGN
7
Patent #:
NONE
Issue Dt:
Application #:
12910946
Filing Dt:
10/25/2010
Publication #:
US20110156858
Pub Dt:
06/30/2011
Title:
SEMICONDUCTOR DEVICE COMPRISING METAL-BASED eFUSES OF ENHANCED PROGRAMMING EFFICIENCY BY ENHANCING METAL AGGLOMERATION AND/OR VOIDING
8
Patent #:
8389401
Issue Dt:
03/05/2013
Application #:
12910979
Filing Dt:
10/25/2010
Publication #:
US20110156270
Pub Dt:
06/30/2011
Title:
CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES FORMED ON THE BASIS OF A PARTIALLY APPLIED ACTIVATION LAYER
9
Patent #:
8349716
Issue Dt:
01/08/2013
Application #:
12911186
Filing Dt:
10/25/2010
Publication #:
US20120098042
Pub Dt:
04/26/2012
Title:
SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE
10
Patent #:
8898605
Issue Dt:
11/25/2014
Application #:
12911327
Filing Dt:
10/25/2010
Publication #:
US20120102444
Pub Dt:
04/26/2012
Title:
ON-CHIP TUNABLE TRANSMISSION LINES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
11
Patent #:
8440497
Issue Dt:
05/14/2013
Application #:
12911833
Filing Dt:
10/26/2010
Publication #:
US20120100664
Pub Dt:
04/26/2012
Title:
FABRICATING KESTERITE SOLAR CELLS AND PARTS THEREOF
12
Patent #:
8356267
Issue Dt:
01/15/2013
Application #:
12912819
Filing Dt:
10/27/2010
Publication #:
US20120110536
Pub Dt:
05/03/2012
Title:
STATISTICAL METHOD FOR HIERARCHICALLY ROUTING LAYOUT UTILIZING FLAT ROUTE INFORMATION
13
Patent #:
8681839
Issue Dt:
03/25/2014
Application #:
12912883
Filing Dt:
10/27/2010
Publication #:
US20120106687
Pub Dt:
05/03/2012
Title:
Calibration of Multiple Parallel Data Communications Lines for High Skew Conditions
14
Patent #:
8685847
Issue Dt:
04/01/2014
Application #:
12912897
Filing Dt:
10/27/2010
Publication #:
US20120104498
Pub Dt:
05/03/2012
Title:
SEMICONDUCTOR DEVICE HAVING LOCALIZED EXTREMELY THIN SILICON ON INSULATOR CHANNEL REGION
15
Patent #:
8458634
Issue Dt:
06/04/2013
Application #:
12912919
Filing Dt:
10/27/2010
Publication #:
US20120110532
Pub Dt:
05/03/2012
Title:
LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS
16
Patent #:
8592266
Issue Dt:
11/26/2013
Application #:
12912963
Filing Dt:
10/27/2010
Publication #:
US20120104469
Pub Dt:
05/03/2012
Title:
REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE
17
Patent #:
NONE
Issue Dt:
Application #:
12913064
Filing Dt:
10/27/2010
Publication #:
US20120106539
Pub Dt:
05/03/2012
Title:
Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant Lines
18
Patent #:
8765491
Issue Dt:
07/01/2014
Application #:
12914095
Filing Dt:
10/28/2010
Publication #:
US20120104500
Pub Dt:
05/03/2012
Title:
SHALLOW TRENCH ISOLATION RECESS REPAIR USING SPACER FORMATION PROCESS
19
Patent #:
8390079
Issue Dt:
03/05/2013
Application #:
12914132
Filing Dt:
10/28/2010
Publication #:
US20120104512
Pub Dt:
05/03/2012
Title:
SEALED AIR GAP FOR SEMICONDUCTOR CHIP
20
Patent #:
8429570
Issue Dt:
04/23/2013
Application #:
12914154
Filing Dt:
10/28/2010
Publication #:
US20120110522
Pub Dt:
05/03/2012
Title:
Pattern Recognition with Edge Correction for Design Based Metrology
21
Patent #:
8381141
Issue Dt:
02/19/2013
Application #:
12914212
Filing Dt:
10/28/2010
Publication #:
US20120107969
Pub Dt:
05/03/2012
Title:
METHOD AND SYSTEM FOR COMPARING LITHOGRAPHIC PROCESSING CONDITIONS AND OR DATA PREPARATION PROCESSES
22
Patent #:
8383500
Issue Dt:
02/26/2013
Application #:
12914234
Filing Dt:
10/28/2010
Publication #:
US20110186931
Pub Dt:
08/04/2011
Title:
SEMICONDUCTOR DEVICE FORMED BY A REPLACEMENT GATE APPROACH BASED ON AN EARLY WORK FUNCTION METAL
23
Patent #:
NONE
Issue Dt:
Application #:
12914343
Filing Dt:
10/28/2010
Publication #:
US20110186937
Pub Dt:
08/04/2011
Title:
ADJUSTMENT OF TRANSISTOR CHARACTERISTICS BASED ON A LATE WELL IMPLANTATION
24
Patent #:
8409942
Issue Dt:
04/02/2013
Application #:
12914570
Filing Dt:
10/28/2010
Publication #:
US20110186915
Pub Dt:
08/04/2011
Title:
REPLACEMENT GATE APPROACH BASED ON A REVERSE OFFSET SPACER APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION
25
Patent #:
8253234
Issue Dt:
08/28/2012
Application #:
12914644
Filing Dt:
10/28/2010
Publication #:
US20120105144
Pub Dt:
05/03/2012
Title:
OPTIMIZED SEMICONDUCTOR PACKAGING IN A THREE-DIMENSIONAL STACK
26
Patent #:
8048726
Issue Dt:
11/01/2011
Application #:
12914663
Filing Dt:
10/28/2010
Publication #:
US20110189825
Pub Dt:
08/04/2011
Title:
SOI SEMICONDUCTOR DEVICE WITH REDUCED TOPOGRAPHY ABOVE A SUBSTRATE WINDOW AREA
27
Patent #:
8405998
Issue Dt:
03/26/2013
Application #:
12914697
Filing Dt:
10/28/2010
Publication #:
US20120106074
Pub Dt:
05/03/2012
Title:
HEAT SINK INTEGRATED POWER DELIVERY AND DISTRIBUTION FOR INTEGRATED CIRCUITS
28
Patent #:
8427833
Issue Dt:
04/23/2013
Application #:
12914730
Filing Dt:
10/28/2010
Publication #:
US20120105145
Pub Dt:
05/03/2012
Title:
Thermal Power Plane for Integrated Circuits
29
Patent #:
8631058
Issue Dt:
01/14/2014
Application #:
12915003
Filing Dt:
10/28/2010
Publication #:
US20110106870
Pub Dt:
05/05/2011
Title:
PROVIDING NONDETERMINISTIC DATA
30
Patent #:
8048748
Issue Dt:
11/01/2011
Application #:
12915216
Filing Dt:
10/29/2010
Publication #:
US20110189831
Pub Dt:
08/04/2011
Title:
REDUCING CONTAMINATION IN A PROCESS FLOW OF FORMING A CHANNEL SEMICONDUCTOR ALLOY IN A SEMICONDUCTOR DEVICE
31
Patent #:
8232164
Issue Dt:
07/31/2012
Application #:
12915463
Filing Dt:
10/29/2010
Publication #:
US20120104538
Pub Dt:
05/03/2012
Title:
DAMASCENE METHOD OF FORMING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE WITH MULTIPLE FIN-SHAPED CHANNEL REGIONS HAVING DIFFERENT WIDTHS
32
Patent #:
8618588
Issue Dt:
12/31/2013
Application #:
12915888
Filing Dt:
10/29/2010
Publication #:
US20120105692
Pub Dt:
05/03/2012
Title:
ANTI-BLOOMING PIXEL SENSOR CELL WITH ACTIVE NEUTRAL DENSITY FILTER, METHODS OF MANUFACTURE, AND DESIGN STRUCTURE
33
Patent #:
8347240
Issue Dt:
01/01/2013
Application #:
12915923
Filing Dt:
10/29/2010
Publication #:
US20120110521
Pub Dt:
05/03/2012
Title:
SPLIT-LAYER DESIGN FOR DOUBLE PATTERNING LITHOGRAPHY
34
Patent #:
8232163
Issue Dt:
07/31/2012
Application #:
12916864
Filing Dt:
11/01/2010
Publication #:
US20120104547
Pub Dt:
05/03/2012
Title:
LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE
35
Patent #:
8232173
Issue Dt:
07/31/2012
Application #:
12917029
Filing Dt:
11/01/2010
Publication #:
US20120104546
Pub Dt:
05/03/2012
Title:
STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME
36
Patent #:
NONE
Issue Dt:
Application #:
12917599
Filing Dt:
11/02/2010
Publication #:
US20110186916
Pub Dt:
08/04/2011
Title:
SEMICONDUCTOR RESISTORS FORMED IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES BY REDUCING CONDUCTIVITY OF A METAL-CONTAINING CAP MATERIAL
37
Patent #:
8198152
Issue Dt:
06/12/2012
Application #:
12917700
Filing Dt:
11/02/2010
Publication #:
US20110210398
Pub Dt:
09/01/2011
Title:
TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND ADAPTED CHANNEL SEMICONDUCTOR MATERIALS
38
Patent #:
9184095
Issue Dt:
11/10/2015
Application #:
12917763
Filing Dt:
11/02/2010
Publication #:
US20110210380
Pub Dt:
09/01/2011
Title:
CONTACT BARS WITH REDUCED FRINGING CAPACITANCE IN A SEMICONDUCTOR DEVICE
39
Patent #:
8105850
Issue Dt:
01/31/2012
Application #:
12917800
Filing Dt:
11/02/2010
Title:
PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE
40
Patent #:
8329531
Issue Dt:
12/11/2012
Application #:
12917870
Filing Dt:
11/02/2010
Publication #:
US20110210427
Pub Dt:
09/01/2011
Title:
STRAIN MEMORIZATION IN STRAINED SOI SUBSTRATES OF SEMICONDUCTOR DEVICES
41
Patent #:
8595328
Issue Dt:
11/26/2013
Application #:
12938411
Filing Dt:
11/03/2010
Publication #:
US20120110394
Pub Dt:
05/03/2012
Title:
SELF-UPDATING NODE CONTROLLER FOR AN ENDPOINT IN A CLOUD COMPUTING ENVIRONMENT
42
Patent #:
8334088
Issue Dt:
12/18/2012
Application #:
12938459
Filing Dt:
11/03/2010
Publication #:
US20110045407
Pub Dt:
02/24/2011
Title:
FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME
43
Patent #:
8473953
Issue Dt:
06/25/2013
Application #:
12939119
Filing Dt:
11/03/2010
Publication #:
US20120023369
Pub Dt:
01/26/2012
Title:
BATCHING TRANSACTIONS TO APPLY TO A DATABASE
44
Patent #:
8507348
Issue Dt:
08/13/2013
Application #:
12939282
Filing Dt:
11/04/2010
Publication #:
US20110211394
Pub Dt:
09/01/2011
Title:
FIELD EFFECT TRANSISTORS FOR A FLASH MEMORY COMPRISING A SELF-ALIGNED CHARGE STORAGE REGION
45
Patent #:
8479578
Issue Dt:
07/09/2013
Application #:
12939471
Filing Dt:
11/04/2010
Publication #:
US20110209548
Pub Dt:
09/01/2011
Title:
ASSESSING METAL STACK INTEGRITY IN SOPHISTICATED SEMICONDUCTOR DEVICES BY MECHANICALLY STRESSING DIE CONTACTS
46
Patent #:
8642407
Issue Dt:
02/04/2014
Application #:
12939506
Filing Dt:
11/04/2010
Publication #:
US20120112246
Pub Dt:
05/10/2012
Title:
DEVICES HAVING REDUCED SUSCEPTIBILITY TO SOFT-ERROR EFFECTS AND METHOD FOR FABRICATION
47
Patent #:
8089105
Issue Dt:
01/03/2012
Application #:
12939520
Filing Dt:
11/04/2010
Publication #:
US20110042779
Pub Dt:
02/24/2011
Title:
FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
48
Patent #:
8580684
Issue Dt:
11/12/2013
Application #:
12939523
Filing Dt:
11/04/2010
Publication #:
US20110210447
Pub Dt:
09/01/2011
Title:
CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES COMPRISING A CONTINUOUS TRANSITION TO METAL LINES OF A METALLIZATION LAYER
49
Patent #:
8236655
Issue Dt:
08/07/2012
Application #:
12939538
Filing Dt:
11/04/2010
Publication #:
US20110045644
Pub Dt:
02/24/2011
Title:
FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
50
Patent #:
8232156
Issue Dt:
07/31/2012
Application #:
12939668
Filing Dt:
11/04/2010
Publication #:
US20120112244
Pub Dt:
05/10/2012
Title:
VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
51
Patent #:
8558695
Issue Dt:
10/15/2013
Application #:
12940095
Filing Dt:
11/05/2010
Publication #:
US20120116580
Pub Dt:
05/10/2012
Title:
Biodegradable Device and Mesh Network for Optimization of Payload Material Delivery
52
Patent #:
8492845
Issue Dt:
07/23/2013
Application #:
12940210
Filing Dt:
11/05/2010
Publication #:
US20120112287
Pub Dt:
05/10/2012
Title:
GATE-TO-GATE RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
53
Patent #:
8332787
Issue Dt:
12/11/2012
Application #:
12940762
Filing Dt:
11/05/2010
Publication #:
US20120117524
Pub Dt:
05/10/2012
Title:
REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT
54
Patent #:
8572315
Issue Dt:
10/29/2013
Application #:
12941016
Filing Dt:
11/17/2016
Publication #:
US20120113786
Pub Dt:
05/10/2012
Title:
SMART OPTIMIZATION OF TRACKS FOR CLOUD COMPUTING
55
Patent #:
8324058
Issue Dt:
12/04/2012
Application #:
12941042
Filing Dt:
11/06/2010
Publication #:
US20120112279
Pub Dt:
05/10/2012
Title:
CONTACTS FOR FET DEVICES
56
Patent #:
8609485
Issue Dt:
12/17/2013
Application #:
12941185
Filing Dt:
11/08/2010
Publication #:
US20110241124
Pub Dt:
10/06/2011
Title:
METHODS OF FORMING EFUSE DEVICES
57
Patent #:
8564089
Issue Dt:
10/22/2013
Application #:
12941595
Filing Dt:
11/08/2010
Publication #:
US20110241086
Pub Dt:
10/06/2011
Title:
ELECTRONIC FUSE STRUCTURE FORMED USING A METAL GATE ELECTRODE MATERIAL STACK CONFIGURATION
58
Patent #:
8618554
Issue Dt:
12/31/2013
Application #:
12941771
Filing Dt:
11/08/2010
Publication #:
US20120112207
Pub Dt:
05/10/2012
Title:
METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE
59
Patent #:
NONE
Issue Dt:
Application #:
12942116
Filing Dt:
11/09/2010
Publication #:
US20120115326
Pub Dt:
05/10/2012
Title:
Method of Forming Metal Silicide Regions
60
Patent #:
9034744
Issue Dt:
05/19/2015
Application #:
12942200
Filing Dt:
11/09/2010
Publication #:
US20110244670
Pub Dt:
10/06/2011
Title:
Replacement Gate Approach for High-K Metal Gate Stacks by Avoiding a Polishing Process for Exposing the Placeholder Material
61
Patent #:
8361859
Issue Dt:
01/29/2013
Application #:
12942289
Filing Dt:
11/09/2010
Publication #:
US20120112208
Pub Dt:
05/10/2012
Title:
STRESSED TRANSISTOR WITH IMPROVED METASTABILITY
62
Patent #:
8541769
Issue Dt:
09/24/2013
Application #:
12942490
Filing Dt:
11/09/2010
Publication #:
US20120112164
Pub Dt:
05/10/2012
Title:
FORMATION OF A GRAPHENE LAYER ON A LARGE SUBSTRATE
63
Patent #:
8497554
Issue Dt:
07/30/2013
Application #:
12942506
Filing Dt:
11/09/2010
Publication #:
US20110241117
Pub Dt:
10/06/2011
Title:
SEMICONDUCTOR DEVICE COMPRISING METAL GATE STRUCTURES FORMED BY A REPLACEMENT GATE APPROACH AND EFUSES INCLUDING A SILICIDE
64
Patent #:
8542030
Issue Dt:
09/24/2013
Application #:
12942662
Filing Dt:
11/09/2010
Publication #:
US20120112776
Pub Dt:
05/10/2012
Title:
THREE-DIMENSIONAL (3D) STACKED INTEGRATED CIRCUIT TESTING
65
Patent #:
NONE
Issue Dt:
Application #:
12942664
Filing Dt:
11/09/2010
Publication #:
US20110241167
Pub Dt:
10/06/2011
Title:
Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime
66
Patent #:
8114747
Issue Dt:
02/14/2012
Application #:
12943146
Filing Dt:
11/10/2010
Publication #:
US20110059583
Pub Dt:
03/10/2011
Title:
METHOD FOR CREATING 3-D SINGLE GATE INVERTER
67
Patent #:
8652933
Issue Dt:
02/18/2014
Application #:
12943973
Filing Dt:
11/11/2010
Publication #:
US20120122303
Pub Dt:
05/17/2012
Title:
SEMICONDUCTOR STRUCTURE HAVING WIDE AND NARROW DEEP TRENCHES WITH DIFFERENT MATERIALS
68
Patent #:
8637941
Issue Dt:
01/28/2014
Application #:
12943995
Filing Dt:
11/11/2010
Publication #:
US20120119307
Pub Dt:
05/17/2012
Title:
SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER
69
Patent #:
8516409
Issue Dt:
08/20/2013
Application #:
12944020
Filing Dt:
11/11/2010
Publication #:
US20120124532
Pub Dt:
05/17/2012
Title:
IMPLEMENTING VERTICAL DIE STACKING TO DISTRIBUTE LOGICAL FUNCTION OVER MULTIPLE DIES IN THROUGH-SILICON-VIA STACKED SEMICONDUCTOR DEVICE
70
Patent #:
8689158
Issue Dt:
04/01/2014
Application #:
12944059
Filing Dt:
11/11/2010
Publication #:
US20120124534
Pub Dt:
05/17/2012
Title:
SYSTEM AND METHOD FOR PERFORMING STATIC TIMING ANALYSIS IN THE PRESENCE OF CORRELATIONS BETWEEN ASSERTED ARRIVAL TIMES
71
Patent #:
8564262
Issue Dt:
10/22/2013
Application #:
12944392
Filing Dt:
11/11/2010
Publication #:
US20120119717
Pub Dt:
05/17/2012
Title:
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72
Patent #:
8239810
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08/07/2012
Application #:
12944480
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11/11/2010
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US20120124542
Pub Dt:
05/17/2012
Title:
METHOD AND SYSTEM FOR OPTIMIZING A DEVICE WITH CURRENT SOURCE MODELS
73
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8250509
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08/21/2012
Application #:
12944493
Filing Dt:
11/11/2010
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US20120124537
Pub Dt:
05/17/2012
Title:
SLACK-BASED TIMING BUDGET APPORTIONMENT
74
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8527704
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09/03/2013
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12944682
Filing Dt:
11/11/2010
Publication #:
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Pub Dt:
05/17/2012
Title:
METHOD AND APPARATUS FOR OPTIMAL CACHE SIZING AND CONFIGURATION FOR LARGE MEMORY SYSTEMS
75
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8463571
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06/11/2013
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12944892
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11/12/2010
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US20120123725
Pub Dt:
05/17/2012
Title:
PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES
76
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NONE
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12946232
Filing Dt:
11/15/2010
Publication #:
US20120122031
Pub Dt:
05/17/2012
Title:
PHOTORESIST COMPOSITION FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF
77
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8402403
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03/19/2013
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12946325
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11/15/2010
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Pub Dt:
06/23/2011
Title:
VERIFYING A REGISTER-TRANSFER LEVEL DESIGN OF AN EXECUTION UNIT
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8040140
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10/18/2011
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12946386
Filing Dt:
11/15/2010
Publication #:
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Pub Dt:
03/10/2011
Title:
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8610451
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12/17/2013
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12946875
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11/16/2010
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Pub Dt:
05/17/2012
Title:
POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES
80
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8554390
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10/08/2013
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12946925
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11/16/2010
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US20120123607
Pub Dt:
05/17/2012
Title:
FREE COOLING SOLUTION FOR A CONTAINERIZED DATA CENTER
81
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8560980
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10/15/2013
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12946950
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11/16/2010
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US20120124535
Pub Dt:
05/17/2012
Title:
OPTIMAL CHIP ACCEPTANCE CRITERION AND ITS APPLICATIONS
82
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8667441
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03/04/2014
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12947445
Filing Dt:
11/16/2010
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Pub Dt:
05/17/2012
Title:
Clock Optimization with Local Clock Buffer Control Optimization
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12947460
Filing Dt:
11/16/2010
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Pub Dt:
05/17/2012
Title:
SEMICONDUCTOR DEVICE SUBSTRATE WITH EMBEDDED STRESS REGION, AND RELATED FABRICATION METHODS
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12948031
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11/17/2010
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Pub Dt:
05/17/2012
Title:
Replacement Gate Having Work Function at Valence Band Edge
85
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8138099
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03/20/2012
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12948079
Filing Dt:
11/17/2010
Title:
CHIP PACKAGE SOLDER INTERCONNECT FORMED BY SURFACE TENSION
86
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8296707
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10/23/2012
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12948165
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11/17/2010
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Pub Dt:
05/17/2012
Title:
IMPLEMENTING SPARE LATCH PLACEMENT QUALITY DETERMINATION
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8084311
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12/27/2011
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12948246
Filing Dt:
11/17/2010
Title:
METHOD OF FORMING REPLACEMENT METAL GATE WITH BORDERLESS CONTACT AND STRUCTURE THEREOF
88
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8580646
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12948805
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11/18/2010
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05/24/2012
Title:
METHOD OF FABRICATING FIELD EFFECT TRANSISTORS WITH LOW K SIDEWALL SPACERS
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8236662
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08/07/2012
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12949108
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11/18/2010
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03/17/2011
Title:
BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION
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8466056
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06/18/2013
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11/18/2010
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05/19/2011
Title:
Method of Forming Metal Interconnect Structures in Ultra Low-K Dielectrics
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12/04/2012
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12949328
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11/18/2010
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05/24/2012
Title:
PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION
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8762919
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12949998
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Title:
CIRCUIT MACRO PLACEMENT USING MACRO ASPECT RATIO BASED ON PORTS
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8562210
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05/24/2012
Title:
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12950635
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05/24/2012
Title:
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12951107
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METHOD OF FORMING E-FUSE IN REPLACEMENT METAL GATE MANUFACTURING PROCESS
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12951516
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05/24/2012
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HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE
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8633067
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12951597
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11/22/2010
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FABRICATING PHOTONICS DEVICES FULLY INTEGRATED INTO A CMOS MANUFACTURING PROCESS
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Method of Manufacturing a Photovoltaic Cell
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12953511
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11/24/2010
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05/24/2012
Title:
DETERMINING LITHOGRAPHIC SET POINT USING OPTICAL PROXIMITY CORRECTION VERIFICATION SIMULATION
100
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NONE
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12953654
Filing Dt:
11/24/2010
Publication #:
US20110068462
Pub Dt:
03/24/2011
Title:
SEMICONDUCTOR CHIP PACKAGES HAVING REDUCED STRESS
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
440 STONE BREAK ROAD EXTENSION
MALTA, NEW YORK 12020
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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