Total properties:
483
Page
1
of
5
Pages:
1 2 3 4 5
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
09681986
|
Filing Dt:
|
07/03/2001
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
Title:
|
METHOD OF AVOIDING DIELECTRIC LAYER DETERIOATION WITH A LOW DIELECTRIC CONSTANT DURING A STRIPPING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
09681987
|
Filing Dt:
|
07/03/2001
|
Publication #:
|
|
Pub Dt:
|
01/09/2003
| | | | |
Title:
|
METHOD OF AVOIDING DIELECTRIC LAYER DETERIOATION WITH A LOW DIELECTRIC CONSTANT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
09682303
|
Filing Dt:
|
08/16/2001
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
Title:
|
DELAY LOCK CIRCUIT USING BISECTION ALGORITHM AND RELATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09682479
|
Filing Dt:
|
09/07/2001
|
Title:
|
METHOD OF REPAIRING A LOW DIELECTRIC CONSTANT MATERIAL LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09682946
|
Filing Dt:
|
11/02/2001
|
Title:
|
STRUCTURE OF A TEST KEY FOR MONITORING SALICIDE RESIDUE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
09910876
|
Filing Dt:
|
07/24/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
DUAL DAMASCENE PROCESS USING METAL HARD MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10063307
|
Filing Dt:
|
04/10/2002
|
Publication #:
|
|
Pub Dt:
|
10/16/2003
| | | | |
Title:
|
COMPOSITE PHOTORESIST FOR PATTERN TRANSFERRING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10064051
|
Filing Dt:
|
06/05/2002
|
Publication #:
|
|
Pub Dt:
|
12/11/2003
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTOR AND FABRICATING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10064052
|
Filing Dt:
|
06/05/2002
|
Publication #:
|
|
Pub Dt:
|
12/11/2003
| | | | |
Title:
|
METHOD OF FORMING A FUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
10064110
|
Filing Dt:
|
06/12/2002
|
Title:
|
MULTI-DIE PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
10092998
|
Filing Dt:
|
03/06/2002
|
Publication #:
|
|
Pub Dt:
|
09/11/2003
| | | | |
Title:
|
METHOD FOR FORMING THE SELF-ALIGNED BURIED N+ TYPE TO DIFFUSION PROCESS IN ETOX FLASH CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
10165739
|
Filing Dt:
|
06/07/2002
|
Publication #:
|
|
Pub Dt:
|
12/11/2003
| | | | |
Title:
|
METHOD FOR IMPROVING ADHESION OF A LOW K DIELECTRIC TO A BARRIER LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10248833
|
Filing Dt:
|
02/24/2003
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
Title:
|
CAPACITOR IN AN INTERCONNECT SYSTEM AND METHOD OF MANUFACTURING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10249374
|
Filing Dt:
|
04/03/2003
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
Title:
|
MANUFACTURING METHOD OF AN INTEGRATED CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10428508
|
Filing Dt:
|
05/01/2003
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
Title:
|
METHOD FOR REMOVING PHOTORESIST
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10449262
|
Filing Dt:
|
05/29/2003
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
INTERCONNECTION STRUCTURE AND FABRICATION METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10609478
|
Filing Dt:
|
07/01/2003
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
Title:
|
SEMICONDUCTOR MEMORY APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
10659258
|
Filing Dt:
|
09/11/2003
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
PLASMA APPARATUS AND METHOD CAPABLE OF ADAPTIVE IMPEDANCE MATCHING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10685496
|
Filing Dt:
|
10/16/2003
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
NON-VOLATILE MEMORY TECHNOLOGY SUITABLE FOR FLASH AND BYTE OPERATION APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10705500
|
Filing Dt:
|
11/12/2003
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
METHOD FOR PREVENTING TO FORM A SPACER UNDERCUT IN SEG PRE-CLEAN PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10707517
|
Filing Dt:
|
12/19/2003
|
Title:
|
METHOD OF FABRICATING A DUAL DAMASCENE COPPER WIRE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10708108
|
Filing Dt:
|
02/10/2004
|
Title:
|
MIXED-MODE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10708694
|
Filing Dt:
|
03/18/2004
|
Title:
|
TRIPLE GATE DEVICE HAVING STRAINED-SILICON CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10708983
|
Filing Dt:
|
04/05/2004
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
Title:
|
METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10709568
|
Filing Dt:
|
05/14/2004
|
Publication #:
|
|
Pub Dt:
|
11/18/2004
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTOR AND FABRICATING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10709569
|
Filing Dt:
|
05/14/2004
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTOR AND FABRICATING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10709854
|
Filing Dt:
|
06/02/2004
|
Title:
|
NON-VOLATILE MEMORY WITH INDUCED BIT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10711790
|
Filing Dt:
|
10/05/2004
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
Title:
|
FUSE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
10718896
|
Filing Dt:
|
11/20/2003
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY CELL AND METHOD FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2005
|
Application #:
|
10788183
|
Filing Dt:
|
02/25/2004
|
Title:
|
METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2007
|
Application #:
|
10810435
|
Filing Dt:
|
03/25/2004
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
METHOD OF FABRICATING INDUCTOR AND STRUCTURE FORMED THEREFROM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10820601
|
Filing Dt:
|
04/07/2004
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
10839524
|
Filing Dt:
|
05/04/2004
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
Title:
|
IMAGE SENSOR DEVICE AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10841562
|
Filing Dt:
|
05/10/2004
|
Publication #:
|
|
Pub Dt:
|
12/16/2004
| | | | |
Title:
|
BARRIER LAYER STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10893632
|
Filing Dt:
|
07/15/2004
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
Title:
|
INTERCONNECTION STRUCTURE AND FABRICATION METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
10904081
|
Filing Dt:
|
10/22/2004
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
FUSE-STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10904620
|
Filing Dt:
|
11/18/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD OF MANUFACTURING A MOS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10905185
|
Filing Dt:
|
12/21/2004
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
METHOD OF REMOVING SPACERS AND FABRICATING MOS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10906583
|
Filing Dt:
|
02/25/2005
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
SYSTEM-ON-CHIP WITH SHIELD RINGS FOR SHIELDING FUNCTIONAL BLOCKS THEREIN FROM ELECTROMAGNETIC INTERFERENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
10907125
|
Filing Dt:
|
03/22/2005
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
SEMICONDUCTOR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10907448
|
Filing Dt:
|
04/01/2005
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
MIM CAPACITOR STRUCTURE AND FABRICATING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10907710
|
Filing Dt:
|
04/13/2005
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
SALICIDE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10907924
|
Filing Dt:
|
04/21/2005
|
Title:
|
METHOD FOR FABRICATING TRENCH ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10908815
|
Filing Dt:
|
05/27/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
METHOD OF REDUCING CHARGING DAMAGE TO INTEGRATED CIRCUITS DURING SEMICONDUCTOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
10908828
|
Filing Dt:
|
05/27/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
DEFECT DETECTION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
10980075
|
Filing Dt:
|
11/02/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY CELL AND MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10996204
|
Filing Dt:
|
11/22/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
11003515
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
IMAGE SENSOR DEVICE WITH COLOR FILTERS AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11014395
|
Filing Dt:
|
12/15/2004
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
METHOD FOR REMOVING PHOTORESIST
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
11078543
|
Filing Dt:
|
03/11/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2009
|
Application #:
|
11099058
|
Filing Dt:
|
04/05/2005
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
Title:
|
IMAGE SENSOR DEVICE AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11122655
|
Filing Dt:
|
05/04/2005
|
Publication #:
|
|
Pub Dt:
|
09/15/2005
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY CELL AND METHOD FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11155729
|
Filing Dt:
|
06/16/2005
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
Title:
|
PROCESS OF METAL INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11160101
|
Filing Dt:
|
06/09/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
METHOD FOR TRIMMING PROGRAMMABLE RESISTOR TO PREDETERMINED RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11160107
|
Filing Dt:
|
06/09/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
11160630
|
Filing Dt:
|
07/01/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
METHOD OF REDUCING CHARGING DAMAGE TO INTEGRATED CIRCUITS DURING SEMICONDUCTOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2009
|
Application #:
|
11161170
|
Filing Dt:
|
07/26/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
SEMICONDUCTOR CMOS TRANSISTORS AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
11161302
|
Filing Dt:
|
07/29/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
DIGITAL-TO-ANALOG CONVERTER AND RELATED LEVEL SHIFTER THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11161760
|
Filing Dt:
|
08/16/2005
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
Title:
|
TRENCH CAPACITOR OF A DRAM AND FABRICATING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11162117
|
Filing Dt:
|
08/29/2005
|
Publication #:
|
|
Pub Dt:
|
04/26/2007
| | | | |
Title:
|
STACKED ALIGNMENT MARK AND METHOD FOR MANUFACTURING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
11162118
|
Filing Dt:
|
08/29/2005
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
Title:
|
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11162693
|
Filing Dt:
|
09/20/2005
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
METAL OXIDE SEMICONDUCTOR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11162863
|
Filing Dt:
|
09/27/2005
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11163124
|
Filing Dt:
|
10/05/2005
|
Publication #:
|
|
Pub Dt:
|
04/05/2007
| | | | |
Title:
|
METAL OXIDE SEMICONDUCTOR TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
11163149
|
Filing Dt:
|
10/06/2005
|
Publication #:
|
|
Pub Dt:
|
04/12/2007
| | | | |
Title:
|
METHOD OF FABRICATING OPENINGS AND CONTACT HOLES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
11163437
|
Filing Dt:
|
10/19/2005
|
Title:
|
CIRCUIT TO CHARACTERIZE MATCHING OF ENERGY-STORAGE COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11164127
|
Filing Dt:
|
11/10/2005
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
Title:
|
RETICLE AND OPTICAL PROXIMITY CORRECTION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
11164204
|
Filing Dt:
|
11/14/2005
|
Publication #:
|
|
Pub Dt:
|
05/17/2007
| | | | |
Title:
|
CHEMICAL MECHANICAL POLISHING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11164405
|
Filing Dt:
|
11/22/2005
|
Publication #:
|
|
Pub Dt:
|
05/24/2007
| | | | |
Title:
|
LOW-VOLTAGE DIFFERENTIAL SIGNAL DRIVER WITH PRE-EMPHASIS CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11164481
|
Filing Dt:
|
11/24/2005
|
Publication #:
|
|
Pub Dt:
|
05/24/2007
| | | | |
Title:
|
METHOD OF FORMING A CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11164949
|
Filing Dt:
|
12/12/2005
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
METHOD FOR FORMING HIGH VOLTAGE DEVICE AND SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11218456
|
Filing Dt:
|
09/02/2005
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
Title:
|
INTERCONNECTION STRUCTURE USED IN A PAD REGION OF A SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11277149
|
Filing Dt:
|
03/22/2006
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
Title:
|
SEMICONDUCTOR WAFER AND METHOD FOR MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11278434
|
Filing Dt:
|
04/03/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
METHOD OF FORMING A MOS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11278550
|
Filing Dt:
|
04/04/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
INDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11278952
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
METHOD FOR FABRICATING A TRANSFORMER INTEGRATED WITH A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11279254
|
Filing Dt:
|
04/11/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11307660
|
Filing Dt:
|
02/16/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
SEMICONDUCTOR MOS TRANSISTOR DEVICE AND METHOD FOR MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11308162
|
Filing Dt:
|
03/09/2006
|
Publication #:
|
|
Pub Dt:
|
09/13/2007
| | | | |
Title:
|
CAPACITOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11308560
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
FABRICATING METHOD OF SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11308643
|
Filing Dt:
|
04/17/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
METHOD FOR FORMING STRAINED SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SOURCE/DRAIN REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
11309164
|
Filing Dt:
|
07/04/2006
|
Publication #:
|
|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
METHOD FOR REDUCING CAPACITANCE VARIATION BETWEEN CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
11358972
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
CAPACITANCE DIELECTRIC LAYER AND CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11379057
|
Filing Dt:
|
04/18/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
IMAGE SENSOR DEVICE AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
11379226
|
Filing Dt:
|
04/19/2006
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
SPACER STRUCTURE WHEREIN CARBON-CONTAINING OXYNITRIDE FILM FORMED WITHIN
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11379380
|
Filing Dt:
|
04/20/2006
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
METHOD OF REDUCING CHARGING DAMAGE TO INTEGRATED CIRCUITS DURING SEMICONDUCTOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11399827
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11400077
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE AND FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11420222
|
Filing Dt:
|
05/25/2006
|
Publication #:
|
|
Pub Dt:
|
11/29/2007
| | | | |
Title:
|
TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11460631
|
Filing Dt:
|
07/28/2006
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
Title:
|
METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11462802
|
Filing Dt:
|
08/07/2006
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
FREQUENCY GENERATOR APPARATUS AND CONTROL CIRCUIT THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11465811
|
Filing Dt:
|
08/20/2006
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11532100
|
Filing Dt:
|
09/15/2006
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
FABRICATING METHOD FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11553477
|
Filing Dt:
|
10/27/2006
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
SALICIDE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
11560831
|
Filing Dt:
|
11/16/2006
|
Publication #:
|
|
Pub Dt:
|
04/26/2007
| | | | |
Title:
|
METHOD OF REDUCING CHARGING DAMAGE TO INTEGRATED CIRCUITS DURING SEMICONDUCTOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11562918
|
Filing Dt:
|
11/22/2006
|
Publication #:
|
|
Pub Dt:
|
04/19/2007
| | | | |
Title:
|
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY CELL AND MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2009
|
Application #:
|
11566688
|
Filing Dt:
|
12/05/2006
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11608249
|
Filing Dt:
|
12/08/2006
|
Publication #:
|
|
Pub Dt:
|
04/19/2007
| | | | |
Title:
|
SYSTEM-ON-CHIP WITH SHIELD RINGS FOR SHIELDING FUNCTIONAL BLOCKS THEREIN FROM ELECTROMAGNETIC INTERFERENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
11608927
|
Filing Dt:
|
12/11/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11620057
|
Filing Dt:
|
01/05/2007
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
Title:
|
METHOD OF FORMING INTERCONNECT HAVING STACKED ALIGNMENT MARK
|
|