Total properties:
30
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
09667122
|
Filing Dt:
|
09/21/2000
|
Title:
|
PROCESSING SYSTEM HAVING SEQUENTIAL ADDRESS INDICATOR SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
09798390
|
Filing Dt:
|
03/05/2001
|
Publication #:
|
|
Pub Dt:
|
09/05/2002
| | | | |
Title:
|
DATA PROCESSING SYSTEM HAVING REDIRECTING CIRCUITRY AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10608719
|
Filing Dt:
|
06/26/2003
|
Publication #:
|
|
Pub Dt:
|
01/29/2004
| | | | |
Title:
|
SYNCHRONOUS SRAM-COMPATIBLE MEMORY AND METHOD OF DRIVING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
11363251
|
Filing Dt:
|
02/28/2006
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
LOW POWER MEMORY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2009
|
Application #:
|
11381284
|
Filing Dt:
|
05/02/2006
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
Title:
|
INSTRUCTION FOR CONDITIONALLY YIELDING TO A READY THREAD BASED ON PRIORITY CRITERIA
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
11477659
|
Filing Dt:
|
06/30/2006
|
Publication #:
|
|
Pub Dt:
|
01/03/2008
| | | | |
Title:
|
SYNCHRONOUS MEMORY READ DATA CAPTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2009
|
Application #:
|
11565170
|
Filing Dt:
|
11/30/2006
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
FLASH MEMORY PROGRAM INHIBIT SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
11613325
|
Filing Dt:
|
12/20/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11703634
|
Filing Dt:
|
02/08/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
SIMPLIFIED BIAS CIRCUITRY FOR DIFFERENTIAL BUFFER STAGE WITH SYMMETRIC LOADS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2009
|
Application #:
|
11762330
|
Filing Dt:
|
06/13/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
12067590
|
Filing Dt:
|
03/20/2008
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
CONTROLLER AND METHOD FOR CONTROLLING AN IGNITION COIL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
12371088
|
Filing Dt:
|
02/13/2009
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
FLASH MEMORY PROGRAM INHIBIT SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12389153
|
Filing Dt:
|
02/19/2009
|
Publication #:
|
|
Pub Dt:
|
08/19/2010
| | | | |
Title:
|
ADDRESS TRANSLATION TRACE MESSAGE GENERATION FOR DEBUG
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2011
|
Application #:
|
12389156
|
Filing Dt:
|
02/19/2009
|
Publication #:
|
|
Pub Dt:
|
08/19/2010
| | | | |
Title:
|
PROGRAM CORRELATION MESSAGE GENERATION FOR DEBUG
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12463759
|
Filing Dt:
|
05/11/2009
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12470877
|
Filing Dt:
|
05/22/2009
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
LOW POWER MEMORY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
12472012
|
Filing Dt:
|
05/26/2009
|
Publication #:
|
|
Pub Dt:
|
11/12/2009
| | | | |
Title:
|
HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12719413
|
Filing Dt:
|
03/08/2010
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
FLASH MEMORY PROGRAM INHIBIT SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12827718
|
Filing Dt:
|
06/30/2010
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12884939
|
Filing Dt:
|
09/17/2010
|
Publication #:
|
|
Pub Dt:
|
01/13/2011
| | | | |
Title:
|
FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13040254
|
Filing Dt:
|
03/03/2011
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13208732
|
Filing Dt:
|
08/12/2011
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
FLASH MEMORY PROGRAM INHIBIT SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
13328762
|
Filing Dt:
|
12/16/2011
|
Publication #:
|
|
Pub Dt:
|
04/12/2012
| | | | |
Title:
|
FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13655582
|
Filing Dt:
|
10/19/2012
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2015
|
Application #:
|
13829436
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
Lithography-friendly Local Read Circuit for NAND Flash Memory Devices and Manufacturing Method Thereof
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13892743
|
Filing Dt:
|
05/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/19/2013
| | | | |
Title:
|
FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2018
|
Application #:
|
14141686
|
Filing Dt:
|
12/27/2013
|
Title:
|
SYNCHRONOUS MEMORY READ DATA CAPTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
14208812
|
Filing Dt:
|
03/13/2014
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2016
|
Application #:
|
14699831
|
Filing Dt:
|
04/29/2015
|
Publication #:
|
|
Pub Dt:
|
10/22/2015
| | | | |
Title:
|
Lithography-friendly Local Read Circuit for NAND Flash Memory Devices and Manufacturing Method Thereof
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2017
|
Application #:
|
15054873
|
Filing Dt:
|
02/26/2016
|
Publication #:
|
|
Pub Dt:
|
11/03/2016
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION
|
|