skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:058002/0470   Pages: 437
Recorded: 11/03/2020
Attorney Dkt #:127110/12
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST.
Total properties: 4704
Page 4 of 48
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
1
Patent #:
6066963
Issue Dt:
05/23/2000
Application #:
08939196
Filing Dt:
09/29/1997
Title:
MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
2
Patent #:
6033991
Issue Dt:
03/07/2000
Application #:
08939838
Filing Dt:
09/29/1997
Title:
ISOLATION SCHEME BASED ON RECESSED LOCOS USING A SLOPED SI ETCH AND DRY FIELD OXIDATION
3
Patent #:
5966027
Issue Dt:
10/12/1999
Application #:
08940437
Filing Dt:
09/30/1997
Title:
SYMMETRIC LOGIC BLOCK INPUT/OUTPUT SCHEME
4
Patent #:
5912489
Issue Dt:
06/15/1999
Application #:
08940674
Filing Dt:
09/30/1997
Title:
A DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
5
Patent #:
6545505
Issue Dt:
04/08/2003
Application #:
08940682
Filing Dt:
09/30/1997
Title:
HYBRID ROUTING ARCHITECTURE FOR HIGH DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES
6
Patent #:
5852576
Issue Dt:
12/22/1998
Application #:
08944904
Filing Dt:
10/06/1997
Title:
HIGH VOLTAGE NMOS PASS GATE FOR INTEGRATED CIRCUIT WITH HIGH VOLTAGE GENERATOR AND FLASH NON-VOLATILE MEMORY DEVICE HAVING THE PASS GATE
7
Patent #:
6201407
Issue Dt:
03/13/2001
Application #:
08946030
Filing Dt:
10/07/1997
Title:
CIRCULAR PRODUCT TERM ALLOATIONS SCHEME FOR A PROGRAMMABLE DEVICE
8
Patent #:
5889697
Issue Dt:
03/30/1999
Application #:
08947123
Filing Dt:
10/08/1997
Title:
MEMORY CELL FOR STORING AT LEAST THREE LOGIC STATES
9
Patent #:
6049242
Issue Dt:
04/11/2000
Application #:
08949861
Filing Dt:
10/14/1997
Title:
VOLTAGE REFERENCE SOURCE FOR AN OVERVOLTAGE-TOLERANT BUS INTERFACE
10
Patent #:
5914844
Issue Dt:
06/22/1999
Application #:
08949863
Filing Dt:
10/14/1997
Title:
OVERVOLTAGE-TOLERANT INPUT OUTPUT BUFFERS HAVING A SWITCH CONFIGURED T TO ISOLATE A PUL-UP TRANSISTOR FROM A VOLTAGE SUPPLY
11
Patent #:
5888870
Issue Dt:
03/30/1999
Application #:
08955794
Filing Dt:
10/22/1997
Title:
MEMORY CELL FABRICATION EMPLOYING AN INTERPOLY GATE DIELECTRIC ARRANGED UPON A POLISHED FLOATING GATE
12
Patent #:
6097222
Issue Dt:
08/01/2000
Application #:
08958464
Filing Dt:
10/27/1997
Title:
SYMMETRICAL NOR GATES
13
Patent #:
6147908
Issue Dt:
11/14/2000
Application #:
08962860
Filing Dt:
11/03/1997
Title:
STABLE ADJUSTABLE PROGRAMMING VOLTAGE SCHEME
14
Patent #:
5968178
Issue Dt:
10/19/1999
Application #:
08963843
Filing Dt:
11/04/1997
Title:
CIRCUIT AND METHOD FOR RESETTING A MICROCONTROLLER
15
Patent #:
6114890
Issue Dt:
09/05/2000
Application #:
08967658
Filing Dt:
11/10/1997
Title:
SKEW-REDUCTION CIRCUIT
16
Patent #:
6140228
Issue Dt:
10/31/2000
Application #:
08970107
Filing Dt:
11/13/1997
Title:
LOW TEMPERATURE METALLIZATION PROCESS
17
Patent #:
5995406
Issue Dt:
11/30/1999
Application #:
08970448
Filing Dt:
11/14/1997
Title:
PLATE LINE SEGMENTATION IN A 1T/1C FERROELECTRIC MEMORY
18
Patent #:
5956266
Issue Dt:
09/21/1999
Application #:
08970452
Filing Dt:
11/14/1997
Title:
REFERENCE CELL FOR A 1T/1C FERROELECTRIC MEMORY
19
Patent #:
5880989
Issue Dt:
03/09/1999
Application #:
08970453
Filing Dt:
11/14/1997
Title:
SENSING METHODOLOGY FOR A 1T/1C FERROELECTRIC MEMORY
20
Patent #:
5892728
Issue Dt:
04/06/1999
Application #:
08970454
Filing Dt:
11/14/1997
Title:
COLUMN DECODER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
21
Patent #:
5986919
Issue Dt:
11/16/1999
Application #:
08970518
Filing Dt:
11/14/1997
Title:
REFERENCE CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
22
Patent #:
5969980
Issue Dt:
10/19/1999
Application #:
08970519
Filing Dt:
11/14/1997
Title:
SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
23
Patent #:
6028783
Issue Dt:
02/22/2000
Application #:
08970520
Filing Dt:
11/14/1997
Title:
MEMORY CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
24
Patent #:
5978251
Issue Dt:
11/02/1999
Application #:
08970522
Filing Dt:
11/14/1997
Title:
PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
25
Patent #:
6157582
Issue Dt:
12/05/2000
Application #:
08971627
Filing Dt:
11/17/1997
Title:
DYNAMIC PULL-UP SUPPRESSOR FOR COLUMN REDUNDANCY WRITE SCHEMES WITH REDUNDANT DATA LINES
26
Patent #:
6040792
Issue Dt:
03/21/2000
Application #:
08974736
Filing Dt:
11/19/1997
Title:
UNIVERSAL SERIAL BUS TO PARALLEL BUS SIGNAL CONVERTER AND METHOD OF CONVERSION
27
Patent #:
6823435
Issue Dt:
11/23/2004
Application #:
08974971
Filing Dt:
11/20/1997
Title:
NON-VOLATILE MEMORY SYSTEM HAVING A PROGRAMMABLY SELECTABLE BOOT CODE SECTION SIZE
28
Patent #:
6020238
Issue Dt:
02/01/2000
Application #:
08978107
Filing Dt:
11/25/1997
Title:
METHOD OF FABRICATING A HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY
29
Patent #:
6025228
Issue Dt:
02/15/2000
Application #:
08978398
Filing Dt:
11/25/1997
Title:
METHOD OF FABRICATING AN OXYNITRIDE-CAPPED HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY.
30
Patent #:
6017786
Issue Dt:
01/25/2000
Application #:
08982186
Filing Dt:
12/17/1997
Title:
METHOD FOR FORMING A LOW BARRIER HEIGHT OXIDE LAYER ON A SILICON SUBSTRATE
31
Patent #:
6061817
Issue Dt:
05/09/2000
Application #:
08982730
Filing Dt:
12/02/1997
Title:
METHOD AND APPARATUS FOR GENERATING TEST PATTERN FOR SECQUENCE DETECTION
32
Patent #:
6111800
Issue Dt:
08/29/2000
Application #:
08985890
Filing Dt:
12/05/1997
Title:
PARALLEL TEST FOR ASYNCHRONOUS MEMORY
33
Patent #:
5981341
Issue Dt:
11/09/1999
Application #:
08986160
Filing Dt:
12/05/1997
Title:
SIDEWALL SPACER FOR PROTECTING TUNNEL OXIDE DURING ISOLATION TRENCH FORMATION IN SELF-ALIGNED FLASH MEMORY CORE
34
Patent #:
5976900
Issue Dt:
11/02/1999
Application #:
08986371
Filing Dt:
12/08/1997
Title:
METHOD OF REDUCING IMPURITY CONTAMINATION IN SEMICONDUCTOR PROCESS CHAMBERS
35
Patent #:
6054879
Issue Dt:
04/25/2000
Application #:
08986440
Filing Dt:
12/08/1997
Title:
CURRENTSENSING AMPLIFIER WITH FEEDBACK
36
Patent #:
6001688
Issue Dt:
12/14/1999
Application #:
08986860
Filing Dt:
12/08/1997
Title:
METHOD OF ELIMINATING POLY STRINGER IN A MEMORY DEVICE
37
Patent #:
6046085
Issue Dt:
04/04/2000
Application #:
08986951
Filing Dt:
12/08/1997
Title:
ELIMINATION OF POLY STRINGERS WITH STRAIGHT POLY PROFILE
38
Patent #:
5933729
Issue Dt:
08/03/1999
Application #:
08986953
Filing Dt:
12/08/1997
Title:
REDUCTION OF ONO FENCE DURING SELF-ALIGNED ETCH TO ELIMINATE POLY STRINGERS
39
Patent #:
6097618
Issue Dt:
08/01/2000
Application #:
08988942
Filing Dt:
12/11/1997
Title:
APPARATUS AND METHOD FOR CORRECTING DATA IN A NON- VOLATILE RANDOM ACCESS MEMORY
40
Patent #:
6008629
Issue Dt:
12/28/1999
Application #:
08989517
Filing Dt:
12/12/1997
Title:
A CHARGING AND DISCHARGING DEVICE FOR AN ELECTRONIC APPARATUS, AND AN ELECTRONIC APPARATUS INCLUDING THE SAME, UTILIZING A CHARGING DEVICE PROVIDING A CONSTANT CHARGING CURRENT
41
Patent #:
6107859
Issue Dt:
08/22/2000
Application #:
08989707
Filing Dt:
12/12/1997
Title:
LOW POWER BUFFER CIRCUIT AND METHOD FOR GENERATING A COMMON-MODE OUTPUT ABSENT PROCESS-INDUCED MISMATCH ERROR
42
Patent #:
6002160
Issue Dt:
12/14/1999
Application #:
08989820
Filing Dt:
12/12/1997
Title:
SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
43
Patent #:
5940345
Issue Dt:
08/17/1999
Application #:
08990126
Filing Dt:
12/12/1997
Title:
COMBINATIONAL LOGIC FEEDBACK CIRCUIT TO ENSURE CORRECT POWER-ON-RESET OF A FOUR-BIT SYNCHRONOUS SHIFT REGISTER
44
Patent #:
5994780
Issue Dt:
11/30/1999
Application #:
08991052
Filing Dt:
12/16/1997
Title:
SEMICONDUCTOR DEVICE WITH MULTIPLE CONTACT SIZES
45
Patent #:
5963487
Issue Dt:
10/05/1999
Application #:
08991231
Filing Dt:
12/16/1997
Title:
WRITE ENABLING CIRCUITRY FOR A SEMICONDUCT0R MEMORY
46
Patent #:
6898101
Issue Dt:
05/24/2005
Application #:
08991232
Filing Dt:
12/16/1997
Title:
MICROCONTROLLER WITH PROGRAMMABLE LOGIC ON A SINGLE CHIP
47
Patent #:
6072191
Issue Dt:
06/06/2000
Application #:
08991299
Filing Dt:
12/16/1997
Title:
INTERLEVEL DIELECTRIC THICKNESS MONITOR FOR COMPLEX SEMICONDUCTOR CHIPS
48
Patent #:
5859796
Issue Dt:
01/12/1999
Application #:
08991466
Filing Dt:
12/16/1997
Title:
PROGRAMMING OF MEMORY CELLS USING CONNECTED FLOATING GATE ANALOG REFERENCE CELL
49
Patent #:
6127222
Issue Dt:
10/03/2000
Application #:
08991687
Filing Dt:
12/16/1997
Title:
NON-SELF-ALIGNED SIDE CHANNEL IMPLANTS FOR FLASH MEMORY CELLS
50
Patent #:
6366979
Issue Dt:
04/02/2002
Application #:
08991845
Filing Dt:
12/16/1997
Title:
APPARATUS AND METHOD FOR SHORTING RESTRANSMIT RECOVERY TIMES UTILIZING CACHE MEMORY IN HIGH SPEED FIFO
51
Patent #:
5907561
Issue Dt:
05/25/1999
Application #:
08992077
Filing Dt:
12/17/1997
Title:
METHOD TO IMPROVE TESTING SPEED OF MEMORY
52
Patent #:
6005821
Issue Dt:
12/21/1999
Application #:
08992199
Filing Dt:
12/17/1997
Title:
CIRCUIT AND METHOD FOR INSTRUCTION CONTROLLABLE SLEW RATE OF BIT LINE DRIVER
53
Patent #:
6027998
Issue Dt:
02/22/2000
Application #:
08992536
Filing Dt:
12/17/1997
Title:
METHOD FOR FULLY PLANARIZED CONDUCTIVE LINE FOR A STACK GATE
54
Patent #:
6387755
Issue Dt:
05/14/2002
Application #:
08992616
Filing Dt:
12/17/1997
Title:
METHOD AND SYSTEM FOR PROVIDING LOCALIZED GATE EDGE ROUNDING WITH MINIMAL ENCROACHMENT AND GATE EDGE LIFTING
55
Patent #:
6103602
Issue Dt:
08/15/2000
Application #:
08992618
Filing Dt:
12/17/1997
Title:
METHOD AND SYSTEM FOR PROVIDING A DRAIN SIDE POCKET IMPLANT
56
Patent #:
5949718
Issue Dt:
09/07/1999
Application #:
08992622
Filing Dt:
12/17/1997
Title:
METHOD AND SYSTEM FOR SELECTED SOURCE DURING READ AND PROGRAMMING OF FLASH MEMORY
57
Patent #:
6034394
Issue Dt:
03/07/2000
Application #:
08992950
Filing Dt:
12/18/1997
Title:
METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
58
Patent #:
5973353
Issue Dt:
10/26/1999
Application #:
08992951
Filing Dt:
12/18/1997
Title:
METHODS AND ARRANGEMENTS FOR FORMING A TAPERED FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
59
Patent #:
6258669
Issue Dt:
07/10/2001
Application #:
08992960
Filing Dt:
12/18/1997
Title:
METHODS AND ARRANGEMENTS FOR IMPROVED FORMATION OF CONTROL AND FLOATING GATES IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
60
Patent #:
6124608
Issue Dt:
09/26/2000
Application #:
08992961
Filing Dt:
12/18/1997
Title:
NON-VOLATILE TRENCH SEMICONDUCTOR DEVICE HAVING A SHALLOW DRAIN REGION
61
Patent #:
6054710
Issue Dt:
04/25/2000
Application #:
08993036
Filing Dt:
12/18/1997
Title:
METHOD AND APPARATUS FOR OBTAINING TWO-OR THREE-DEMENSIONAL INFORMATION FROM SCANNING ELECTRON MICROSCOPY
62
Patent #:
6185630
Issue Dt:
02/06/2001
Application #:
08993062
Filing Dt:
12/18/1997
Title:
DEVICE INITIALIZING SYSTEM WITH PROGRAMMABLE ARRAY LOGIC CONFIGURED TO CAUSE NON-VOLATILE MEMORY TO OUTPUT ADDRESS AND DATA INFORMATION TO THE DEVICE IN A PRESCRIBED SEQUENCE
63
Patent #:
6228746
Issue Dt:
05/08/2001
Application #:
08993149
Filing Dt:
12/18/1997
Title:
METHODOLOGY FOR ACHIEVING DUAL FIELD OXIDE THICKNESSES
64
Patent #:
5994239
Issue Dt:
11/30/1999
Application #:
08993343
Filing Dt:
12/18/1997
Title:
MANUFACTURING PROCESS TO ELIMINATE POLYSTRINGERS IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
65
Patent #:
6281078
Issue Dt:
08/28/2001
Application #:
08993344
Filing Dt:
12/18/1997
Title:
MANUFACTURING PROCESS TO ELIMINATE ONO FENCE MATERIAL IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
66
Patent #:
6667511
Issue Dt:
12/23/2003
Application #:
08993368
Filing Dt:
12/18/1997
Title:
NOVEL NAND TYPE CORE CELL STRUCTURE FOR A HIGH DENSITY FLASH MEMORY DEVICE HAVING A UNIQUE SELECT GATE TRANSISTOR CONFIGURATION
67
Patent #:
6063662
Issue Dt:
05/16/2000
Application #:
08993409
Filing Dt:
12/18/1997
Title:
METHODS FOR FORMING A CONTROL GATE APPARATUS IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
68
Patent #:
6114230
Issue Dt:
09/05/2000
Application #:
08993443
Filing Dt:
12/18/1997
Title:
NITROGEN ION IMPLANTED AMORPHOUS SILICON TO PRODUCE OXIDATION RESISTANT AND FINER GRAIN POLYSILICON BASED FLOATING GATES
69
Patent #:
6140246
Issue Dt:
10/31/2000
Application #:
08993444
Filing Dt:
12/18/1997
Title:
IN SITU P DOPED AMORPHOUS SILICON BY NH3 TO FORM OXIDATION RESISTANT AND FINER GRAIN FLOATING GATES.
70
Patent #:
5940709
Issue Dt:
08/17/1999
Application #:
08993599
Filing Dt:
12/18/1997
Title:
METHOD AND SYSTEM FOR SOURCE ONLY REOXIDATION AFTER JUNCTION IMPLANT FOR FLASH MEMORY DEVICES
71
Patent #:
6025240
Issue Dt:
02/15/2000
Application #:
08993600
Filing Dt:
12/18/1997
Title:
METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
72
Patent #:
6005804
Issue Dt:
12/21/1999
Application #:
08993634
Filing Dt:
12/18/1997
Title:
SPLIT VOLTAGE FOR NAND FLASH
73
Patent #:
6080682
Issue Dt:
06/27/2000
Application #:
08993716
Filing Dt:
12/18/1997
Title:
METHODOLOGY FOR ACHIEVING DUAL GATE OXIDE THICKNESSES
74
Patent #:
6015736
Issue Dt:
01/18/2000
Application #:
08993787
Filing Dt:
12/19/1997
Title:
METHOD AND SYSTEM FOR GATE STACK REOXIDATION CONTROL
75
Patent #:
6002151
Issue Dt:
12/14/1999
Application #:
08993890
Filing Dt:
12/18/1997
Title:
NON- VOLATILE TRENCH SEMICONDUCTOR DEVICE
76
Patent #:
6329257
Issue Dt:
12/11/2001
Application #:
08994140
Filing Dt:
12/19/1997
Title:
METHOD FOR LATERALLY PEAKED SOURCE DOPING PROFILES FOR BETTER ERASE CONTROL IN FLASH MEMORY DEVICES
77
Patent #:
6023435
Issue Dt:
02/08/2000
Application #:
08995381
Filing Dt:
12/22/1997
Title:
STAGGERED BITLINE PRECHARGE SCHEME
78
Patent #:
6124750
Issue Dt:
09/26/2000
Application #:
08995494
Filing Dt:
12/22/1997
Title:
CURRENT SENSING GATED CURRENT SOURCE FOR DELAY REDUCTION IN A UNIVERSAL SERIAL BUS (USB) LOW SPEED OUTPUT DRIVER
79
Patent #:
6148435
Issue Dt:
11/14/2000
Application #:
08998090
Filing Dt:
12/24/1997
Title:
OPTIMIZED PROGRAMMING/ERASE PARAMETERS FOR PROGRAMMABLE DEVICES
80
Patent #:
5959889
Issue Dt:
09/28/1999
Application #:
08998258
Filing Dt:
12/29/1997
Title:
COUNTER-BIAS SCHEME TO REDUCE CHARGE GAIN IN AN ELECTRICALLY ERASABLE CELL
81
Patent #:
6166439
Issue Dt:
12/26/2000
Application #:
09000739
Filing Dt:
12/30/1997
Title:
A LOW DIELECTRIC CONSTANT MATERIAL AND METHOD OF APPLICATION TO ISOLATE CONDUCTIVE LINES
82
Patent #:
5972749
Issue Dt:
10/26/1999
Application #:
09002783
Filing Dt:
01/05/1998
Title:
METHOD FOR PREVENTING P1 PUNCHTHROUGH
83
Patent #:
6235632
Issue Dt:
05/22/2001
Application #:
09006495
Filing Dt:
01/13/1998
Title:
TRUNGSTEN PLUG FORMATION
84
Patent #:
6188101
Issue Dt:
02/13/2001
Application #:
09006757
Filing Dt:
01/14/1998
Title:
FLASH EPROM CELL WITH REDUCED SHORT CHANNEL EFFECT AND METHOD FOR PROVIDING SAME
85
Patent #:
6906421
Issue Dt:
06/14/2005
Application #:
09006958
Filing Dt:
01/14/1998
Title:
METHOD OF FORMING A LOW RESISTIVITY TI-CONTAINING INTERCONNECT AND SEMICONDUCTOR DEVICE COMPRISING THE SAME
86
Patent #:
5892670
Issue Dt:
04/06/1999
Application #:
09007393
Filing Dt:
01/15/1998
Title:
IMPROVED CHARGE PUMP ARCHITECTURE
87
Patent #:
6492675
Issue Dt:
12/10/2002
Application #:
09008162
Filing Dt:
01/16/1998
Title:
FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
88
Patent #:
6001689
Issue Dt:
12/14/1999
Application #:
09008415
Filing Dt:
01/16/1998
Title:
PROCESS FOR FABRICATING A FLASH MEMORY WITH DUAL FUNCTION CONTROL LINES
89
Patent #:
6031425
Issue Dt:
02/29/2000
Application #:
09014250
Filing Dt:
01/27/1998
Title:
LOW POWER PRESCALER FOR A PLL CIRCUIT
90
Patent #:
5914903
Issue Dt:
06/22/1999
Application #:
09015912
Filing Dt:
01/30/1998
Title:
SEMICONDUCTOR MEMORY DEVICE
91
Patent #:
6011420
Issue Dt:
01/04/2000
Application #:
09017125
Filing Dt:
02/02/1998
Title:
ESD PROTECTION APPARATUS HAVING FLOATING ESD BUS AND SEMICONDUCTOR STRUCTURE
92
Patent #:
5963499
Issue Dt:
10/05/1999
Application #:
09018758
Filing Dt:
02/05/1998
Title:
CASCADABLE MULTI-CHANNEL NETWORK MEMORY WITH DYNAMIC ALLOCATION
93
Patent #:
6263398
Issue Dt:
07/17/2001
Application #:
09021132
Filing Dt:
02/10/1998
Title:
INTEGRATED CIRCUIT MEMORY DEVICE INCORPORATING A NON-VOLATILE MEMORY ARRAY AND A RELATIVELY FASTER ACCESS TIME MEMORY CACHE
94
Patent #:
6278295
Issue Dt:
08/21/2001
Application #:
09021461
Filing Dt:
02/10/1998
Title:
BUFFER WITH STABLE TRIP POINT
95
Patent #:
6081475
Issue Dt:
06/27/2000
Application #:
09021719
Filing Dt:
02/10/1998
Title:
WRITE CONTROL APPARATUS FOR MEMORY DEVICES
96
Patent #:
6069382
Issue Dt:
05/30/2000
Application #:
09022222
Filing Dt:
02/11/1998
Title:
NON-VOLATILE MEMORY CELL HAVING A HIGH COUPLING RATIO
97
Patent #:
5888867
Issue Dt:
03/30/1999
Application #:
09023241
Filing Dt:
02/13/1998
Title:
NON-UNIFORM THRESHOLD VOLTAGE ADJUSTMENT IN FLASH EPROMS THROUGH GATE WORK FUNCTION ALTERATION
98
Patent #:
6137153
Issue Dt:
10/24/2000
Application #:
09023497
Filing Dt:
02/13/1998
Title:
FLOATING GATE CAPACITOR FOR USE IN VOLTAGE REGULATORS
99
Patent #:
5923063
Issue Dt:
07/13/1999
Application #:
09026358
Filing Dt:
02/19/1998
Title:
DOUBLE DENSITY V NONVOLATILE MEMORY CELL
100
Patent #:
6100593
Issue Dt:
08/08/2000
Application #:
09032362
Filing Dt:
02/27/1998
Title:
MULTIPLE CHIP HYBRID PACKAGE USING BUMP TECHNOLOGY
Assignors
1
CYPRESS SEMICONDUCTOR CORPORATION
Exec Dt:
03/12/2015
2
SPANSION LLC
Exec Dt:
03/12/2015
Assignee
1
MORGAN STANLEY SENIOR FUNDING, INC.
1585 BROADWAY
NEW YORK, NEW YORK 10036
Correspondence name and address
SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP
ONE MANHATTAN WEST
MONIQUE L. RIBANDO
NEW YORK, NY 10001-8602

Search Results as of: 05/09/2024 12:03 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT