skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:058002/0470   Pages: 437
Recorded: 11/03/2020
Attorney Dkt #:127110/12
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST.
Total properties: 4704
Page 5 of 48
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
1
Patent #:
6091138
Issue Dt:
07/18/2000
Application #:
09032398
Filing Dt:
02/27/1998
Title:
MULTI-CHIP PACKAGING USING BUMP TECHNOLOGY
2
Patent #:
6187092
Issue Dt:
02/13/2001
Application #:
09033642
Filing Dt:
03/03/1998
Title:
METHOD AND APPARATUS FOR CONTROLLING THE THICKNESS OF A GATE OXIDE IN A SEMICONDUCTOR MANUFACTURING PROCESS
3
Patent #:
6043120
Issue Dt:
03/28/2000
Application #:
09033723
Filing Dt:
03/03/1998
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
4
Patent #:
6110833
Issue Dt:
08/29/2000
Application #:
09033836
Filing Dt:
03/03/1998
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRI NGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
5
Patent #:
6030868
Issue Dt:
02/29/2000
Application #:
09033916
Filing Dt:
03/03/1998
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
6
Patent #:
6169322
Issue Dt:
01/02/2001
Application #:
09036598
Filing Dt:
03/06/1998
Title:
DIE ATTACH PAD ADAPTED TO REDUCE DELAMINATION STRESS AND METHOD OF USING SAME
7
Patent #:
6118727
Issue Dt:
09/12/2000
Application #:
09038552
Filing Dt:
03/10/1998
Title:
SEMICONDUCTOR MEMORY WITH INTERDIGITATED ARRAY HAVING BIT LINE PAIRS ACCESSIBLE FOR EITHER OF TWO SIDE OF THE ARRAY
8
Patent #:
6225819
Issue Dt:
05/01/2001
Application #:
09040033
Filing Dt:
03/17/1998
Title:
TRANSMISSION LINE IMPEDANCE MATCHING OUTPUT BUFFER
9
Patent #:
6153487
Issue Dt:
11/28/2000
Application #:
09040107
Filing Dt:
03/17/1998
Title:
NEW APPROACH FOR THE FORMATION OF SEMICONDUCTOR DEVICES WHICH REDUCES BAND-TO-BAND TUNNELING CURRENT AND SHORT-CHANNEL EFFECTS
10
Patent #:
6248629
Issue Dt:
06/19/2001
Application #:
09040823
Filing Dt:
03/18/1998
Title:
PROCESS FOR FABRICATING A FLASH MEMORY DEVICE
11
Patent #:
5981339
Issue Dt:
11/09/1999
Application #:
09045013
Filing Dt:
03/20/1998
Title:
NARROWER ERASE DISTRIBUTION FOR FLASH MEMORY BY SMALLER POLY GRAIN SIZE
12
Patent #:
6207991
Issue Dt:
03/27/2001
Application #:
09045269
Filing Dt:
03/20/1998
Title:
INTEGRATED NON-VOLATILE AND CMOS MEMORIES HAVING SUBSTANTIALLY THE SAME THICKNESS GATES AND METHODS OF FORMING THE SAME
13
Patent #:
6124157
Issue Dt:
09/26/2000
Application #:
09045294
Filing Dt:
03/20/1998
Title:
INTEGRATED NON-VOLATILE AND RANDOM ACCESS MEMORY AND METHOD OF FORMING THE SAME
14
Patent #:
6160410
Issue Dt:
12/12/2000
Application #:
09046757
Filing Dt:
03/24/1998
Title:
APPARATUS, METHOD AND KIT FOR ADJUSTING INTEGRATED CIRCUIT LEAD DEFLECTION UPON A TEST SOCKET CONDUCTOR
15
Patent #:
6198305
Issue Dt:
03/06/2001
Application #:
09046960
Filing Dt:
03/24/1998
Title:
REDUCED AREA PRODUCT-TERM ARRAY
16
Patent #:
6057696
Issue Dt:
05/02/2000
Application #:
09046962
Filing Dt:
03/24/1998
Title:
APPARATUS, METHOD AND KIT FOR ALIGNING AN INTEGRATED CIRCUIT TO A TEST SOCKET
17
Patent #:
6262469
Issue Dt:
07/17/2001
Application #:
09047237
Filing Dt:
03/25/1998
Title:
CAPACITOR FOR USE IN A CAPACITOR DIVIDER THAT HAS A FLOATING GATE TRANSISTOR AS A CORRESPONDING CAPACITOR
18
Patent #:
6433645
Issue Dt:
08/13/2002
Application #:
09048905
Filing Dt:
03/26/1998
Title:
PROGRAMMABLE CLOCK GENERATOR
19
Patent #:
6023176
Issue Dt:
02/08/2000
Application #:
09049823
Filing Dt:
03/27/1998
Title:
INPUT BUFFER WITH PARALLEL PULL-UP TRANSISTORS WHEREIN THE BUFFER CAN BE SELECTIVELY CONFIGURED AS A VOLTAGE REFERENCED BUFFER OF A NON-REFERENCED BUFFER
20
Patent #:
6028448
Issue Dt:
02/22/2000
Application #:
09049887
Filing Dt:
03/27/1998
Title:
CIRCUITRY ARCHITECTURE AND METHOD FOR IMPROVING OUTPUT TRI-STATE TIME
21
Patent #:
6119249
Issue Dt:
09/12/2000
Application #:
09049952
Filing Dt:
03/27/1998
Title:
MEMORY DEVICES OPERABLE IN BOTH A NORMAL AND A TEST MODE AND METHODS FOR TESTING SAME
22
Patent #:
6209110
Issue Dt:
03/27/2001
Application #:
09050242
Filing Dt:
03/30/1998
Title:
CIRCUITRY, APPARATUS AND METHOD FOR EMBEDDING A TEST STATUS OUTCOME WITHIN A CIRCUIT BEING TESTED
23
Patent #:
6181615
Issue Dt:
01/30/2001
Application #:
09050243
Filing Dt:
03/30/1998
Title:
CIRCUITRY, APPARATUS AND METHOD FOR EMBEDDING QUANTIFIABLE TEST RESULTS WITHIN A CIRCUIT BEING TESTED
24
Patent #:
5896068
Issue Dt:
04/20/1999
Application #:
09050521
Filing Dt:
03/30/1998
Title:
VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY GAIN COMPENSATION CIRCUIT
25
Patent #:
6466072
Issue Dt:
10/15/2002
Application #:
09050548
Filing Dt:
03/30/1998
Title:
INTEGRATED CIRCUITRY FOR DELAY GENERATION
26
Patent #:
6163048
Issue Dt:
12/19/2000
Application #:
09051700
Filing Dt:
04/16/1998
Title:
SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE HAVING A NAND CELL STRUCTURE
27
Patent #:
6285054
Issue Dt:
09/04/2001
Application #:
09052057
Filing Dt:
03/30/1998
Title:
TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE WITH THE SOURCE/DRAIN REGIONS SPACED FROM THE TRENCH BY SIDEWALL DOPINGS
28
Patent #:
6225659
Issue Dt:
05/01/2001
Application #:
09052058
Filing Dt:
03/30/1998
Title:
TRENCHED GATE SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS
29
Patent #:
6147377
Issue Dt:
11/14/2000
Application #:
09052061
Filing Dt:
03/30/1998
Title:
FULLY RECESSED SEMICONDUCTOR DEVICE
30
Patent #:
5990515
Issue Dt:
11/23/1999
Application #:
09052062
Filing Dt:
03/30/1998
Title:
TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD WITH CORNER DOPING AND SIDEWALL DOPING
31
Patent #:
6171180
Issue Dt:
01/09/2001
Application #:
09052219
Filing Dt:
03/31/1998
Title:
PLANARIZING A TRENCH DIELECTRIC HAVING AN UPPER SURFACE WITHIN A TRENCH SPACED BELOW AN ADJACENT POLISH STOP SURFACE
32
Patent #:
6114724
Issue Dt:
09/05/2000
Application #:
09052770
Filing Dt:
03/31/1998
Title:
NONVOLATILE SEMICONDUCTOR MEMORY CELL WITH SELECT GATE
33
Patent #:
6005814
Issue Dt:
12/21/1999
Application #:
09054654
Filing Dt:
04/03/1998
Title:
TEST MODE ENTRANCE THROUGH CLOCKED ADDRESSES
34
Patent #:
5952670
Issue Dt:
09/14/1999
Application #:
09057783
Filing Dt:
04/09/1998
Title:
ANTI-WAFER BREAKAGE DETECTION SYSTEM
35
Patent #:
6065128
Issue Dt:
05/16/2000
Application #:
09057798
Filing Dt:
04/09/1998
Title:
ANTI-WAFER BREAKAGE DETECTION SYSTEM
36
Patent #:
6657241
Issue Dt:
12/02/2003
Application #:
09058549
Filing Dt:
04/10/1998
Title:
ESD STRUCTURE HAVING AN IMPROVED NOISE IMMUNITY IN CMOS AND BICMOS SEMICONDUCTOR DEVICES
37
Patent #:
6203608
Issue Dt:
03/20/2001
Application #:
09061362
Filing Dt:
04/15/1998
Title:
FERROELECTRIC THIN FILMS AND SOLUTIONS: COMPOSITIONS
38
Patent #:
5999452
Issue Dt:
12/07/1999
Application #:
09063688
Filing Dt:
04/21/1998
Title:
DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
39
Patent #:
6118321
Issue Dt:
09/12/2000
Application #:
09067107
Filing Dt:
04/27/1998
Title:
PASS TRANSISTOR CAPACITIVE COUPLING CONTROL CIRCUIT
40
Patent #:
6221776
Issue Dt:
04/24/2001
Application #:
09073033
Filing Dt:
05/05/1998
Title:
ANTI-REFLECTIVE COATING USED AS A DISPOSABLE ETCH STOP
41
Patent #:
6535960
Issue Dt:
03/18/2003
Application #:
09074317
Filing Dt:
05/08/1998
Title:
INFORMATION PROCESSING DEVICE
42
Patent #:
6211074
Issue Dt:
04/03/2001
Application #:
09076584
Filing Dt:
05/12/1998
Title:
METHODS AND ARRANGEMENTS FOR REDUCING STRESS AND PREVENTING CRACKING IN A SILICIDE LAYER
43
Patent #:
6159794
Issue Dt:
12/12/2000
Application #:
09076662
Filing Dt:
05/12/1998
Title:
METHODS FOR REMOVING SILICIDE RESIDUE IN A SEMICONDUCTOR DEVICE
44
Patent #:
6074956
Issue Dt:
06/13/2000
Application #:
09076663
Filing Dt:
05/12/1998
Title:
METHODS FOR PREVENTING SILICIDE RESIDUE FORMATION IN A SEMICONDUCTOR DEVICE
45
Patent #:
6362898
Issue Dt:
03/26/2002
Application #:
09076754
Filing Dt:
05/12/1998
Title:
PULSE WIDTH POSITION MODULATOR AND CLOCK SKEW SYNCHRONIZER
46
Patent #:
5990742
Issue Dt:
11/23/1999
Application #:
09076919
Filing Dt:
05/13/1998
Title:
DIFFERENTIAL AMPLIFIER CIRCUIT
47
Patent #:
6140676
Issue Dt:
10/31/2000
Application #:
09082167
Filing Dt:
05/20/1998
Title:
SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE HAVING AN IMPROVED WRITE SPEED
48
Patent #:
6211542
Issue Dt:
04/03/2001
Application #:
09085280
Filing Dt:
05/27/1998
Title:
COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR USING A LEAD-ENHANCED ESCAPSULATION LAYER
49
Patent #:
5901090
Issue Dt:
05/04/1999
Application #:
09085552
Filing Dt:
05/27/1998
Title:
METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM )
50
Patent #:
6157572
Issue Dt:
12/05/2000
Application #:
09085680
Filing Dt:
05/27/1998
Title:
METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY(EEPROM)
51
Patent #:
5875130
Issue Dt:
02/23/1999
Application #:
09085705
Filing Dt:
05/27/1998
Title:
METHOD FOR PROGRAMMING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
52
Patent #:
6084479
Issue Dt:
07/04/2000
Application #:
09086124
Filing Dt:
05/28/1998
Title:
CIRCUIT, ARCHITECTURE AND METHOD (S) OF CONTROLLING A PERIODIC SIGNAL GENERATING CIRCUIT OR DEVICE
53
Patent #:
6134686
Issue Dt:
10/17/2000
Application #:
09086870
Filing Dt:
05/29/1998
Title:
TECHNIQUE TO DETECT DRIVE STRENGTH OF INPUT PIN
54
Patent #:
6201408
Issue Dt:
03/13/2001
Application #:
09087654
Filing Dt:
05/30/1998
Title:
HYBRID PRODUCT TERM AND LOOK-UP TABLE-BASED PROGRAMMABLE LOGIC DEVICE WITH IMPROVED SPEED AND AREA EFFICIENCY
55
Patent #:
6211696
Issue Dt:
04/03/2001
Application #:
09087656
Filing Dt:
05/30/1998
Title:
HYBRID PRODUCT TERM AND LOOK-UP TABLE-BASED PROGRAMMABLE LOGIC DEVICE WITH IMPROVED SPEED AND AREA EFFICIENCY
56
Patent #:
6034395
Issue Dt:
03/07/2000
Application #:
09092352
Filing Dt:
06/05/1998
Title:
A SEMICONDUCTOR DEVICE HAVING A REDUCED HEIGHT FLOATING GATE
57
Patent #:
5948703
Issue Dt:
09/07/1999
Application #:
09092924
Filing Dt:
06/08/1998
Title:
METHOD OF SOFT-LANDING GATE ETCHING TO PREVENT GATE OXIDE DAMAGE
58
Patent #:
6034546
Issue Dt:
03/07/2000
Application #:
09093651
Filing Dt:
06/09/1998
Title:
HIGH PERFORMANCE PRODUCT TERM BASED CARRY CHAIN SCHEME
59
Patent #:
5936894
Issue Dt:
08/10/1999
Application #:
09094786
Filing Dt:
06/15/1998
Title:
DUAL LEVEL WORDLINE CLAMP FOR REDUCED MEMORY CELL CURRENT
60
Patent #:
6063666
Issue Dt:
05/16/2000
Application #:
09098292
Filing Dt:
06/16/1998
Title:
RTCVD OXIDE AND N2O ANNEAL FOR TOP OXIDE OF ONO FILM
61
Patent #:
6187667
Issue Dt:
02/13/2001
Application #:
09099655
Filing Dt:
06/17/1998
Title:
METHOD OF FORMING METAL LAYER (S) AND/OR ANTIREFLECTIVE COATING LAYER (S) ON AN INTEGRATED CIRCUIT
62
Patent #:
6360307
Issue Dt:
03/19/2002
Application #:
09099915
Filing Dt:
06/18/1998
Title:
CIRCUIT ARCHITECTURE AND METHOD OF WRITING DATA TO A MEMORY
63
Patent #:
5930172
Issue Dt:
07/27/1999
Application #:
09103041
Filing Dt:
06/23/1998
Title:
PAGE BUFFER FOR A MULTI-LEVEL FLASH MEMORY WITH A LIMITED NUMBER OF LATCHES PER MEMORY CELL
64
Patent #:
5973958
Issue Dt:
10/26/1999
Application #:
09103046
Filing Dt:
06/23/1998
Title:
INTERLACED STORAGE AND SENSE TECHNIQUE FOR FLASH MULTI-LEVEL DEVICES
65
Patent #:
6087858
Issue Dt:
07/11/2000
Application #:
09103960
Filing Dt:
06/24/1998
Title:
SELF-TIMED SENSE AMPLIFIER EVALUATION SCHEME
66
Patent #:
6320881
Issue Dt:
11/20/2001
Application #:
09104557
Filing Dt:
06/25/1998
Title:
METHOD, ARCHITECTURE AND CIRCUIT FOR LOCKING A DATA TRANSMISSION FRAME
67
Patent #:
6172553
Issue Dt:
01/09/2001
Application #:
09104643
Filing Dt:
06/25/1998
Title:
HIGH VOLTAGE STEERING NETWORK FOR EEPROM/FLASH MEMORY
68
Patent #:
6166982
Issue Dt:
12/26/2000
Application #:
09104919
Filing Dt:
06/25/1998
Title:
HIGH VOLTAGE SWITCH FOR EEPROM/FLASH MEMORIES
69
Patent #:
6271702
Issue Dt:
08/07/2001
Application #:
09105329
Filing Dt:
06/25/1998
Title:
CLOCK CIRCUIT FOR GENERATING A DELAY
70
Patent #:
6055177
Issue Dt:
04/25/2000
Application #:
09105724
Filing Dt:
06/26/1998
Title:
MEMORY CELL
71
Patent #:
6369421
Issue Dt:
04/09/2002
Application #:
09106177
Filing Dt:
06/29/1998
Title:
EEPROM HAVING STACKED DIELECTRIC TO INCREASE PROGRAMMING SPEED
72
Patent #:
6757349
Issue Dt:
06/29/2004
Application #:
09106715
Filing Dt:
06/29/1998
Title:
PLL FREQUENCY SYNTHESIZER WITH LOCK DETECTION CIRCUIT
73
Patent #:
5986970
Issue Dt:
11/16/1999
Application #:
09106806
Filing Dt:
06/29/1998
Title:
METHOD ARCHITECTURE AND CIRCUIT FOR WRITING TO A MEMORY
74
Patent #:
6094095
Issue Dt:
07/25/2000
Application #:
09106808
Filing Dt:
06/29/1998
Title:
EFFICIENT PUMP FOR GENERATING VOLTAGES ABOVE AND/OR BELOW OPERATING VOLTAGES
75
Patent #:
6122203
Issue Dt:
09/19/2000
Application #:
09107000
Filing Dt:
06/29/1998
Title:
METHOD, ARCHITECTURE AND CIRCUIT FOR WRITING TO AND READING FROM A MEMORY DURING A SINGLE CYCLE
76
Patent #:
6091631
Issue Dt:
07/18/2000
Application #:
09108529
Filing Dt:
07/01/1998
Title:
PROGRAM/VERIFY TECHNIQUE FOR MULTI-LEVEL FLASH CELLS ENABLING DIFFERENT THRESHOLD LEVELS TO BE SIMULTANEOUSLY PROGRAMMED
77
Patent #:
6159795
Issue Dt:
12/12/2000
Application #:
09109664
Filing Dt:
07/02/1998
Title:
LOW VOLTAGE JUNCTION AND HIGH VOLTAGE JUNCTION OPTIMIZATION FOR FLASH MEMORY
78
Patent #:
6346737
Issue Dt:
02/12/2002
Application #:
09109755
Filing Dt:
07/02/1998
Title:
SHALLOW TRENCH ISOLATION PROCESS PARTICULARLY SUITED FOR HIGH VOLTAGE CIRCUITS
79
Patent #:
6118147
Issue Dt:
09/12/2000
Application #:
09110446
Filing Dt:
07/07/1998
Title:
DOUBLE DENSITY NON-VOLATILE MEMEORY CELLS
80
Patent #:
6159860
Issue Dt:
12/12/2000
Application #:
09118375
Filing Dt:
07/17/1998
Title:
METHOD FOR ETCHING LAYERS ON A SEMICONDUCTOR WAFER IN A SINGLE ETCHING CHAMBER
81
Patent #:
5977601
Issue Dt:
11/02/1999
Application #:
09118377
Filing Dt:
07/17/1998
Title:
METHOD FOR ETCHING MEMORY GATE STACK USING THIN RESIST LAYER
82
Patent #:
6110779
Issue Dt:
08/29/2000
Application #:
09118382
Filing Dt:
07/17/1998
Title:
METHOD AND STRUCTURE OF ETCHING A MEMORY CELL POLISILICON GATE LAYER USING RESIST MASK AND ETCHED SILICON OXYNITRIDE
83
Patent #:
6174819
Issue Dt:
01/16/2001
Application #:
09119777
Filing Dt:
07/21/1998
Title:
LOW TEMPERATURE PHOTORESIST REMOVAL FOR REWORK DURING METAL MASK FORMATION
84
Patent #:
6286118
Issue Dt:
09/04/2001
Application #:
09120678
Filing Dt:
07/21/1998
Title:
SCAN PATH CIRCUITRY INCLUDING A PROGRAMMABLE DELAY CIRCUIT
85
Patent #:
6075477
Issue Dt:
06/13/2000
Application #:
09122646
Filing Dt:
07/27/1998
Title:
VOLTAGE SELECTOR FOR A D/A CONVERTER
86
Patent #:
5946255
Issue Dt:
08/31/1999
Application #:
09126832
Filing Dt:
07/31/1998
Title:
WORDLINE SYNCHRONIZED REFERENCE VOLTAGE GENERATOR
87
Patent #:
5909396
Issue Dt:
06/01/1999
Application #:
09127991
Filing Dt:
08/03/1998
Title:
HIGH VOLTAGE NMOS PASS GATE HAVING SUPPLY RANGE, AREA, AND SPEED ADVANTAGES
88
Patent #:
6100754
Issue Dt:
08/08/2000
Application #:
09128024
Filing Dt:
08/03/1998
Title:
VT REFERENCE VOLTAGE FOR EXTREMELY LOW POWER SUPPLY
89
Patent #:
6417539
Issue Dt:
07/09/2002
Application #:
09128864
Filing Dt:
08/04/1998
Publication #:
US20010020716
Pub Dt:
09/13/2001
Title:
HIGH DENSITY MEMORY CELL ASSEMBLY AND METHODS
90
Patent #:
6385265
Issue Dt:
05/07/2002
Application #:
09128901
Filing Dt:
08/04/1998
Title:
DIFFERENTIAL CHARGE PUMP
91
Patent #:
6060914
Issue Dt:
05/09/2000
Application #:
09131778
Filing Dt:
08/10/1998
Title:
SEMICONDUCTOR DEVICE INCLUDING A BOOST CIRCUIT
92
Patent #:
5978280
Issue Dt:
11/02/1999
Application #:
09132100
Filing Dt:
08/10/1998
Title:
METHOD, ARCHITECTURE AND CIRCUIT FOR REDUCING AND/OR ELIMINATING SMALL SIGNAL VOLTAGE SWING SENSITIVITY
93
Patent #:
6011721
Issue Dt:
01/04/2000
Application #:
09132347
Filing Dt:
08/12/1998
Title:
METHOD FOR SENSING STATE OF ERASURE OF A FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
94
Patent #:
6052310
Issue Dt:
04/18/2000
Application #:
09132981
Filing Dt:
08/12/1998
Title:
METHOD FOR TIGHTENING ERASE THRESHOLD VOLTAGE DISTRIBUTION IN FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
95
Patent #:
6107169
Issue Dt:
08/22/2000
Application #:
09134526
Filing Dt:
08/14/1998
Title:
METHOD FOR FABRICATING A DOPED POLYSILICON FEATURE IN A SEMICONDUCTOR DEVICE
96
Patent #:
6122191
Issue Dt:
09/19/2000
Application #:
09136694
Filing Dt:
08/19/1998
Title:
SEMICONDUCTOR NON-VOLATILE DEVICE INCLUDING EMBEDDED NON-VOLATILE ELEMENTS
97
Patent #:
6026018
Issue Dt:
02/15/2000
Application #:
09137914
Filing Dt:
08/20/1998
Title:
NON-VOLATILE, STATIC RANDOM ACCESS MEMORY WITH STORE DISTURB IMMUNITY
98
Patent #:
5972751
Issue Dt:
10/26/1999
Application #:
09143090
Filing Dt:
08/28/1998
Title:
METHODS AND ARRANGEMENTS FOR INTRODUCING NITROGEN INTO A TUNNEL OXIDE IN A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
99
Patent #:
6534378
Issue Dt:
03/18/2003
Application #:
09143899
Filing Dt:
08/31/1998
Title:
METHOD FOR FORMING AN INTEGRATED CIRCUIT DEVICE
100
Patent #:
5972124
Issue Dt:
10/26/1999
Application #:
09144353
Filing Dt:
08/31/1998
Title:
METHOD FOR CLEANING A SURFACE OF A DIELECTRIC MATERIAL
Assignors
1
CYPRESS SEMICONDUCTOR CORPORATION
Exec Dt:
03/12/2015
2
SPANSION LLC
Exec Dt:
03/12/2015
Assignee
1
MORGAN STANLEY SENIOR FUNDING, INC.
1585 BROADWAY
NEW YORK, NEW YORK 10036
Correspondence name and address
SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP
ONE MANHATTAN WEST
MONIQUE L. RIBANDO
NEW YORK, NY 10001-8602

Search Results as of: 05/08/2024 10:41 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT