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Reel/Frame:058002/0470   Pages: 437
Recorded: 11/03/2020
Attorney Dkt #:127110/12
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST.
Total properties: 4704
Page 6 of 48
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
1
Patent #:
Issue Dt:
09/26/2000
Application #:
09144506
Filing Dt:
08/31/1998
Title:
SCALABLE AND RELIABLE INTEGRATED CIRCUIT INTER-LEVEL DIELECTRIC
2
Patent #:
Issue Dt:
10/17/2000
Application #:
09144521
Filing Dt:
08/31/1998
Title:
REDUCTION OF SILICON OXYNITRIDE FILM DELAMINATION IN INTEGRATED CIRCUIT INTER-LEVEL DIELECTRICS
3
Patent #:
Issue Dt:
11/14/2000
Application #:
09146032
Filing Dt:
09/02/1998
Title:
METHOD FOR MANUFACTURING MEMORY DEVICES
4
Patent #:
Issue Dt:
08/08/2000
Application #:
09150551
Filing Dt:
09/09/1998
Title:
SELF-TIMED SYNCHRONOUS PULSE GENERATOR WITH TEST MODE
5
Patent #:
Issue Dt:
10/28/2003
Application #:
09151475
Filing Dt:
09/11/1998
Title:
METHOD OF DEPOSITING METAL ONTO A SUBSTRATE
6
Patent #:
Issue Dt:
02/20/2001
Application #:
09153941
Filing Dt:
09/16/1998
Title:
PROGRAMMABLE BUS HOLD CIRCUIT AND METHOD OF USING THE SAME
7
Patent #:
Issue Dt:
05/09/2000
Application #:
09154072
Filing Dt:
09/16/1998
Title:
STACKED GATE STRUCTURE FOR FLASH MEMORY APPLICATION
8
Patent #:
Issue Dt:
01/04/2000
Application #:
09154073
Filing Dt:
09/16/1998
Title:
METAL OXIDE STACK FOR FLASH MEMORY APPLICATION
9
Patent #:
Issue Dt:
12/14/1999
Application #:
09154074
Filing Dt:
09/16/1998
Title:
METHODS FOR FORMING NITROGEN-RICH REGIONS IN A FLOATING GATE AND INTERPOLY DIELECTRIC LAYER IN A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
10
Patent #:
Issue Dt:
03/07/2000
Application #:
09159023
Filing Dt:
09/23/1998
Title:
METHOD OF MAKING FLEXIBLY PARTITIONED METAL LINE SEGMENTS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
11
Patent #:
Issue Dt:
11/30/1999
Application #:
09159142
Filing Dt:
09/23/1998
Title:
SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
12
Patent #:
Issue Dt:
12/21/1999
Application #:
09159342
Filing Dt:
09/23/1998
Title:
MEMORY ADDRESS DECODING CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
13
Patent #:
Issue Dt:
08/14/2001
Application #:
09159489
Filing Dt:
09/23/1998
Title:
BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
14
Patent #:
Issue Dt:
10/31/2000
Application #:
09159908
Filing Dt:
09/24/1998
Title:
CIRCUITS, ARCHITECTURES AND METHODS FOR DETECTING AND CORRECTING EXCESS OSCILLATOR FREQUENCIES
15
Patent #:
Issue Dt:
01/14/2003
Application #:
09160046
Filing Dt:
09/25/1998
Publication #:
Pub Dt:
09/06/2001
Title:
FLASH MEMORY DEVICE AND A FABRICATION PROCESS THEREOF
16
Patent #:
Issue Dt:
10/05/1999
Application #:
09160858
Filing Dt:
09/25/1998
Title:
SECONDARY STORAGE DEVICE USING NONVOLATILE SEMICONDUCTOR MEMORY
17
Patent #:
Issue Dt:
11/23/1999
Application #:
09161423
Filing Dt:
09/24/1998
Title:
METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MEMORY
18
Patent #:
Issue Dt:
02/13/2001
Application #:
09161821
Filing Dt:
09/28/1998
Title:
CONFIGURABLE CLOCK GENERATOR
19
Patent #:
Issue Dt:
11/13/2001
Application #:
09162107
Filing Dt:
09/28/1998
Title:
HIGH DENSITY LEAD FRAMES AND METHODS FOR PLASTIC INJECTION MOLDING
20
Patent #:
Issue Dt:
06/05/2001
Application #:
09163310
Filing Dt:
09/30/1998
Title:
SELF-ALIGNING POLY 1 ONO DIELECTRIC FOR NON-VOLATILE MEMORY
21
Patent #:
Issue Dt:
06/26/2001
Application #:
09163315
Filing Dt:
09/30/1998
Title:
VIABLE MEMORY CELL FORMED USING RAPID THERMAL ANNEALING
22
Patent #:
Issue Dt:
08/01/2000
Application #:
09164531
Filing Dt:
09/30/1998
Title:
NON-VOLATILE, STATIC RANDOM ACCESS MEMORY WITH HIGH SPEED STORE CAPABILITY
23
Patent #:
Issue Dt:
06/19/2001
Application #:
09164952
Filing Dt:
10/01/1998
Title:
HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCUIT MEMORY DEVICES
24
Patent #:
Issue Dt:
03/20/2001
Application #:
09166384
Filing Dt:
10/05/1998
Title:
METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
25
Patent #:
Issue Dt:
05/22/2001
Application #:
09167799
Filing Dt:
10/07/1998
Title:
DYNAMIC SLEW RATE CONTROL OUTPUT BUFFER
26
Patent #:
Issue Dt:
12/19/2000
Application #:
09170061
Filing Dt:
10/13/1998
Title:
METHOD OF FORMING A COMPOSITE INTERPOLY GATE DIELECTRIC
27
Patent #:
Issue Dt:
04/11/2000
Application #:
09172410
Filing Dt:
10/14/1998
Title:
FLASH MEMORY DEVICE HAVING HIGH PERMITTIVITY STACKED DIELECTRIC AND FABRICATION THEREOF
28
Patent #:
Issue Dt:
08/15/2000
Application #:
09172956
Filing Dt:
10/14/1998
Title:
DEVICE AND METHOD FOR INTERCONNECTING UNIVERSAL SERIAL BUSES INCLUDING POWER MANAGEMENT
29
Patent #:
Issue Dt:
07/18/2000
Application #:
09173470
Filing Dt:
10/14/1998
Title:
DEVICE AND METHOD FOR SYNCHRONIZING THE CLOCKS OF INTERCONNECTED UNIVERSAL SERIAL BUSES
30
Patent #:
Issue Dt:
11/02/1999
Application #:
09175647
Filing Dt:
10/20/1998
Title:
BIT LINE BIASING METHOD TO ELIMATE PROGRAM DISTURBANCE IN A NON-VOLATILE MEMORY DEVICE AND MEMORY DEVICE EMPLOYING THE SAME
31
Patent #:
Issue Dt:
10/30/2001
Application #:
09176047
Filing Dt:
10/20/1998
Title:
DEVICE AND METHOD FOR EFFICIENT BULK DATA RETRIEVAL USING A UNIVERSAL SERIAL BUS
32
Patent #:
Issue Dt:
04/03/2001
Application #:
09177294
Filing Dt:
10/22/1998
Title:
PROCESS FOR FABRICATING A COMMON SOURCE REGION IN MEMORY DEVICES
33
Patent #:
Issue Dt:
01/16/2001
Application #:
09177392
Filing Dt:
10/23/1998
Title:
METHOD OF MANUFACTURING FERROELECTRIC MEMORY DEVICE USEFUL FOR PREVENTING HYDROGEN LINE DEGRADATION
34
Patent #:
Issue Dt:
01/23/2001
Application #:
09177817
Filing Dt:
10/23/1998
Title:
HIGH VOLTAGE TRANSISTOR WITH HIGH GATED DIODE BREAKDOWN VOLTAGE
35
Patent #:
Issue Dt:
08/13/2002
Application #:
09179212
Filing Dt:
10/26/1998
Title:
DIGITAL RADIO-FREQUENCY TRANSCEIVER
36
Patent #:
Issue Dt:
04/24/2001
Application #:
09179280
Filing Dt:
10/26/1998
Title:
OVERVOLTAGE TOLERANT INTEGRATED CIRCUIT INPUT/OUTPUT INTERFACE
37
Patent #:
Issue Dt:
04/09/2002
Application #:
09182525
Filing Dt:
10/30/1998
Title:
HIGH VOLTAGE TRANSISTOR WITH LOW BODY EFFECT AND LOW LEAKAGE
38
Patent #:
Issue Dt:
06/13/2000
Application #:
09189227
Filing Dt:
11/11/1998
Title:
LPCVD OXIDE AND RTA FOR TOP OXIDE OF ONO FILM TO IMPROVE RELIABILITY FOR FLASH MEMORY DEVICES
39
Patent #:
Issue Dt:
01/09/2001
Application #:
09192715
Filing Dt:
11/16/1998
Title:
SELECTABLE SINGLE ENDED-TO DIFFERENTIAL OUTPUT ADJUSTMENT SCHEME
40
Patent #:
Issue Dt:
04/17/2001
Application #:
09198654
Filing Dt:
11/24/1998
Title:
METHOD FOR FABRICATING A HIGH-DENSITY AND HIGH-RELIABILITY EEPROM DEVICE
41
Patent #:
Issue Dt:
10/24/2000
Application #:
09198747
Filing Dt:
11/24/1998
Title:
SEMICONDUCTOR REFERENCE VOLTAGE GENERATOR HAVING A NON VOLATILE MEMORY STRUCTURE
42
Patent #:
Issue Dt:
06/27/2000
Application #:
09199265
Filing Dt:
11/25/1998
Title:
SEMICONDUCTOR DEVICE CONTAINING P-HDP INTERDIELECTRIC LAYER
43
Patent #:
Issue Dt:
05/29/2001
Application #:
09199772
Filing Dt:
11/25/1998
Title:
METHOD FOR IMPROVING ELECTROSTATIC DISCHARGE ( ESD) ROBUSTNESS
44
Patent #:
Issue Dt:
04/23/2002
Application #:
09200219
Filing Dt:
11/25/1998
Title:
OUTPUT DATA PATH SCHEME IN A MEMORY DEVICE
45
Patent #:
Issue Dt:
06/27/2000
Application #:
09200373
Filing Dt:
11/24/1998
Title:
INTERRUPTIBLE STATE MACHINE
46
Patent #:
Issue Dt:
08/21/2001
Application #:
09205558
Filing Dt:
12/04/1998
Title:
UNIVERSAL SERIAL BUS PERIPHERAL BRIDGE SIMULATES A DEVICE DISCONNECT CONDITION TO A HOST WHEN THE DEVICE IS IN A NOT-READY CONDITION TO AVOID WASTING BUS RESOURCES
47
Patent #:
Issue Dt:
04/30/2002
Application #:
09205899
Filing Dt:
12/04/1998
Title:
METHOD OF FORMING ONO STACKED FILMS AND DCS TUNGSTEN SILICIDE GATE TO IMPROVE POLYCIDE GATE PERFORMANCE FOR FLASH MEMORY DEVICES
48
Patent #:
Issue Dt:
11/30/2004
Application #:
09207713
Filing Dt:
12/09/1998
Title:
METHOD FOR SHALLOW TRENCH ISOLATION AND SHALLOW TRENCH ISOLATION STRUCTURE
49
Patent #:
Issue Dt:
11/20/2001
Application #:
09208889
Filing Dt:
12/10/1998
Title:
MULTIPORT MEMORY SCHEME
50
Patent #:
Issue Dt:
08/14/2001
Application #:
09216460
Filing Dt:
12/18/1998
Title:
CIRCUIT AND METHOD FOR CONTROLLING AN OUTPUT OF A RING OSCILLATOR
51
Patent #:
Issue Dt:
02/12/2002
Application #:
09219663
Filing Dt:
12/23/1998
Title:
PROGRAMMABLE GATE ARRAY DEVICE
52
Patent #:
Issue Dt:
06/19/2001
Application #:
09221989
Filing Dt:
12/29/1998
Title:
TRANSISTOR OUTPUT CIRCUIT
53
Patent #:
Issue Dt:
11/27/2001
Application #:
09222578
Filing Dt:
12/28/1998
Title:
SCHEME FOR REDUCING LEAKAGE CURRENT IN AN INPUT BUFFER
54
Patent #:
Issue Dt:
12/07/1999
Application #:
09223281
Filing Dt:
12/30/1998
Title:
NONVOLATILE SEMICONDUTOR MEMORY DEVICE AND METHOD OF REPRODUCING DATA OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
55
Patent #:
Issue Dt:
07/11/2000
Application #:
09226748
Filing Dt:
01/06/1999
Title:
ONE-PIN SHIFT REGISTER INTERFACE
56
Patent #:
Issue Dt:
06/11/2002
Application #:
09231211
Filing Dt:
01/14/1999
Title:
SELF-ADJUSTING OPTIMAL DELAY TIME FILTER
57
Patent #:
Issue Dt:
06/27/2000
Application #:
09232023
Filing Dt:
01/14/1999
Title:
EEPROM DECODER BLOCK HAVING A P-WELL COUPLED TO A CHARGE PUMP FOR CHARGING THE P-WELL AND METHOD OF PROGRAMMING WITH THE EEPROM DECODER BLOCK
58
Patent #:
Issue Dt:
05/14/2002
Application #:
09232578
Filing Dt:
01/16/1999
Title:
DEDICATED CIRCUIT AND METHOD FOR ENUMERATING AND OPERATING A PERIPHERAL DEVICE ON A UNIVERSAL SERIAL BUS
59
Patent #:
Issue Dt:
05/30/2000
Application #:
09238270
Filing Dt:
01/27/1999
Title:
CIRCUIT AND METHOD FOR IMPLEMENTING SINGLE-CYCLE READ/WRITE OPERATION(S), AND RANDOM ACCESS MEMORY INCLUDING THE CIRCUIT AND/OR PRACTICING THE METHOD
60
Patent #:
Issue Dt:
07/17/2001
Application #:
09238953
Filing Dt:
01/27/1999
Title:
RANDOM ACCESS MEMORY HAVING INDEPENDENT READ PORT AND WRITE PORT AND PROCESS FOR WRITING TO AND READING FROM THE SAME
61
Patent #:
Issue Dt:
07/17/2001
Application #:
09238954
Filing Dt:
01/27/1999
Title:
RANDOM ACCESS MEMORY HAVING A READ/WRITE ADDRESS BUS AND PROCESS FOR WRITING TO AND READING FROM THE SAME
62
Patent #:
Issue Dt:
11/20/2001
Application #:
09241082
Filing Dt:
02/01/1999
Title:
SYSTEM LSI HAVING COMMUNICATION FUNCTION
63
Patent #:
Issue Dt:
02/04/2003
Application #:
09244429
Filing Dt:
02/04/1999
Title:
SEMICONDUCTOR DEVICES WITH REDUCED CONTROL GATE DIMENSIONS
64
Patent #:
Issue Dt:
01/16/2001
Application #:
09246981
Filing Dt:
02/09/1999
Title:
CLOCK GENERATOR WITH PROGRAMMABLE TWO-TONE MODULATION FOR EMI REDUCTION
65
Patent #:
Issue Dt:
11/09/1999
Application #:
09247546
Filing Dt:
02/10/1999
Title:
MEMORY DEVICE
66
Patent #:
Issue Dt:
09/19/2000
Application #:
09252123
Filing Dt:
02/18/1999
Title:
SCHEME FOR INCREASING ENMABLE ACCESS SPEED IN A MEMORY DEVICE
67
Patent #:
Issue Dt:
06/12/2001
Application #:
09252185
Filing Dt:
02/18/1999
Title:
LOW DIELECTRIC SEMICONDUCTOR DEVICE WITH RIGID, CONDUCTIVELY LINED INTERCONNECTION SYSTEM
68
Patent #:
Issue Dt:
12/23/2003
Application #:
09252186
Filing Dt:
02/18/1999
Title:
LOW DIELECTRIC METAL SILICIDE LINED INTERCONNECTION SYSTEM
69
Patent #:
Issue Dt:
06/12/2001
Application #:
09252854
Filing Dt:
09/08/1998
Title:
NOVEL PROCESS FOR RELIABLE ULTRATHIN OXYNITRIDE FORMATION
70
Patent #:
Issue Dt:
06/11/2002
Application #:
09253991
Filing Dt:
02/22/1999
Title:
SELECTIVE SAC ETCH PROCESS
71
Patent #:
Issue Dt:
01/08/2002
Application #:
09255108
Filing Dt:
02/22/1999
Title:
IN LINE YIELD PREDICTION USING ADC DETERMINED KILL RATIOS DIE HEALTH STATISTICS AND DIE STACKING
72
Patent #:
Issue Dt:
09/04/2001
Application #:
09257040
Filing Dt:
02/25/1999
Title:
SHARED MEMORY ACCESS DEVICE AND METHOD
73
Patent #:
Issue Dt:
10/17/2000
Application #:
09257468
Filing Dt:
02/24/1999
Title:
CONFIGURABLE MEMORY BLOCK
74
Patent #:
Issue Dt:
04/24/2001
Application #:
09257733
Filing Dt:
02/25/1999
Title:
USE OF IMPLANTED IONS TO REDUCE OXIDE-NITRIDE-OXIDE (ONO) ETCH RESIDUE AND POLYSTRINGERS
75
Patent #:
Issue Dt:
12/18/2001
Application #:
09259482
Filing Dt:
02/26/1999
Title:
HIGH RELIABILITY LEAD FRAME AND PACKAGING TECHNOLOGY CONTAINING THE SAME
76
Patent #:
Issue Dt:
01/30/2001
Application #:
09262430
Filing Dt:
03/04/1999
Title:
LOW SUPPLY VOLTAGE BICMOS SELF-BIASED BANDGAP REFERENCE USING A CURRENT SUMMING ARCHITECTURE
77
Patent #:
Issue Dt:
03/12/2002
Application #:
09263699
Filing Dt:
03/05/1999
Title:
EFFECT OF DOPED AMORPHOUS SI THICKNESS ON BETTER POLY 1 CONTACT RESISTANCE PERFORMANCE FOR NAND TYPE FLASH MEMORY DEVICES
78
Patent #:
Issue Dt:
02/06/2001
Application #:
09263701
Filing Dt:
03/05/1999
Title:
METHOD TO ELIMATE SILICIDE CRACKING FOR NAND TYPE FLASH MEMORY DEVICES BY IMPLANTING A POLISH RATE IMPROVER INTO THE SECOND POLYSILICON LAYER AND POLISHING IT
79
Patent #:
Issue Dt:
10/30/2001
Application #:
09263983
Filing Dt:
03/05/1999
Publication #:
Pub Dt:
11/29/2001
Title:
METHOD OF FORMING HIGH K TANTALUM PENTOXIDE TA205 INSTEAD OF ONO STACKED FILMS TO INCREASE COUPLING RATIO AND IMPROVE RELIABILITY FOR FLASH MEMORY DEVICES
80
Patent #:
Issue Dt:
05/17/2005
Application #:
09266869
Filing Dt:
03/12/1999
Title:
MICROCONTROLLER HAVING PREFETCH FUNCTION
81
Patent #:
Issue Dt:
05/23/2000
Application #:
09271330
Filing Dt:
03/18/1999
Title:
METHOD AND APPARATUS FOR PREVENTING P1 PUNCHTHROUGH
82
Patent #:
Issue Dt:
11/05/2002
Application #:
09272298
Filing Dt:
03/19/1999
Title:
OPTICAL COMMUNICATION DEVICE AND RECEIVING CIRCUIT THEREOF
83
Patent #:
Issue Dt:
05/15/2001
Application #:
09273310
Filing Dt:
03/19/1999
Title:
UNIVERSAL SERIAL BUS PERIPHERAL BRIDGE WITH SEQUENCER
84
Patent #:
Issue Dt:
02/20/2001
Application #:
09275336
Filing Dt:
03/24/1999
Title:
PROGRAMMABLE OSCILLATOR SCHEME
85
Patent #:
Issue Dt:
01/09/2001
Application #:
09275373
Filing Dt:
03/24/1999
Title:
METHOD FOR REDUCING STATIC PHASE OFFSET IN A PLL
86
Patent #:
Issue Dt:
12/05/2000
Application #:
09276321
Filing Dt:
03/25/1999
Title:
VOLTAGE CONVERSION/ REGULATOR CIRCUIT AND METHOD
87
Patent #:
Issue Dt:
12/07/1999
Application #:
09276947
Filing Dt:
03/26/1999
Title:
CHARGE PUMP ARCHITECTURE FOR INTEGRATED CIRCUIT
88
Patent #:
Issue Dt:
08/08/2000
Application #:
09277616
Filing Dt:
03/26/1999
Title:
NONVOLATILE CELL
89
Patent #:
Issue Dt:
08/20/2002
Application #:
09281672
Filing Dt:
03/30/1999
Title:
METHOD FOR FORMING NITROGEN-RICH SILICON OXIDE-BASED DIELECTRIC MATERIALS
90
Patent #:
Issue Dt:
06/05/2001
Application #:
09283166
Filing Dt:
04/01/1999
Title:
BARRIER LAYER TO PROTECT A FERROELECTRIC CAPACITOR AFTER CONTACT HAS BEEN MADE TO THE CAPACITOR ELECTRODE
91
Patent #:
Issue Dt:
11/07/2000
Application #:
09283308
Filing Dt:
03/31/1999
Title:
BARRIER LAYER DECREASES NITROGEN CONTAMINATION OF PERIPHERAL GATE REGIONS DURING TUNNEL OXIDE NITRIDATION
92
Patent #:
Issue Dt:
04/16/2002
Application #:
09286464
Filing Dt:
04/06/1999
Title:
METHOD FOR TRIMMING A PHOTORESIST PATTERN LINE FOR MEMORY GATE ETCHING
93
Patent #:
Issue Dt:
02/18/2003
Application #:
09288376
Filing Dt:
04/08/1999
Publication #:
Pub Dt:
01/16/2003
Title:
SYNCHRONIZATION MANAGER FOR STANDARDIZED SYNCHRONIZATION OF SEPARATE PROGRAMS
94
Patent #:
Issue Dt:
10/16/2001
Application #:
09300817
Filing Dt:
04/27/1999
Title:
METHODS OF FILLING CONSTRAINED SPACES WITH INSULATING MATERIALS AND/OR OF FORMING CONTACT HOLES AND/OR CONTACTS IN AN INTEGRATED CIRCUIT
95
Patent #:
Issue Dt:
02/06/2001
Application #:
09306306
Filing Dt:
05/06/1999
Title:
STORAGE CIRCUIT APPARATUS
96
Patent #:
Issue Dt:
02/13/2001
Application #:
09307259
Filing Dt:
05/06/1999
Title:
RAMPED OR STEPPED GATE CHANNEL ERASE FOR FLASH MEMORY APPLICATION
97
Patent #:
Issue Dt:
10/24/2000
Application #:
09307588
Filing Dt:
05/07/1999
Title:
OPTIMAL DELAY CONTROLLER
98
Patent #:
Issue Dt:
04/02/2002
Application #:
09309710
Filing Dt:
05/11/1999
Title:
LOCAL OSCILLATION CIRCUIT AND A RECEIVING CIRCUIT INCLUDING THE LOCAL OSCILLATION CIRCUIT
99
Patent #:
Issue Dt:
05/08/2001
Application #:
09309994
Filing Dt:
05/11/1999
Title:
CORE FIELD ISOLATION FOR A NAND FLASH MEMORY
100
Patent #:
Issue Dt:
09/05/2000
Application #:
09314535
Filing Dt:
05/19/1999
Title:
FRACTIONAL SYNTHESIS SCHEME FOR GENERATING PERIODIC SIGNALS
Assignors
1
Exec Dt:
03/12/2015
2
Exec Dt:
03/12/2015
Assignee
1
1585 BROADWAY
NEW YORK, NEW YORK 10036
Correspondence name and address
SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP
ONE MANHATTAN WEST
MONIQUE L. RIBANDO
NEW YORK, NY 10001-8602

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