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Reel/Frame:058002/0470   Pages: 437
Recorded: 11/03/2020
Attorney Dkt #:127110/12
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST.
Total properties: 4704
Page 8 of 48
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
1
Patent #:
6111787
Issue Dt:
08/29/2000
Application #:
09421776
Filing Dt:
10/19/1999
Title:
ADDRESS TRANSISTION DETECT TIMING ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
2
Patent #:
6185128
Issue Dt:
02/06/2001
Application #:
09421984
Filing Dt:
10/19/1999
Title:
REFERENCE CELL FOUR-WAY SWITCH FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
3
Patent #:
6359808
Issue Dt:
03/19/2002
Application #:
09421985
Filing Dt:
10/19/1999
Title:
LOW VOLTAGE READ CASCODE FOR 2V/3V AND DIFFERENT BANK COMBINATIONS WITHOUT METAL OPTIONS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
4
Patent #:
6259633
Issue Dt:
07/10/2001
Application #:
09422198
Filing Dt:
10/19/1999
Title:
SENSE AMPLIFIER ARCHITECTURE FOR SLIDING BANKS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
5
Patent #:
6118698
Issue Dt:
09/12/2000
Application #:
09422199
Filing Dt:
10/19/1999
Title:
OUTPUT MULTIPLEXING IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
6
Patent #:
6172907
Issue Dt:
01/09/2001
Application #:
09426100
Filing Dt:
10/22/1999
Title:
SILICON-OXIDE-NITRIDE-OXIDE-SEMICONDUCTOR (SONOS) TYPE MEMORY CELL AND METHOD FOR RETAINING DATA IN THE SAME
7
Patent #:
6248635
Issue Dt:
06/19/2001
Application #:
09426205
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING A BIT-LINE IN A MONOS DEVICE USING A DUAL LAYER HARD MASK
8
Patent #:
6218227
Issue Dt:
04/17/2001
Application #:
09426239
Filing Dt:
10/25/1999
Title:
METHOD TO GENERATE A MONOS TYPE FLASH CELL USING POLYCRYSTALLINE SILICON AS AN ONO TOP LAYER
9
Patent #:
6207502
Issue Dt:
03/27/2001
Application #:
09426255
Filing Dt:
10/25/1999
Title:
METHOD OF USING SOURCE/DRAIN NITRIDE FOR PERIPHERY FIELD OXIDE AND BIT-LINE OXIDE
10
Patent #:
6326268
Issue Dt:
12/04/2001
Application #:
09426427
Filing Dt:
10/25/1999
Title:
METHOD OF FABRICATING A MONOS FLASH CELL USING SHALLOW TRENCH ISOLATION
11
Patent #:
6248628
Issue Dt:
06/19/2001
Application #:
09426430
Filing Dt:
10/25/1999
Title:
METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS
12
Patent #:
6265268
Issue Dt:
07/24/2001
Application #:
09426672
Filing Dt:
10/25/1999
Title:
HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO BIT EEPROM DEVICE
13
Patent #:
6297143
Issue Dt:
10/02/2001
Application #:
09426743
Filing Dt:
10/25/1999
Title:
PROCESS FOR FORMING A BIT-LINE IN A MONOS DEVICE
14
Patent #:
6516378
Issue Dt:
02/04/2003
Application #:
09426757
Filing Dt:
10/26/1999
Title:
MICROPROCESSOR FOR CONTROLLING BUSSES
15
Patent #:
6117730
Issue Dt:
09/12/2000
Application #:
09427402
Filing Dt:
10/25/1999
Title:
INTEGRATED METHOD BY USING HIGH TEMPERATURE OXIDE FOR TOP OXIDE AND PERIPHERY GATE OXIDE
16
Patent #:
6242305
Issue Dt:
06/05/2001
Application #:
09427404
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING A BIT-LINE USING BURIED DIFFUSION ISOLATION
17
Patent #:
6287637
Issue Dt:
09/11/2001
Application #:
09427644
Filing Dt:
10/27/1999
Title:
MULTI-LAYER APPROACH FOR OPTIMIZING FERROELECTRIC FILM PERFORMANCE
18
Patent #:
6369660
Issue Dt:
04/09/2002
Application #:
09428624
Filing Dt:
10/27/1999
Title:
CIRCUIT AND METHOD FOR PREVENTING RUNAWAY IN A PHASE LOCK LOOP
19
Patent #:
6448609
Issue Dt:
09/10/2002
Application #:
09429244
Filing Dt:
10/28/1999
Title:
METHOD AND SYSTEM FOR PROVIDINNG A POLYSILICON STRINGER MONITOR
20
Patent #:
6399446
Issue Dt:
06/04/2002
Application #:
09429722
Filing Dt:
10/29/1999
Title:
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A METALLIC HARD MASK
21
Patent #:
6147907
Issue Dt:
11/14/2000
Application #:
09430336
Filing Dt:
10/29/1999
Title:
BIASING SCHEME TO REDUCE STRESS ON NON-SELECTED CELLS DURING READ
22
Patent #:
6867097
Issue Dt:
03/15/2005
Application #:
09430366
Filing Dt:
10/28/1999
Title:
METHOD OF MAKING A MEMORY CELL WITH POLISHED INSULATOR LAYER
23
Patent #:
6329273
Issue Dt:
12/11/2001
Application #:
09430410
Filing Dt:
10/29/1999
Title:
SOLID-SOURCE DOPING FOR SOURCE/DRAIN TO ELIMINATE IMPLANT DAMAGE
24
Patent #:
6436766
Issue Dt:
08/20/2002
Application #:
09430493
Filing Dt:
10/29/1999
Title:
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A POLYSILICON HARD MASK
25
Patent #:
6180454
Issue Dt:
01/30/2001
Application #:
09430765
Filing Dt:
10/29/1999
Title:
METHOD FOR FORMING FLASH MEMORY DEVICES
26
Patent #:
6441418
Issue Dt:
08/27/2002
Application #:
09430848
Filing Dt:
11/01/1999
Title:
SPACER NARROWED, DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
27
Patent #:
6163481
Issue Dt:
12/19/2000
Application #:
09431296
Filing Dt:
10/29/1999
Title:
FLASH MEMORY WORDLINE TRACKING ACROSS WHOLE CHIP
28
Patent #:
6319775
Issue Dt:
11/20/2001
Application #:
09433037
Filing Dt:
10/25/1999
Title:
NITRIDATION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE
29
Patent #:
6406960
Issue Dt:
06/18/2002
Application #:
09433041
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO STRUCTURE HAVING A SILICON-RICH SILICON NITRIDE LAYER
30
Patent #:
6458677
Issue Dt:
10/01/2002
Application #:
09433186
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO STRUCTURE
31
Patent #:
6166991
Issue Dt:
12/26/2000
Application #:
09433822
Filing Dt:
11/03/1999
Title:
CIRCUIT, ARCHITECTURE AND METHOD FOR REDUCING POWER CONSUMPTION IN A SYNCHRONOUS INTEGRATED CIRCUIT
32
Patent #:
6927756
Issue Dt:
08/09/2005
Application #:
09434908
Filing Dt:
11/05/1999
Title:
APPARATUS AND METHOD FOR CONTROLLING AN ELECTRONIC PRESENTATION
33
Patent #:
6553057
Issue Dt:
04/22/2003
Application #:
09436155
Filing Dt:
11/09/1999
Title:
CIRCUIT AND METHOD FOR LINEAR CONTROL OF A SPREAD SPECTRUM TRANSITION
34
Patent #:
6232632
Issue Dt:
05/15/2001
Application #:
09436503
Filing Dt:
11/09/1999
Title:
DOUBLE DENSITY NON-VOLATILE MEMORY CELLS
35
Patent #:
6850554
Issue Dt:
02/01/2005
Application #:
09436522
Filing Dt:
11/09/1999
Title:
CIRCUIT AND METHOD FOR CONTROLLING A SPREAD SPECTRUM TRANSITION
36
Patent #:
6309949
Issue Dt:
10/30/2001
Application #:
09440934
Filing Dt:
11/16/1999
Title:
SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
37
Patent #:
6608612
Issue Dt:
08/19/2003
Application #:
09441134
Filing Dt:
11/17/1999
Publication #:
US20030071777
Pub Dt:
04/17/2003
Title:
SELECTOR AND MULTILAYER INTERCONNECTION WITH REDUCED OCCUPIED AREA ON SUBSTRATE
38
Patent #:
6489805
Issue Dt:
12/03/2002
Application #:
09441649
Filing Dt:
11/17/1999
Publication #:
US20020171452
Pub Dt:
11/21/2002
Title:
CIRCUITS, ARCHITECTURES, AND METHODS FOR GENERATING A PERIODIC SIGNAL IN A MEMORY
39
Patent #:
6775627
Issue Dt:
08/10/2004
Application #:
09442715
Filing Dt:
11/18/1999
Title:
METHOD AND/OR SOFTWARE FOR DETERMINING THE CAPACITANCE OF AN ANALOG/MIXED SIGNAL CIRCUIT
40
Patent #:
6215689
Issue Dt:
04/10/2001
Application #:
09442851
Filing Dt:
11/18/1999
Title:
ARCHITECTURE, CIRCUITRY AND METHOD FOR CONFIGURING VOLATILE AND/OR NON-VOLATILE MEMORY FOR PROGRAMMABLE LOGIC APPLICATIONS
41
Patent #:
6246263
Issue Dt:
06/12/2001
Application #:
09451958
Filing Dt:
11/30/1999
Title:
MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
42
Patent #:
6467073
Issue Dt:
10/15/2002
Application #:
09451959
Filing Dt:
11/30/1999
Title:
METHOD AND APPARATUS FOR THE AUTOMATED GENERATION OF SINGLE AND MULTISTAGE PROGRAMMABLE INTERCONNECT MATRICES WITH AUTOMATIC ROUTING TOOLS
43
Patent #:
6144580
Issue Dt:
11/07/2000
Application #:
09456801
Filing Dt:
12/08/1999
Title:
NON-VOLATILE INVERTER LATCH
44
Patent #:
6329840
Issue Dt:
12/11/2001
Application #:
09458552
Filing Dt:
12/09/1999
Title:
Tristate output buffer with matched signals to pmos and nmos output transistors
45
Patent #:
6236596
Issue Dt:
05/22/2001
Application #:
09461376
Filing Dt:
12/15/1999
Title:
BIASING METHOD AND STRUCTURE FOR REDUCING BAND-TO-BAND AND/OR AVALANCHE CURRENTS DURING THE ERASE OF FLASH MEMORY DEVICES
46
Patent #:
6249464
Issue Dt:
06/19/2001
Application #:
09461632
Filing Dt:
12/15/1999
Title:
BLOCK REDUNDANCY IN ULTRA LOW POWER MEMORY CIRCUITS
47
Patent #:
6668302
Issue Dt:
12/23/2003
Application #:
09465067
Filing Dt:
12/16/1999
Title:
METHOD AND ARCHITECTURE FOR RE-PROGRAMMING CONVENTIONALLY NON-REPROGRAMMABLE TECHNOLOGY
48
Patent #:
6185123
Issue Dt:
02/06/2001
Application #:
09465724
Filing Dt:
12/17/1999
Title:
PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
49
Patent #:
6405353
Issue Dt:
06/11/2002
Application #:
09467098
Filing Dt:
12/10/1999
Title:
DUAL THRESHOLD DELAY MEASUREMENT/SCALING SCHEME TO AVOID NEGATIVE AND NON-MONOTONIC DELAY PARAMETERS IN TIMING ANALYSIS/CHARACTERIZATION OF CIRCUIT BLOCKS
50
Patent #:
6181610
Issue Dt:
01/30/2001
Application #:
09468938
Filing Dt:
12/22/1999
Title:
SEMICONDUCTOR DEVICE HAVING CURRENT AUXILIARY CIRCUIT FOR OUTPUT CIRCUIT
51
Patent #:
6225161
Issue Dt:
05/01/2001
Application #:
09470568
Filing Dt:
12/22/1999
Title:
FULLY RECESSED SEMICONDUCTOR METHOD FOR LOW POWER APPLICATIONS WITH SINGLE WRAP AROUND BURIED DRAIN REGION
52
Patent #:
6598176
Issue Dt:
07/22/2003
Application #:
09472005
Filing Dt:
12/27/1999
Title:
APPARATUS FOR ESTIMATING MICROCONTROLLER AND METHOD THEREOF
53
Patent #:
6388464
Issue Dt:
05/14/2002
Application #:
09475808
Filing Dt:
12/30/1999
Title:
CONFIGURABLE MEMORY FOR PROGRAMMABLE LOGIC CIRCUITS
54
Patent #:
6864710
Issue Dt:
03/08/2005
Application #:
09475879
Filing Dt:
12/30/1999
Title:
PROGRAMMABLE LOGIC DEVICE
55
Patent #:
6274433
Issue Dt:
08/14/2001
Application #:
09476121
Filing Dt:
01/03/2000
Title:
METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
56
Patent #:
6238978
Issue Dt:
05/29/2001
Application #:
09476584
Filing Dt:
01/03/2000
Title:
USE OF ETCH TO BLUNT GATE CORNERS
57
Patent #:
6969448
Issue Dt:
11/29/2005
Application #:
09476669
Filing Dt:
12/30/1999
Title:
METHOD FOR FORMING A METALLIZATION STRUCTURE IN AN INTEGRATED CIRCUIT
58
Patent #:
6518072
Issue Dt:
02/11/2003
Application #:
09476906
Filing Dt:
01/03/2000
Title:
DEPOSITED SCREEN OXIDE FOR REDUCING GATE EDGE LIFTING
59
Patent #:
6249825
Issue Dt:
06/19/2001
Application #:
09476923
Filing Dt:
01/04/2000
Title:
1376123452182SYSTEM FOR RECONFIGURING A PERIPHERAL DEVICE BY DOWNLOADING INFORMATION FROM A HOST AND ELECTRONICALLY SIMULATE A PHYSICAL DISCONNECTION AND RECONNECTION TO RECONFIGURE THE DEVICE
60
Patent #:
6410956
Issue Dt:
06/25/2002
Application #:
09478864
Filing Dt:
01/07/2000
Title:
METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
61
Patent #:
6638358
Issue Dt:
10/28/2003
Application #:
09483176
Filing Dt:
01/13/2000
Title:
METHOD AND SYSTEM FOR PROCESSING A SEMICONDUCTOR DEVICE
62
Patent #:
6225646
Issue Dt:
05/01/2001
Application #:
09483557
Filing Dt:
01/14/2000
Title:
Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base
63
Patent #:
6499089
Issue Dt:
12/24/2002
Application #:
09484975
Filing Dt:
01/18/2000
Title:
METHOD, ARCHITECTURE AND CIRCUITRY FOR INDEPENDENTLY CONFIGURING A MULTIPLE ARRAY MEMORY DEVICE
64
Patent #:
6376308
Issue Dt:
04/23/2002
Application #:
09487073
Filing Dt:
01/19/2000
Title:
Process for fabricating an eeprom device having a pocket substrate region
65
Patent #:
6168993
Issue Dt:
01/02/2001
Application #:
09487922
Filing Dt:
01/19/2000
Title:
Process for fabricating a semiconductor device having a graded junction
66
Patent #:
6465835
Issue Dt:
10/15/2002
Application #:
09487964
Filing Dt:
01/18/2000
Title:
CHARGE GAIN/CHARGE LOSS JUNCTION LEAKAGE PREVENTION FOR FLASH TECHNOLOGY BY USING DOUBLE ISOLATION/CAPPING LAYER BETWEEN LIGHTLY DOPED DRAIN AND GATE
67
Patent #:
6236603
Issue Dt:
05/22/2001
Application #:
09489232
Filing Dt:
01/21/2000
Title:
High speed charging of core cell drain lines in a memory device
68
Patent #:
6305076
Issue Dt:
10/23/2001
Application #:
09489256
Filing Dt:
01/21/2000
Title:
Apparatus for transferring a plurlity of integrated circuit devices into and/or out of a plurality of sockets
69
Patent #:
6212108
Issue Dt:
04/03/2001
Application #:
09490340
Filing Dt:
01/24/2000
Title:
Distributed voltage charge circuits to reduce sensing time in a memory device
70
Patent #:
6160740
Issue Dt:
12/12/2000
Application #:
09490351
Filing Dt:
01/24/2000
Title:
METHOD TO PROVIDE A REDUCED CONSTANT E-FIELD DURING ERASE OF EEPROMS FOR RELIABILITY IMPROVEMENT
71
Patent #:
6178117
Issue Dt:
01/23/2001
Application #:
09490352
Filing Dt:
01/24/2000
Title:
Background correction for charge gain and loss
72
Patent #:
6137727
Issue Dt:
10/24/2000
Application #:
09490353
Filing Dt:
01/24/2000
Title:
Reduction of oxide stress through the use of forward biased body voltage
73
Patent #:
6596466
Issue Dt:
07/22/2003
Application #:
09491044
Filing Dt:
01/25/2000
Title:
CONTACT STRUCTURE AND METHOD OF FORMING A CONTACT STRUCTURE
74
Patent #:
6509604
Issue Dt:
01/21/2003
Application #:
09491457
Filing Dt:
01/26/2000
Title:
NOVEL NITRIDATION BARRIERS FOR NITRIDATED TUNNEL OXIDE FOR CIRCUITRY FOR FLASH TECHNOLOGY AND FOR LOCOS/STI ISOLATION
75
Patent #:
6812521
Issue Dt:
11/02/2004
Application #:
09492243
Filing Dt:
01/27/2000
Title:
METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF FLASH MEMORY CELL DEVICES
76
Patent #:
6329687
Issue Dt:
12/11/2001
Application #:
09492353
Filing Dt:
01/27/2000
Title:
Two bit flash cell with two floating gate regions
77
Patent #:
6787840
Issue Dt:
09/07/2004
Application #:
09492931
Filing Dt:
01/27/2000
Title:
NITRIDATED TUNNEL OXIDE BARRIERS FOR FLASH MEMORY TECHOLOGY CIRCUITRY
78
Patent #:
6359307
Issue Dt:
03/19/2002
Application #:
09493436
Filing Dt:
01/29/2000
Title:
METHOD FOR FORMING SELF-ALIGNED CONTACTS AND INTERCONNECTION LINES USING DUAL DAMASCENE TECHNIQUES
79
Patent #:
6294430
Issue Dt:
09/25/2001
Application #:
09495213
Filing Dt:
01/31/2000
Title:
Nitridization of the pre-ddi screen oxide
80
Patent #:
6240016
Issue Dt:
05/29/2001
Application #:
09495214
Filing Dt:
01/31/2000
Title:
Method to reduce read gate disturb for flash eeprom application
81
Patent #:
6198664
Issue Dt:
03/06/2001
Application #:
09495215
Filing Dt:
01/31/2000
Title:
APDE scheme for flash memory application
82
Patent #:
6285588
Issue Dt:
09/04/2001
Application #:
09495216
Filing Dt:
01/31/2000
Title:
Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells
83
Patent #:
6160750
Issue Dt:
12/12/2000
Application #:
09498205
Filing Dt:
02/04/2000
Title:
Noise reduction during simultaneous operation of a flash memory device
84
Patent #:
6201409
Issue Dt:
03/13/2001
Application #:
09499816
Filing Dt:
02/08/2000
Title:
High performance product term based carry chain scheme
85
Patent #:
6747624
Issue Dt:
06/08/2004
Application #:
09501009
Filing Dt:
02/09/2000
Title:
DRIVING CIRCUIT FOR SUPPLYING TONE VOLTAGES TO LIQUID CRYSTAL DISPLAY PANEL
86
Patent #:
6243316
Issue Dt:
06/05/2001
Application #:
09501159
Filing Dt:
02/09/2000
Title:
Voltage boost reset circuit for a flash memory
87
Patent #:
6553549
Issue Dt:
04/22/2003
Application #:
09501246
Filing Dt:
02/10/2000
Title:
STATIC TIMING ANALYSIS WITH SIMULATIONS ON CRITICAL PATH NETLISTS GENERATED BY STATIS TIMING ANALYSIS TOOLS
88
Patent #:
6215705
Issue Dt:
04/10/2001
Application #:
09501448
Filing Dt:
02/10/2000
Title:
Simultaneous program, program-verify scheme
89
Patent #:
6348379
Issue Dt:
02/19/2002
Application #:
09502153
Filing Dt:
02/11/2000
Title:
Method of forming self-aligned contacts using consumable spacers
90
Patent #:
6420752
Issue Dt:
07/16/2002
Application #:
09502163
Filing Dt:
02/11/2000
Title:
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
91
Patent #:
6682978
Issue Dt:
01/27/2004
Application #:
09504087
Filing Dt:
02/15/2000
Title:
INTEGRATED CIRCUIT HAVING INCREASED GATE COUPLING CAPACITANCE
92
Patent #:
6651134
Issue Dt:
11/18/2003
Application #:
09504344
Filing Dt:
02/14/2000
Title:
MEMORY DEVICE WITH FIXED LENGTH NON-INTERRUPTIBLE BURST
93
Patent #:
6266281
Issue Dt:
07/24/2001
Application #:
09504695
Filing Dt:
02/16/2000
Title:
Method of erasing non-volatile memory cells
94
Patent #:
6215702
Issue Dt:
04/10/2001
Application #:
09504696
Filing Dt:
02/16/2000
Title:
Method of maintaining constant erasing speeds for non-volatile memory cells
95
Patent #:
6150184
Issue Dt:
11/21/2000
Application #:
09505106
Filing Dt:
02/15/2000
Title:
METHOD OF FABRICATING PARTIALLY OR COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
96
Patent #:
6243300
Issue Dt:
06/05/2001
Application #:
09505259
Filing Dt:
02/16/2000
Title:
Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
97
Patent #:
6727161
Issue Dt:
04/27/2004
Application #:
09505737
Filing Dt:
02/16/2000
Publication #:
US20030032260
Pub Dt:
02/13/2003
Title:
ISOLATION TECHNOLOGY FOR SUBMICRON SEMICONDUCTOR DEVICES
98
Patent #:
6455888
Issue Dt:
09/24/2002
Application #:
09506298
Filing Dt:
02/17/2000
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
99
Patent #:
6285583
Issue Dt:
09/04/2001
Application #:
09506351
Filing Dt:
02/17/2000
Title:
High speed sensing to detect write protect state in a flash memory device
100
Patent #:
6410443
Issue Dt:
06/25/2002
Application #:
09507810
Filing Dt:
02/22/2000
Title:
METHOD FOR REMOVING SEMICONDUCTOR ARC USING ARC CMP BUFFING
Assignors
1
CYPRESS SEMICONDUCTOR CORPORATION
Exec Dt:
03/12/2015
2
SPANSION LLC
Exec Dt:
03/12/2015
Assignee
1
MORGAN STANLEY SENIOR FUNDING, INC.
1585 BROADWAY
NEW YORK, NEW YORK 10036
Correspondence name and address
SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP
ONE MANHATTAN WEST
MONIQUE L. RIBANDO
NEW YORK, NY 10001-8602

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