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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:058871/0928   Pages: 15
Recorded: 11/12/2021
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 140
Page 1 of 2
Pages: 1 2
1
Patent #:
6881994
Issue Dt:
04/19/2005
Application #:
09927648
Filing Dt:
08/13/2001
Publication #:
US20020028541
Pub Dt:
03/07/2002
Title:
MONOLITHIC THREE DIMENSIONAL ARRAY OF CHARGE STORAGE DEVICES CONTAINING A PLANARIZED SURFACE
2
Patent #:
6841813
Issue Dt:
01/11/2005
Application #:
09983988
Filing Dt:
10/26/2001
Publication #:
US20030030074
Pub Dt:
02/13/2003
Title:
TFT MASK ROM AND METHOD FOR MAKING SAME
3
Patent #:
6897514
Issue Dt:
05/24/2005
Application #:
10066376
Filing Dt:
02/05/2002
Publication #:
US20020142546
Pub Dt:
10/03/2002
Title:
TWO MASK FLOATING GATE EEPROM AND METHOD OF MAKING
4
Patent #:
6567304
Issue Dt:
05/20/2003
Application #:
10144451
Filing Dt:
05/09/2002
Title:
MEMORY DEVICE AND METHOD FOR RELIABLY READING MULTI-BIT DATA FROM A WRITE-MANY MEMORY CELL
5
Patent #:
6908817
Issue Dt:
06/21/2005
Application #:
10268635
Filing Dt:
10/09/2002
Publication #:
US20040070021
Pub Dt:
04/15/2004
Title:
FLASH MEMORY ARRAY WITH INCREASED COUPLING BETWEEN FLOATING AND CONTROL GATES
6
Patent #:
7073103
Issue Dt:
07/04/2006
Application #:
10314055
Filing Dt:
12/05/2002
Publication #:
US20040109362
Pub Dt:
06/10/2004
Title:
SMART VERIFY FOR MULTI-STATE MEMORIES
7
Patent #:
7233024
Issue Dt:
06/19/2007
Application #:
10403752
Filing Dt:
03/31/2003
Publication #:
US20040188714
Pub Dt:
09/30/2004
Title:
THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED BIT LINE MEMORY ARRAY
8
Patent #:
7511352
Issue Dt:
03/31/2009
Application #:
10440882
Filing Dt:
05/19/2003
Publication #:
US20040232509
Pub Dt:
11/25/2004
Title:
RAIL SCHOTTKY DEVICE AND METHOD OF MAKING
9
Patent #:
NONE
Issue Dt:
Application #:
10796413
Filing Dt:
03/10/2004
Publication #:
US20050202615
Pub Dt:
09/15/2005
Title:
Nano-enabled memory devices and anisotropic charge carrying arrays
10
Patent #:
7129538
Issue Dt:
10/31/2006
Application #:
10842008
Filing Dt:
05/10/2004
Publication #:
US20040206996
Pub Dt:
10/21/2004
Title:
DENSE ARRAYS AND CHARGE STORAGE DEVICES
11
Patent #:
6992349
Issue Dt:
01/31/2006
Application #:
10849000
Filing Dt:
05/20/2004
Publication #:
US20040214379
Pub Dt:
10/28/2004
Title:
RAIL STACK ARRAY OF CHARGE STORAGE DEVICES AND METHOD OF MAKING SAME
12
Patent #:
7615436
Issue Dt:
11/10/2009
Application #:
10849152
Filing Dt:
05/20/2004
Publication #:
US20040207001
Pub Dt:
10/21/2004
Title:
TWO MASK FLOATING GATE EEPROM AND METHOD OF MAKING
13
Patent #:
7294882
Issue Dt:
11/13/2007
Application #:
10952689
Filing Dt:
09/28/2004
Publication #:
US20060071264
Pub Dt:
04/06/2006
Title:
NON-VOLATILE MEMORY WITH ASYMMETRICAL DOPING PROFILE
14
Patent #:
8637366
Issue Dt:
01/28/2014
Application #:
10955549
Filing Dt:
09/29/2004
Publication #:
US20050052915
Pub Dt:
03/10/2005
Title:
NONVOLATILE MEMORY CELL WITHOUT A DIELECTRIC ANTIFUSE HAVING HIGH- AND LOW-IMPEDANCE STATES
15
Patent #:
7566974
Issue Dt:
07/28/2009
Application #:
10955710
Filing Dt:
09/29/2004
Publication #:
US20060071074
Pub Dt:
04/06/2006
Title:
DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS
16
Patent #:
7250646
Issue Dt:
07/31/2007
Application #:
10965780
Filing Dt:
10/18/2004
Publication #:
US20050070060
Pub Dt:
03/31/2005
Title:
TFT MASK ROM AND METHOD FOR MAKING SAME
17
Patent #:
7595528
Issue Dt:
09/29/2009
Application #:
11018572
Filing Dt:
12/21/2004
Publication #:
US20050201149
Pub Dt:
09/15/2005
Title:
NANO-ENABLED MEMORY DEVICES AND ANISOTROPIC CHARGE CARRYING ARRAYS
18
Patent #:
7517796
Issue Dt:
04/14/2009
Application #:
11061952
Filing Dt:
02/17/2005
Publication #:
US20060183282
Pub Dt:
08/17/2006
Title:
METHOD FOR PATTERNING SUBMICRON PILLARS
19
Patent #:
7521353
Issue Dt:
04/21/2009
Application #:
11089771
Filing Dt:
03/25/2005
Publication #:
US20060216931
Pub Dt:
09/28/2006
Title:
METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES
20
Patent #:
7173854
Issue Dt:
02/06/2007
Application #:
11097038
Filing Dt:
04/01/2005
Publication #:
US20060221693
Pub Dt:
10/05/2006
Title:
NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS
21
Patent #:
7170784
Issue Dt:
01/30/2007
Application #:
11097502
Filing Dt:
04/01/2005
Publication #:
US20060221694
Pub Dt:
10/05/2006
Title:
NON-VOLATILE MEMORY AND METHOD WITH CONTROL GATE COMPENSATION FOR SOURCE LINE BIAS ERRORS
22
Patent #:
7170131
Issue Dt:
01/30/2007
Application #:
11132522
Filing Dt:
05/18/2005
Publication #:
US20050207226
Pub Dt:
09/22/2005
Title:
FLASH MEMORY ARRAY WITH INCREASED COUPLING BETWEEN FLOATING AND CONTROL GATES
23
Patent #:
7267875
Issue Dt:
09/11/2007
Application #:
11147670
Filing Dt:
06/07/2005
Publication #:
US20060040103
Pub Dt:
02/23/2006
Title:
POST-DEPOSITION ENCAPSULATION OF NANOSTRUCTURES: COMPOSITIONS, DEVICES AND SYSTEMS INCORPORATING SAME
24
Patent #:
7501315
Issue Dt:
03/10/2009
Application #:
11148001
Filing Dt:
06/07/2005
Publication #:
US20050287717
Pub Dt:
12/29/2005
Title:
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
25
Patent #:
7800932
Issue Dt:
09/21/2010
Application #:
11237167
Filing Dt:
09/28/2005
Publication #:
US20070090425
Pub Dt:
04/26/2007
Title:
MEMORY CELL COMPRISING SWITCHABLE SEMICONDUCTOR MEMORY ELEMENT WITH TRIMMABLE RESISTANCE
26
Patent #:
7615448
Issue Dt:
11/10/2009
Application #:
11296022
Filing Dt:
12/06/2005
Publication #:
US20070128787
Pub Dt:
06/07/2007
Title:
METHOD OF FORMING LOW RESISTANCE VOID-FREE CONTACTS
27
Patent #:
7737483
Issue Dt:
06/15/2010
Application #:
11296235
Filing Dt:
12/06/2005
Publication #:
US20070126028
Pub Dt:
06/07/2007
Title:
LOW RESISTANCE VOID-FREE CONTACTS
28
Patent #:
8563133
Issue Dt:
10/22/2013
Application #:
11299299
Filing Dt:
12/09/2005
Publication #:
US20080118755
Pub Dt:
05/22/2008
Title:
COMPOSITIONS AND METHODS FOR MODULATION OF NANOSTRUCTURE ENERGY LEVELS
29
Patent #:
7615502
Issue Dt:
11/10/2009
Application #:
11303229
Filing Dt:
12/16/2005
Publication #:
US20070141858
Pub Dt:
06/21/2007
Title:
LASER ANNEAL OF VERTICALLY ORIENTED SEMICONDUCTOR STRUCTURES WHILE MAINTAINING A DOPANT PROFILE
30
Patent #:
7243275
Issue Dt:
07/10/2007
Application #:
11304961
Filing Dt:
12/14/2005
Publication #:
US20060107136
Pub Dt:
05/18/2006
Title:
SMART VERIFY FOR MULTI-STATE MEMORIES
31
Patent #:
7616481
Issue Dt:
11/10/2009
Application #:
11320917
Filing Dt:
12/28/2005
Publication #:
US20070171744
Pub Dt:
07/26/2007
Title:
MEMORIES WITH ALTERNATE SENSING TECHNIQUES
32
Patent #:
7349264
Issue Dt:
03/25/2008
Application #:
11321996
Filing Dt:
12/28/2005
Publication #:
US20070147113
Pub Dt:
06/28/2007
Title:
ALTERNATE SENSING TECHNIQUES FOR NON-VOLATILE MEMORIES
33
Patent #:
7799637
Issue Dt:
09/21/2010
Application #:
11426560
Filing Dt:
06/26/2006
Publication #:
US20070298568
Pub Dt:
12/27/2007
Title:
SCALED DIELECTRIC ENABLED BY STACK SIDEWALL PROCESS
34
Patent #:
7463536
Issue Dt:
12/09/2008
Application #:
11461359
Filing Dt:
07/31/2006
Publication #:
US20080025085
Pub Dt:
01/31/2008
Title:
MEMORY ARRAY INCORPORATING TWO DATA BUSSES FOR MEMORY ARRAY BLOCK SELECTION
35
Patent #:
7570523
Issue Dt:
08/04/2009
Application #:
11461372
Filing Dt:
07/31/2006
Publication #:
US20080025134
Pub Dt:
01/31/2008
Title:
METHOD FOR USING TWO DATA BUSSES FOR MEMORY ARRAY BLOCK SELECTION
36
Patent #:
7755132
Issue Dt:
07/13/2010
Application #:
11465025
Filing Dt:
08/16/2006
Publication #:
US20080042183
Pub Dt:
02/21/2008
Title:
NONVOLATILE MEMORIES WITH SHAPED FLOATING GATES
37
Patent #:
7494860
Issue Dt:
02/24/2009
Application #:
11465038
Filing Dt:
08/16/2006
Publication #:
US20080044972
Pub Dt:
02/21/2008
Title:
METHODS OF FORMING NONVOLATILE MEMORIES WITH L-SHAPED FLOATING GATES
38
Patent #:
7534690
Issue Dt:
05/19/2009
Application #:
11469281
Filing Dt:
08/31/2006
Publication #:
US20070015332
Pub Dt:
01/18/2007
Title:
NON-VOLATILE MEMORY WITH ASYMMETRICAL DOPING PROFILE
39
Patent #:
7754605
Issue Dt:
07/13/2010
Application #:
11478706
Filing Dt:
06/30/2006
Publication #:
US20080003793
Pub Dt:
01/03/2008
Title:
ULTRASHALLOW SEMICONDUCTOR CONTACT BY OUTDIFFUSION FROM A SOLID SOURCE
40
Patent #:
7525137
Issue Dt:
04/28/2009
Application #:
11484757
Filing Dt:
07/12/2006
Publication #:
US20060249735
Pub Dt:
11/09/2006
Title:
TFT MASK ROM AND METHOD FOR MAKING SAME
41
Patent #:
7776758
Issue Dt:
08/17/2010
Application #:
11495188
Filing Dt:
07/28/2006
Publication #:
US20070032091
Pub Dt:
02/08/2007
Title:
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
42
Patent #:
NONE
Issue Dt:
Application #:
11496870
Filing Dt:
07/31/2006
Publication #:
US20080025069
Pub Dt:
01/31/2008
Title:
Mixed-use memory array with different data states
43
Patent #:
NONE
Issue Dt:
Application #:
11496874
Filing Dt:
07/31/2006
Publication #:
US20080023790
Pub Dt:
01/31/2008
Title:
Mixed-use memory array
44
Patent #:
7450414
Issue Dt:
11/11/2008
Application #:
11496983
Filing Dt:
07/31/2006
Publication #:
US20080025118
Pub Dt:
01/31/2008
Title:
METHOD FOR USING A MIXED-USE MEMORY ARRAY
45
Patent #:
7447056
Issue Dt:
11/04/2008
Application #:
11496984
Filing Dt:
07/31/2006
Publication #:
US20070070690
Pub Dt:
03/29/2007
Title:
METHOD FOR USING A MULTI-USE MEMORY CELL AND MEMORY ARRAY
46
Patent #:
NONE
Issue Dt:
Application #:
11496985
Filing Dt:
07/31/2006
Publication #:
US20070069276
Pub Dt:
03/29/2007
Title:
Multi-use memory cell and memory array
47
Patent #:
7800933
Issue Dt:
09/21/2010
Application #:
11496986
Filing Dt:
07/31/2006
Publication #:
US20070072360
Pub Dt:
03/29/2007
Title:
METHOD FOR USING A MEMORY CELL COMPRISING SWITCHABLE SEMICONDUCTOR MEMORY ELEMENT WITH TRIMMABLE RESISTANCE
48
Patent #:
7486537
Issue Dt:
02/03/2009
Application #:
11497021
Filing Dt:
07/31/2006
Publication #:
US20080025062
Pub Dt:
01/31/2008
Title:
METHOD FOR USING A MIXED-USE MEMORY ARRAY WITH DIFFERENT DATA STATES
49
Patent #:
7606091
Issue Dt:
10/20/2009
Application #:
11531217
Filing Dt:
09/12/2006
Publication #:
US20080062768
Pub Dt:
03/13/2008
Title:
METHOD FOR NON-VOLATILE MEMORY WITH REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE
50
Patent #:
7606077
Issue Dt:
10/20/2009
Application #:
11531223
Filing Dt:
09/12/2006
Publication #:
US20080062785
Pub Dt:
03/13/2008
Title:
NON-VOLATILE MEMORY WITH REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE
51
Patent #:
7453731
Issue Dt:
11/18/2008
Application #:
11531227
Filing Dt:
09/12/2006
Publication #:
US20080062765
Pub Dt:
03/13/2008
Title:
METHOD FOR NON-VOLATILE MEMORY WITH LINEAR ESTIMATION OF INITIAL PROGRAMMING VOLTAGE
52
Patent #:
7599223
Issue Dt:
10/06/2009
Application #:
11531230
Filing Dt:
09/12/2006
Publication #:
US20080062770
Pub Dt:
03/13/2008
Title:
NON-VOLATILE MEMORY WITH LINEAR ESTIMATION OF INITIAL PROGRAMMING VOLTAGE
53
Patent #:
NONE
Issue Dt:
Application #:
11544666
Filing Dt:
10/10/2006
Publication #:
US20070029607
Pub Dt:
02/08/2007
Title:
Dense arrays and charge storage devices
54
Patent #:
7391638
Issue Dt:
06/24/2008
Application #:
11552426
Filing Dt:
10/24/2006
Publication #:
US20080094913
Pub Dt:
04/24/2008
Title:
MEMORY DEVICE FOR PROTECTING MEMORY CELLS DURING PROGRAMMING
55
Patent #:
7589989
Issue Dt:
09/15/2009
Application #:
11552441
Filing Dt:
10/24/2006
Publication #:
US20080094892
Pub Dt:
04/24/2008
Title:
METHOD FOR PROTECTING MEMORY CELLS DURING PROGRAMMING
56
Patent #:
7811916
Issue Dt:
10/12/2010
Application #:
11610090
Filing Dt:
12/13/2006
Publication #:
US20080145994
Pub Dt:
06/19/2008
Title:
METHOD FOR ISOTROPIC DOPING OF A NON-PLANAR SURFACE EXPOSED IN A VOID
57
Patent #:
7642160
Issue Dt:
01/05/2010
Application #:
11614894
Filing Dt:
12/21/2006
Publication #:
US20080153226
Pub Dt:
06/26/2008
Title:
METHOD OF FORMING A FLASH NAND MEMORY CELL ARRAY WITH CHARGE STORAGE ELEMENTS POSITIONED IN TRENCHES
58
Patent #:
7800161
Issue Dt:
09/21/2010
Application #:
11614909
Filing Dt:
12/21/2006
Publication #:
US20080149996
Pub Dt:
06/26/2008
Title:
FLASH NAND MEMORY CELL ARRAY WITH CHARGE STORAGE ELEMENTS POSITIONED IN TRENCHES
59
Patent #:
7791191
Issue Dt:
09/07/2010
Application #:
11617687
Filing Dt:
12/28/2006
Publication #:
US20080157355
Pub Dt:
07/03/2008
Title:
SEMICONDUCTOR DEVICE HAVING MULTIPLE DIE REDISTRIBUTION LAYER
60
Patent #:
7560304
Issue Dt:
07/14/2009
Application #:
11617689
Filing Dt:
12/28/2006
Publication #:
US20080160674
Pub Dt:
07/03/2008
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING MULTIPLE DIE REDISTRIBUTION LAYER
61
Patent #:
7592225
Issue Dt:
09/22/2009
Application #:
11623314
Filing Dt:
01/15/2007
Publication #:
US20080171428
Pub Dt:
07/17/2008
Title:
METHODS OF FORMING SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES
62
Patent #:
7773403
Issue Dt:
08/10/2010
Application #:
11623315
Filing Dt:
01/15/2007
Publication #:
US20080169567
Pub Dt:
07/17/2008
Title:
SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES
63
Patent #:
7391645
Issue Dt:
06/24/2008
Application #:
11624617
Filing Dt:
01/18/2007
Publication #:
US20070115721
Pub Dt:
05/24/2007
Title:
NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS
64
Patent #:
7391646
Issue Dt:
06/24/2008
Application #:
11624627
Filing Dt:
01/18/2007
Publication #:
US20070115722
Pub Dt:
05/24/2007
Title:
NON-VOLATILE MEMORY AND METHOD WITH CONTROL GATE COMPENSATION FOR SOURCE LINE BIAS ERRORS
65
Patent #:
7517756
Issue Dt:
04/14/2009
Application #:
11668306
Filing Dt:
01/29/2007
Publication #:
US20070122980
Pub Dt:
05/31/2007
Title:
FLASH MEMORY ARRAY WITH INCREASED COUPLING BETWEEN FLOATING AND CONTROL GATES
66
Patent #:
7382017
Issue Dt:
06/03/2008
Application #:
11695728
Filing Dt:
04/03/2007
Publication #:
US20070187768
Pub Dt:
08/16/2007
Title:
NANO-ENABLED MEMORY DEVICES AND ANISOTROPIC CHARGE CARRYING ARRAYS
67
Patent #:
7585564
Issue Dt:
09/08/2009
Application #:
11706730
Filing Dt:
02/13/2007
Publication #:
US20080032134
Pub Dt:
02/07/2008
Title:
POST-DEPOSITION ENCAPSULATION OF NANOSTRUCTURES: COMPOSITIONS, DEVICES AND SYSTEMS INCORPORATING SAME
68
Patent #:
7584391
Issue Dt:
09/01/2009
Application #:
11759872
Filing Dt:
06/07/2007
Publication #:
US20070234144
Pub Dt:
10/04/2007
Title:
SMART VERIFY FOR MULTI-STATE MEMORIES
69
Patent #:
8659028
Issue Dt:
02/25/2014
Application #:
11764789
Filing Dt:
06/18/2007
Publication #:
US20070263423
Pub Dt:
11/15/2007
Title:
THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY
70
Patent #:
NONE
Issue Dt:
Application #:
11766980
Filing Dt:
06/22/2007
Publication #:
US20070247904
Pub Dt:
10/25/2007
Title:
Nano-enabled memory devices and anisotropic charge carrying arrays
71
Patent #:
7772047
Issue Dt:
08/10/2010
Application #:
11769927
Filing Dt:
06/28/2007
Publication #:
US20090004781
Pub Dt:
01/01/2009
Title:
METHOD OF FABRICATING A SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
72
Patent #:
7763980
Issue Dt:
07/27/2010
Application #:
11769937
Filing Dt:
06/28/2007
Publication #:
US20090001610
Pub Dt:
01/01/2009
Title:
SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
73
Patent #:
7629247
Issue Dt:
12/08/2009
Application #:
11786620
Filing Dt:
04/12/2007
Publication #:
US20080254576
Pub Dt:
10/16/2008
Title:
METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE
74
Patent #:
NONE
Issue Dt:
Application #:
11850127
Filing Dt:
09/05/2007
Publication #:
US20080026532
Pub Dt:
01/31/2008
Title:
Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays
75
Patent #:
7968273
Issue Dt:
06/28/2011
Application #:
11881739
Filing Dt:
07/27/2007
Publication #:
US20100155786
Pub Dt:
06/24/2010
Title:
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
76
Patent #:
8466068
Issue Dt:
06/18/2013
Application #:
11967638
Filing Dt:
12/31/2007
Publication #:
US20090166682
Pub Dt:
07/02/2009
Title:
METHODS AND APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY
77
Patent #:
7759201
Issue Dt:
07/20/2010
Application #:
12000758
Filing Dt:
12/17/2007
Publication #:
US20090155962
Pub Dt:
06/18/2009
Title:
METHOD FOR FABRICATING PITCH-DOUBLING PILLAR STRUCTURES
78
Patent #:
7887999
Issue Dt:
02/15/2011
Application #:
12005276
Filing Dt:
12/27/2007
Publication #:
US20090170030
Pub Dt:
07/02/2009
Title:
METHOD OF MAKING A PILLAR PATTERN USING TRIPLE OR QUADRUPLE EXPOSURE
79
Patent #:
7460406
Issue Dt:
12/02/2008
Application #:
12023317
Filing Dt:
01/31/2008
Publication #:
US20080123414
Pub Dt:
05/29/2008
Title:
ALTERNATE SENSING TECHNIQUES FOR NON-VOLATILE MEMORIES
80
Patent #:
7704832
Issue Dt:
04/27/2010
Application #:
12058512
Filing Dt:
03/28/2008
Publication #:
US20080248621
Pub Dt:
10/09/2008
Title:
INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION
81
Patent #:
7582529
Issue Dt:
09/01/2009
Application #:
12061641
Filing Dt:
04/02/2008
Publication #:
US20080248622
Pub Dt:
10/09/2008
Title:
METHODS OF FABRICATING NON-VOLATILE MEMORY WITH INTEGRATED PERIPHERAL CIRCUITRY AND PRE-ISOLATION MEMORY CELL FORMATION
82
Patent #:
7592223
Issue Dt:
09/22/2009
Application #:
12061642
Filing Dt:
04/02/2008
Publication #:
US20080268596
Pub Dt:
10/30/2008
Title:
METHODS OF FABRICATING NON-VOLATILE MEMORY WITH INTEGRATED SELECT AND PERIPHERAL CIRCUITRY AND POST-ISOLATION MEMORY CELL FORMATION
83
Patent #:
7593249
Issue Dt:
09/22/2009
Application #:
12140991
Filing Dt:
06/17/2008
Publication #:
US20080247213
Pub Dt:
10/09/2008
Title:
MEMORY DEVICE FOR PROTECTING MEMORY CELLS DURING PROGRAMMING
84
Patent #:
7499324
Issue Dt:
03/03/2009
Application #:
12143015
Filing Dt:
06/20/2008
Publication #:
US20080253185
Pub Dt:
10/16/2008
Title:
NON-VOLATILE MEMORY AND METHOD WITH CONTROL GATE COMPENSATION FOR SOURCE LINE BIAS ERRORS
85
Patent #:
7786015
Issue Dt:
08/31/2010
Application #:
12149151
Filing Dt:
04/28/2008
Publication #:
US20090269932
Pub Dt:
10/29/2009
Title:
METHOD FOR FABRICATING SELF-ALIGNED COMPLEMENTARY PILLAR STRUCTURES AND WIRING
86
Patent #:
7579232
Issue Dt:
08/25/2009
Application #:
12216924
Filing Dt:
07/11/2008
Title:
METHOD OF MAKING A NONVOLATILE MEMORY DEVICE INCLUDING FORMING A PILLAR SHAPED SEMICONDUCTOR DEVICE AND A SHADOW MASK
87
Patent #:
8143703
Issue Dt:
03/27/2012
Application #:
12291101
Filing Dt:
11/05/2008
Publication #:
US20090065764
Pub Dt:
03/12/2009
Title:
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
88
Patent #:
8084347
Issue Dt:
12/27/2011
Application #:
12318609
Filing Dt:
12/31/2008
Publication #:
US20100167520
Pub Dt:
07/01/2010
Title:
RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES
89
Patent #:
7825455
Issue Dt:
11/02/2010
Application #:
12320351
Filing Dt:
01/23/2009
Publication #:
US20090173985
Pub Dt:
07/09/2009
Title:
THREE TERMINAL NONVOLATILE MEMORY DEVICE WITH VERTICAL GATED DIODE
90
Patent #:
7928007
Issue Dt:
04/19/2011
Application #:
12363588
Filing Dt:
01/30/2009
Publication #:
US20090142921
Pub Dt:
06/04/2009
Title:
METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES
91
Patent #:
8530318
Issue Dt:
09/10/2013
Application #:
12410789
Filing Dt:
03/25/2009
Publication #:
US20090256131
Pub Dt:
10/15/2009
Title:
MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT FORMED OVER A BOTTOM CONDUCTOR AND METHODS OF FORMING THE SAME
92
Patent #:
7790562
Issue Dt:
09/07/2010
Application #:
12419637
Filing Dt:
04/07/2009
Publication #:
US20090233412
Pub Dt:
09/17/2009
Title:
METHOD FOR ANGULAR DOPING OF SOURCE AND DRAIN REGIONS FOR ODD AND EVEN NAND BLOCKS
93
Patent #:
8759176
Issue Dt:
06/24/2014
Application #:
12422072
Filing Dt:
04/10/2009
Publication #:
US20090224244
Pub Dt:
09/10/2009
Title:
PATTERNING OF SUBMICRON PILLARS IN A MEMORY ARRAY
94
Patent #:
7915163
Issue Dt:
03/29/2011
Application #:
12489214
Filing Dt:
06/22/2009
Publication #:
US20090258462
Pub Dt:
10/15/2009
Title:
METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS
95
Patent #:
8018769
Issue Dt:
09/13/2011
Application #:
12573405
Filing Dt:
10/05/2009
Publication #:
US20100020614
Pub Dt:
01/28/2010
Title:
NON-VOLATILE MEMORY WITH LINEAR ESTIMATION OF INITIAL PROGRAMMING VOLTAGE
96
Patent #:
8389399
Issue Dt:
03/05/2013
Application #:
12611087
Filing Dt:
11/02/2009
Publication #:
US20100044756
Pub Dt:
02/25/2010
Title:
METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE
97
Patent #:
NONE
Issue Dt:
Application #:
12709952
Filing Dt:
02/22/2010
Publication #:
US20110084377
Pub Dt:
04/14/2011
Title:
SYSTEM FOR SEPARATING A DICED SEMICONDUCTOR DIE FROM A DIE ATTACH TAPE
98
Patent #:
8481394
Issue Dt:
07/09/2013
Application #:
12717457
Filing Dt:
03/04/2010
Publication #:
US20110215320
Pub Dt:
09/08/2011
Title:
MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME
99
Patent #:
8114765
Issue Dt:
02/14/2012
Application #:
12754602
Filing Dt:
04/05/2010
Publication #:
US20100193916
Pub Dt:
08/05/2010
Title:
METHODS FOR INCREASED ARRAY FEATURE DENSITY
100
Patent #:
7960266
Issue Dt:
06/14/2011
Application #:
12791103
Filing Dt:
06/01/2010
Publication #:
US20100240182
Pub Dt:
09/23/2010
Title:
SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES
Assignor
1
SANDISK TECHNOLOGIES LLC
Exec Dt:
07/29/2021
Assignee
1
WODEN TECHNOLOGIES INC.
251 LITTLE FALLS DRIVE
WILMINGTON, DELAWARE 19808
Correspondence name and address
WODEN TECHNOLOGIES INC.
1891 ROBERTSON ROAD
SUITE 100
OTTAWA, K2H 5B7 CANADA

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