|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
09969313
|
Filing Dt:
|
10/01/2001
|
|
Title:
|
ARCHITECTURE FOR SYNCHRONIZING AND RESETTING CLOCK SIGNALS SUPPLIED TO MULTIPLE PROGRAMMABLE ANALOG BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
09972003
|
Filing Dt:
|
10/05/2001
|
|
Title:
|
TEST ARCHITECTURE FOR MICROCONTROLLER PROVIDING FOR A SERIAL COMMUNICATION INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
09983510
|
Filing Dt:
|
10/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
METHOD FOR ERASING A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
|
Application #:
|
09983511
|
Filing Dt:
|
10/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
STACK ELEMENT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
09988122
|
Filing Dt:
|
11/19/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
|
Title:
|
PROTECTIVE LAYER IN MEMORY DEVICE AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
09989571
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
METHOD FOR DESIGNING A CIRCUIT FOR PROGRAMMABLE MICROCONTROLLERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
09989762
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
SYSTEM AND METHOD FOR PERFORMING NEXT PLACEMENTS AND PRUNING OF DISALLOWED PLACEMENTS FOR PROGRAMMING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
09989775
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
USER DEFINED NAMES FOR REGISTERS IN MEMORY BANKS DERIVED FROM CONFIGURATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
09989808
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
AUTOMATIC GENERATION OF APPLICATION PROGRAM INTERFACES, SOURCE CODE, INTERRUPTS, AND DATASHEETS FOR MICROCONTROLLER PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
09989815
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
DATA DRIVEN METHOD AND SYSTEM FOR MONITORING HARDWARE RESOURCE USAGE FOR PROGRAMMING AN ELECTRONIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
09989816
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
DATASHEET BROWSING AND CREATION WITH DATA-DRIVEN DATASHEET TABS WITHIN A MICROCONTROLLER DESIGN TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
09989817
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
SYSTEM AND METHOD OF DYNAMICALLY RECONFIGURING A PROGRAMMABLE INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
09989819
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
SYSTEM AND METHOD FOR CREATING A BOOT FILE UTILIZING A BOOT TEMPLATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
09994599
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
AUTOMATIC APPLICATION PROGRAMMING INTERFACE (API) GENERATION FOR FUNCTIONAL BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
09994600
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
SYSTEM AND METHOD FOR DYNAMICALLY GENERATING A CONFIGURATION DATASHEET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
09998848
|
Filing Dt:
|
11/15/2001
|
|
Title:
|
DESIGN SYSTEM PROVIDING AUTOMATIC SOURCE CODE GENERATION FOR PERSONALIZATION AND PARAMETERIZATION OF USER MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
09999609
|
Filing Dt:
|
10/31/2001
|
|
Title:
|
METHOD AND SYSTEM FOR DATA-DRIVEN DISPLAY GRIDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09999869
|
Filing Dt:
|
10/23/2001
|
|
Title:
|
DRAIN SIDE SENSING SCHEME FOR VIRTUAL GROUND FLASH EPROM ARRAY WITH ADJACENT BIT CHARGE AND HOLD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
10002726
|
Filing Dt:
|
10/24/2001
|
|
Title:
|
METHOD AND APPARATUS FOR GENERATING MICROCONTROLLER CONFIGURATION INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10008548
|
Filing Dt:
|
11/09/2001
|
|
Title:
|
QUICK CLICK ICONS FOR WORKSPACE FLOW BETWEEN VIEWS FOR MAJOR SUBSYSTEMS AND VIEWS WITHIN A DESIGN TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
10010837
|
Filing Dt:
|
12/04/2001
|
|
Title:
|
BORDERLESS CONTACT ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10011214
|
Filing Dt:
|
10/25/2001
|
|
Title:
|
METHOD AND CIRCUIT FOR SYNCHRONIZING A WRITE OPERATION BETWEEN AN ON-CHIP MICROPROCESSOR AND AN ON-CHIP PROGRAMMABLE ANALOG DEVICE OPERATING AT DIFFERENT FREQUENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
10011696
|
Filing Dt:
|
12/05/2001
|
|
Title:
|
INTERFACE SCHEME FOR CONNECTING A FIXED CIRCUITRY BLOCK TO A PROGRAMMABLE LOGIC CORE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
10022119
|
Filing Dt:
|
12/13/2001
|
|
Title:
|
SELF REFERENCING 1T/1C FERROELECTRIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
10023278
|
Filing Dt:
|
12/20/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2003
| | | | |
|
Title:
|
REDUCING SECONDARY INJECTION EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
10023349
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
METHOD FOR REPAIRING DAMAGE TO CHARGE TRAPPING DIELECTRIC LAYER FROM BIT LINE IMPLANTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10023469
|
Filing Dt:
|
12/20/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2003
| | | | |
|
Title:
|
NROM NOR ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
10029371
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
CIRCUIT AND METHOD FOR REDUCING VOLTAGE STRESS IN A MEMORY DECODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10032986
|
Filing Dt:
|
10/29/2001
|
|
Title:
|
PIN-OUT CONNECTIONS/DRIVE LEVELS DIRECT-SET BY DROP DOWN LIST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10039469
|
Filing Dt:
|
11/08/2001
|
|
Title:
|
IN SITU DEPOSITION OF A NITRIDE LAYER AND OF AN ANTI-REFLECTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
10050254
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
NEGATIVE PUMP REGULATOR USING MOS CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
10050394
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
DIODE FABRICATION FOR ESD/EOS PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
10050650
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
10052484
|
Filing Dt:
|
01/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
METHOD AND DEVICE FOR READING DUAL BIT MEMORY CELLS USING MULTIPLE REFERENCE CELLS WITH TWO SIDE READ
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10053256
|
Filing Dt:
|
01/18/2002
|
|
Title:
|
TWO-STEP SOURCE SIDE IMPLANT FOR IMPROVING SOURCE RESISTANCE AND SHORT CHANNEL EFFECT IN DEEP SUB-0.18MUM FLASH MEMORY TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10072164
|
Filing Dt:
|
02/07/2002
|
|
Title:
|
DUAL-DAMASCENE PROCESS AND ASSOCIATED FLOATING METAL STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
10073570
|
Filing Dt:
|
02/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
DEVICE FOR PROCESSING DATA SIGNALS, METHOD THEREOF, AND DEVICE FOR MULTIPLEXING DATA SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
10081246
|
Filing Dt:
|
02/22/2002
|
|
Title:
|
DUMMY GATE PROCESS TO REDUCE THE VSS RESISTANCE OF FLASH PRODUCTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10083592
|
Filing Dt:
|
02/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/05/2002
| | | | |
|
Title:
|
DC-DC CONVERTER WITH CONTROL CIRCUIT CAPABLE OF GENERATING STEP-UP AND STEP-DOWN SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
10083789
|
Filing Dt:
|
02/27/2002
|
|
Title:
|
METHOD OF MATCHING CORE CELL AND REFERENCE CELL SOURCE RESISTANCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2003
|
Application #:
|
10087852
|
Filing Dt:
|
03/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2002
| | | | |
|
Title:
|
DC-DC CONVERTER, POWER SUPPLY CIRCUIT, METHOD FOR CONTROLLING DC-DC CONVERTER, AND METHOD FOR CONTROLLING POWER SUPPLY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
10090822
|
Filing Dt:
|
03/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10091767
|
Filing Dt:
|
03/07/2002
|
|
Title:
|
PASSWORD AND DYNAMIC PROTECTION OF FLASH MEMORY DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10097674
|
Filing Dt:
|
03/14/2002
|
|
Title:
|
POLY/SILICIDE STACK AND METHOD OF FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
10097924
|
Filing Dt:
|
03/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/18/2002
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY AND ITS USAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
10099499
|
Filing Dt:
|
03/13/2002
|
|
Title:
|
OVERERASE CORRECTION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10100485
|
Filing Dt:
|
03/14/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10109234
|
Filing Dt:
|
03/27/2002
|
|
Title:
|
LINER FOR SEMICONDUCTOR MEMORIES AND MANUFACTURING METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
10109235
|
Filing Dt:
|
03/27/2002
|
|
Title:
|
MEMORY WORDLINE HARD MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
10109516
|
Filing Dt:
|
03/27/2002
|
|
Title:
|
METHOD OF MAKING MEMORY WORDLINE HARD MASK EXTENSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10113107
|
Filing Dt:
|
03/29/2002
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING A BINARY DEMODULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10113180
|
Filing Dt:
|
03/29/2002
|
|
Title:
|
METHOD AND/OR APPARATUS FOR IMPLEMENTING SECURITY IN KEYBOARD-COMPUTER COMMUNICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
10114535
|
Filing Dt:
|
04/01/2002
|
|
Title:
|
FERROELECTRIC MEMORY WITH BIT-PLATE PARALLEL ARCHITECTURE AND OPERATING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10117818
|
Filing Dt:
|
04/08/2002
|
|
Title:
|
PRECISION HIGH-K INTERGATE DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10118682
|
Filing Dt:
|
04/08/2002
|
|
Title:
|
PINOUT VIEWS FOR ALLOWED CONNECTIONS IN GUI
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
10118732
|
Filing Dt:
|
04/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2003
| | | | |
|
Title:
|
MEMORY MANUFACTURING PROCESS WITH BITLINE ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10119273
|
Filing Dt:
|
04/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2003
| | | | |
|
Title:
|
REFRESH SCHEME FOR DYNAMIC PAGE PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10119366
|
Filing Dt:
|
04/08/2002
|
|
Title:
|
ERASE METHOD FOR A DUAL BIT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
10119391
|
Filing Dt:
|
04/08/2002
|
|
Title:
|
ALGORITHM DYNAMIC REFERENCE PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10119574
|
Filing Dt:
|
04/09/2002
|
|
Title:
|
METHODS OF FORMING SEMICONDUCTOR STRUCTURES, AND ARTICLES AND DEVICES FORMED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10124773
|
Filing Dt:
|
04/16/2002
|
|
Title:
|
HIDING REFRESH IN 1T-SRAM ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10126207
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
USING A FIRST LINER LAYER AS A SPACER IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10128771
|
Filing Dt:
|
04/22/2002
|
|
Title:
|
SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
10136034
|
Filing Dt:
|
04/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2003
| | | | |
|
Title:
|
SYSTEM FOR CONTROL OF PRE-CHARGE LEVELS IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10146560
|
Filing Dt:
|
05/15/2002
|
|
Title:
|
CIRCUIT FOR DRIVING A LASER DIODE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2003
|
Application #:
|
10150204
|
Filing Dt:
|
05/15/2002
|
|
Title:
|
SELF-ALIGNED POLYSILICON POLISH
|
|
|
|
|
Patent #:
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Issue Dt:
|
10/26/2004
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Application #:
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10150240
|
Filing Dt:
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05/15/2002
|
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Title:
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METHOD AND SYSTEM FOR TAILORING CORE AND PERIPHERY CELLS IN A NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
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Application #:
|
10150255
|
Filing Dt:
|
05/15/2002
|
|
Title:
|
METHOD AND SYSTEM FOR SCALING NONVOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10150677
|
Filing Dt:
|
05/17/2002
|
|
Title:
|
INTERMEDIATE FREQUENCY TUNER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
10155215
|
Filing Dt:
|
05/28/2002
|
|
Publication #:
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Pub Dt:
|
02/27/2003
| | | | |
|
Title:
|
EEPROM ARRAY AND METHOD FOR OPERATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10155216
|
Filing Dt:
|
05/28/2002
|
|
Publication #:
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|
Pub Dt:
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01/02/2003
| | | | |
|
Title:
|
PROGRAMMING AND ERASING METHODS FOR A NON -VOLATILE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10155217
|
Filing Dt:
|
05/28/2002
|
|
Publication #:
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Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
PROGRAMMING OF NONVOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10163970
|
Filing Dt:
|
06/06/2002
|
|
Title:
|
IN SITU HARD MASK APPROACH FOR SELF-ALIGNED CONTACT ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10164465
|
Filing Dt:
|
06/05/2002
|
|
Title:
|
USER MODULE PARAMETER AND REGISTER CONFIGURATION BLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10184336
|
Filing Dt:
|
06/26/2002
|
|
Title:
|
PROTECTION OF A LOW-K DIELECTRIC IN A PASSIVATION LEVEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10186466
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
STOCHASTIC PULSE GENERATOR DEVICE AND METHOD OF SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10189533
|
Filing Dt:
|
07/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
|
Title:
|
PROTECTIVE LAYER IN MEMORY DEVICE AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10190002
|
Filing Dt:
|
07/03/2002
|
|
Title:
|
METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY ISOLATION MATERIAL GROWTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10191451
|
Filing Dt:
|
07/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
MULTIPLE USE MEMORY CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
10194270
|
Filing Dt:
|
07/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
SUBSTRATE ISOLATED TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10197116
|
Filing Dt:
|
07/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
SYSTEM FOR USING A DYNAMIC REFERENCE IN A DOUBLE-BIT CELL MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10198508
|
Filing Dt:
|
07/17/2002
|
|
Title:
|
CONTROL TRANSACTION HANDLING IN A DEVICE CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
10200330
|
Filing Dt:
|
07/22/2002
|
|
Title:
|
ON-CHIP ERASE PULSE COUNTER FOR EFFICIENT ERASE VERIFY BIST (BUILT-IN-SELF-TEST) MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
10200396
|
Filing Dt:
|
07/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
PROCESS FOR ANNEALING SEMICONDUCTORS AND/OR INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2003
|
Application #:
|
10200544
|
Filing Dt:
|
07/22/2002
|
|
Title:
|
ON-CHIP REPAIR OF DEFECTIVE ADDRESS OF CORE FLASH MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10205414
|
Filing Dt:
|
07/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND LIQUID CRYSTAL PANEL DRIVER DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10209644
|
Filing Dt:
|
08/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
HIGH VOLTAGE INSERTION IN FLASH MEMORY CARDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10209645
|
Filing Dt:
|
08/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
DEFECTS DETECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10210279
|
Filing Dt:
|
08/01/2002
|
|
Title:
|
INPUT GATE PROTECTION CIRCUIT AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10210378
|
Filing Dt:
|
07/31/2002
|
|
Title:
|
SYSTEM AND METHOD FOR ERASE VOLTAGE CONTROL DURING MULTIPLE SECTOR ERASE OF A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10211234
|
Filing Dt:
|
08/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
|
Title:
|
LOOK AHEAD METHODS AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10211235
|
Filing Dt:
|
08/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
|
Title:
|
MASS STORAGE DEVICE ARCHITECTURE AND OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10211248
|
Filing Dt:
|
08/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
|
Title:
|
METHOD FOR OPERATING A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10211249
|
Filing Dt:
|
08/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
|
Title:
|
MASS STORAGE ARRAY AND METHODS FOR OPERATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
10217403
|
Filing Dt:
|
08/14/2002
|
|
Title:
|
REFLOWABLE-DOPED HDP FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10217821
|
Filing Dt:
|
08/12/2002
|
|
Title:
|
SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
10222155
|
Filing Dt:
|
08/16/2002
|
|
Title:
|
APPARATUS, SYSTEM AND METHOD FOR SHARING DATA FROM A DEVICE BETWEEN MULTIPLE COMPUTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10223920
|
Filing Dt:
|
08/20/2002
|
|
Title:
|
MEMORY DEVICE AND METHOD OF MAKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2009
|
Application #:
|
10225658
|
Filing Dt:
|
08/21/2002
|
|
Title:
|
DIFFERENTIAL CRYSTAL OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10226778
|
Filing Dt:
|
08/23/2002
|
|
Title:
|
SYSTEM AND METHOD FOR DATA TRANSFORMATION OF DEVICE DATABASES FOR FORWARD COMPATIBILITY
|
|
