|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10656251
|
Filing Dt:
|
09/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
METHOD FOR ERASING A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10658428
|
Filing Dt:
|
09/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY ENABLING CORRECT SUBSTITUTION OF REDUNDANT CELL ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10662535
|
Filing Dt:
|
09/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
|
Title:
|
READING ARRAY CELL WITH MATCHED REFERENCE CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10672093
|
Filing Dt:
|
09/26/2003
|
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10677031
|
Filing Dt:
|
10/01/2003
|
|
Title:
|
MEMORY DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
10677073
|
Filing Dt:
|
10/01/2003
|
|
Title:
|
MEMORY DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10677790
|
Filing Dt:
|
10/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
|
Title:
|
MEMORY DEVICE AND METHOD USING POSITIVE GATE STRESS TO RECOVER OVERERASED CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10678446
|
Filing Dt:
|
10/03/2003
|
|
Title:
|
EFFICIENT AND ACCURATE SENSING CIRCUIT AND TECHNIQUE FOR LOW VOLTAGE FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10689054
|
Filing Dt:
|
10/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
CLASS AB VOLTAGE REGULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10695448
|
Filing Dt:
|
10/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
METHOD CIRCUIT AND SYSTEM FOR DETERMINING A REFERENCE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
10695449
|
Filing Dt:
|
10/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
METHOD, SYSTEM AND CIRCUIT FOR PROGRAMMING A NON-VOLATILE MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10695457
|
Filing Dt:
|
10/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
METHOD CIRCUIT AND SYSTEM FOR READ ERROR DETECTION IN A NON-VOLATILE MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10699903
|
Filing Dt:
|
11/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
SIDEWALL FORMATION FOR HIGH DENSITY POLYMER MEMORY ELEMENT ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10701780
|
Filing Dt:
|
11/05/2003
|
|
Title:
|
METHOD AND STRUCTURE FOR PROTECTING NROM DEVICES FROM INDUCED CHARGE DAMAGE DURING DEVICE FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10708379
|
Filing Dt:
|
02/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR IMPROVING CYCLE TIME IN A QUAD DATA RATE SRAM DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10715366
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
MEMORY CONTROL CIRCUIT, MEMORY DEVICE, AND MICROCOMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10717622
|
Filing Dt:
|
11/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE STORING TWO-BIT INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10719108
|
Filing Dt:
|
11/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
IMPRINT-FREE CODING FOR FERROELECTRIC NONVOLATILE COUNTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10721643
|
Filing Dt:
|
11/24/2003
|
|
Title:
|
READING FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10729732
|
Filing Dt:
|
12/05/2003
|
|
Title:
|
HARD MASK SPACER FOR SUBLITHOGRAPHIC BITLINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10731659
|
Filing Dt:
|
12/09/2003
|
|
Title:
|
PROCESS FOR FABRICATION OF NITRIDE LAYER WITH REDUCED HYDROGEN CONTENT IN ONO STRUCTURE IN SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
10738301
|
Filing Dt:
|
12/16/2003
|
|
Title:
|
METHOD AND DEVICE FOR PROGRAMMING CELLS IN A MEMORY ARRAY IN A NARROW DISTRIBUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10740616
|
Filing Dt:
|
12/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/08/2004
| | | | |
|
Title:
|
CHARGE PUMP STAGE WITH BODY EFFECT MINIMIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10747217
|
Filing Dt:
|
12/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
|
Title:
|
METHOD FOR OPERATING A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10758173
|
Filing Dt:
|
01/14/2004
|
|
Title:
|
ELECTROSTATIC DISCHARGE PERFORMANCE OF A SILICON STRUCTURE AND EFFICIENT USE OF AREA WITH ELECTROSTATIC DISCHARGE PROTECTIVE DEVICE UNDER THE PAD APPROACH AND ADJUSTMENT OF VIA CONFIGURATION THERETO TO CONTROL DRAIN JUNCTION RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10759855
|
Filing Dt:
|
01/16/2004
|
|
Title:
|
FLEXIBLE CASCODE AMPLIFIER CIRCUIT WITH HIGH GAIN FOR FLASH MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10762071
|
Filing Dt:
|
01/20/2004
|
|
Title:
|
METHOD FOR ERASING A MEMORY SECTOR IN VIRTUAL GROUND ARCHITECTURE WITH REDUCED LEAKAGE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10762445
|
Filing Dt:
|
01/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
|
Title:
|
STRUCTURE AND METHOD FOR LOW VSS RESISTANCE AND REDUCED DIBL IN A FLOATING GATE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10768188
|
Filing Dt:
|
02/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10770245
|
Filing Dt:
|
02/02/2004
|
|
Title:
|
DISPOSABLE HARD MASK FOR MEMORY BITLINE SCALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10770260
|
Filing Dt:
|
02/02/2004
|
|
Title:
|
FLASH MEMORY CELL WITH UV PROTECTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10770673
|
Filing Dt:
|
02/02/2004
|
|
Title:
|
BITLINE HARD MASK SPACER FLOW FOR MEMORY CELL SCALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10773816
|
Filing Dt:
|
02/06/2004
|
|
Title:
|
VARIABLE IMPEDANCE OUTPUT DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10774806
|
Filing Dt:
|
02/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
|
Title:
|
HIGH VOLTAGE LOW POWER DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
10775668
|
Filing Dt:
|
02/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
|
Title:
|
ENCODING SCHEME FOR DATA TRANSFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10785599
|
Filing Dt:
|
02/24/2004
|
|
Title:
|
POWER SUPPLY DETECTING INPUT RECEIVER CIRCUIT AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10798657
|
Filing Dt:
|
03/11/2004
|
|
Title:
|
LOW DUTY CYCLE DISTORTION DIFFERENTIAL TO CMOS TRANSLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10803011
|
Filing Dt:
|
03/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
LATCH CIRCUIT AND METHOD FOR WRITING AND READING VOLATILE AND NON-VOLATILE DATA TO AND FROM THE LATCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10807909
|
Filing Dt:
|
03/24/2004
|
|
Title:
|
PROTECTION OF INTEGRATED CIRCUIT GATES DURING METALLIZATION PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10808532
|
Filing Dt:
|
03/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT USING BAND-GAP REFERENCE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10810683
|
Filing Dt:
|
03/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
APPARATUS AND METHODS FOR MULTI-LEVEL SENSING IN A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
10817186
|
Filing Dt:
|
04/02/2004
|
|
Title:
|
USING ORGANIC SEMICONDUCTOR MEMORY IN CONJUNCTION WITH A MEMS ACTUATOR FOR AN ULTRA HIGH DENSITY MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10821312
|
Filing Dt:
|
04/08/2004
|
|
Title:
|
NARROW WIDE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
10823970
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A PAD METAL LAYER AND A LOWER METAL LAYER THAT ARE ELECTRICALLY COUPLED, WHEREAS APERTURES ARE FORMED IN THE LOWER METAL LAYER BELOW A CENTER AREA OF THE PAD METAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
10826375
|
Filing Dt:
|
04/19/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
|
Title:
|
METHOD FOR READING A MEMORY ARRAY WITH NEIGHBOR EFFECT CANCELLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10827785
|
Filing Dt:
|
04/19/2004
|
|
Title:
|
CURRENT SOURCE ARCHITECTURE FOR MEMORY DEVICE STANDBY CURRENT REDUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10835341
|
Filing Dt:
|
04/28/2004
|
|
Title:
|
METHOD FOR PROVIDING SHORT CHANNEL EFFECT CONTROL USING A SILICIDE VSS LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
10838962
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
METHOD FOR MINIMIZING FALSE DETECTION OF STATES IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10839561
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
METHOD AND APPARATUS FOR ELIMINATING WORD LINE BENDING BY SOURCE SIDE IMPLANTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10839562
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
POSITIVE GATE STRESS DURING ERASE TO IMPROVE RETENTION IN MULTI-LEVEL, NON-VOLATILE FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10839614
|
Filing Dt:
|
05/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR WORDLINE PROTECTION IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10839626
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
MEMORY ARRAY WITH MEMORY CELLS HAVING REDUCED SHORT CHANNEL EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10841933
|
Filing Dt:
|
05/06/2004
|
|
Title:
|
STRUCTURE AND METHOD FOR PROTECTING MEMORY CELLS FROM UV RADIATION DAMAGE AND UV RADIATION-INDUCED CHARGING DURING BACKEND PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10843289
|
Filing Dt:
|
05/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
|
Title:
|
BITLINE IMPLANT UTILIZING DUAL POLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10844116
|
Filing Dt:
|
05/12/2004
|
|
Title:
|
CASCODE AMPLIFIER CIRCUIT FOR GENERATING AND MAINTAINING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
10849958
|
Filing Dt:
|
05/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
OPERATION MODE CONTROL CIRCUIT, MICROCOMPUTER INCLUDING THE SAME, AND CONTROL SYSTEM USING THE MICROCOMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10850286
|
Filing Dt:
|
05/19/2004
|
|
Title:
|
A USB PERIPHERAL DEVICE STORING AN INDICATION OF AN OPERATING POWER MODE WHEN A HOST WENT INTO HIBERNATE AND RESTARTING AT THE POWER MODE ACCORDINGLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10857039
|
Filing Dt:
|
05/28/2004
|
|
Title:
|
POWER ON RESET CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10860450
|
Filing Dt:
|
06/03/2004
|
|
Title:
|
METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10861575
|
Filing Dt:
|
06/04/2004
|
|
Title:
|
METHOD AND SYSTEM FOR IMPROVING THE TOPOGRAPHY OF A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
10861581
|
Filing Dt:
|
06/04/2004
|
|
Title:
|
Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
10861714
|
Filing Dt:
|
06/04/2004
|
|
Title:
|
BALL GRID ARRAY PACKAGE HAVING INTEGRATED ANTENNA PAD
|
|
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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10862401
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Filing Dt:
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06/08/2004
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Publication #:
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Pub Dt:
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12/08/2005
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Title:
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POWER-UP AND BGREF CIRCUITRY
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|
|
|
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Patent #:
|
|
Issue Dt:
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03/06/2007
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Application #:
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10862404
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Filing Dt:
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06/08/2004
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Publication #:
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Pub Dt:
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02/23/2006
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Title:
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REPLENISHMENT FOR INTERNAL VOLTAGE
|
|
|
|
|
Patent #:
|
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Issue Dt:
|
02/13/2007
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Application #:
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10862636
|
Filing Dt:
|
06/07/2004
|
|
Title:
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LDC IMPLANT FOR MIRRORBIT TO IMPROVE VT ROLL-OFF AND FORM SHARPER JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
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Application #:
|
10864500
|
Filing Dt:
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06/10/2004
|
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Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
REDUCED POWER PROGRAMMING OF NON-VOLATILE CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10864947
|
Filing Dt:
|
06/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
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Title:
|
ERASE ALGORITHM FOR MULTI-LEVEL BIT FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10869286
|
Filing Dt:
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06/16/2004
|
|
Title:
|
ALIGNMENT MARKS WITH SALICIDED SPACERS BETWEEN BITLINES FOR ALIGNMENT SIGNAL IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10869774
|
Filing Dt:
|
06/16/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH CORE AND PERIPHERY REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10871825
|
Filing Dt:
|
06/18/2004
|
|
Title:
|
MEMORY INTERFACE SYSTEM AND METHOD FOR REDUCING CYCLE TIME OF SEQUENTIAL READ AND WRITE ACCESSES USING SEPARATE ADDRESS AND DATA BUSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10877296
|
Filing Dt:
|
06/24/2004
|
|
Title:
|
BINDING FOR ONE-WAY WIRELESS TRANSMISSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
10877313
|
Filing Dt:
|
06/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
MEMORY CELL ARRAY LATCHUP PREVENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
10877932
|
Filing Dt:
|
06/25/2004
|
|
Title:
|
CONFIGURABLE DATA PATH ARCHITECTURE AND CLOCKING SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10889245
|
Filing Dt:
|
07/12/2004
|
|
Title:
|
POWER ON RESET CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
10896292
|
Filing Dt:
|
07/20/2004
|
|
Title:
|
APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10896299
|
Filing Dt:
|
07/20/2004
|
|
Title:
|
METHOD FOR PROGRAMMING DUAL BIT MEMORY DEVICES TO REDUCE COMPLEMENTARY BIT DISTURBANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10899072
|
Filing Dt:
|
07/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
SERIAL COMMUNICATION DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10899344
|
Filing Dt:
|
07/26/2004
|
|
Title:
|
THREE DIMENSIONAL POLYMER MEMORY CELL SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10909693
|
Filing Dt:
|
08/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
|
Title:
|
FLASH MEMORY UNIT AND METHOD OF PROGRAMMING A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
10916167
|
Filing Dt:
|
08/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
|
Title:
|
METHOD OF FORMING NARROWLY SPACED FLASH MEMORY CONTACT OPENINGS AND LITHOGRAPHY MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10917562
|
Filing Dt:
|
08/13/2004
|
|
Title:
|
USING THIN UNDOPED TEOS WITH BPTEOS ILD OR BPTEOS ILD ALONE TO IMPROVE CHARGE LOSS AND CONTACT RESISTANCE IN MULTI BIT MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
10927365
|
Filing Dt:
|
08/26/2004
|
|
Title:
|
METHOD OF REDUCING STEP HEIGHT DIFFERENCE BETWEEN DOPED REGIONS OF FIELD OXIDE IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10927583
|
Filing Dt:
|
08/26/2004
|
|
Title:
|
MEMORY ARRAY WITH CURRENT LIMITING DEVICE FOR PREVENTING PARTICLE INDUCED LATCH-UP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
10936275
|
Filing Dt:
|
09/08/2004
|
|
Title:
|
METHOD FOR REDUCING SOFT ERROR RATES OF MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10939897
|
Filing Dt:
|
09/13/2004
|
|
Title:
|
METHOD OF FORMING COPPER SULFIDE LAYER OVER SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10941753
|
Filing Dt:
|
09/15/2004
|
|
Title:
|
LOW VOLTAGE LOGIC CIRCUIT WITH SET AND/OR RESET FUNCTIONALITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10945914
|
Filing Dt:
|
09/22/2004
|
|
Title:
|
METHODS AND SYSTEMS FOR REDUCING ERASE TIMES IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10946809
|
Filing Dt:
|
09/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
|
Title:
|
READ APPROACH FOR MULTI-LEVEL VIRTUAL GROUND MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10947538
|
Filing Dt:
|
09/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND MICROCONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10948524
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
|
Title:
|
LEVEL CONVERSION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
10949093
|
Filing Dt:
|
09/23/2004
|
|
Title:
|
MAPPING OF NON-ISOCHRONOUS AND ISOCHRONOUS CHANNELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10949176
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
|
Title:
|
NONVOLATILE PROGRAMMABLE CRYSTAL OSCILLATOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
10950332
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
OXIDE-NITRIDE STACK GATE DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
10958044
|
Filing Dt:
|
10/04/2004
|
|
Title:
|
MEMORY DEVICE WITH A SELF-ASSEMBLED POLYMER FILM AND METHOD OF MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
10961398
|
Filing Dt:
|
10/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2008
| | | | |
|
Title:
|
NROM FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10968713
|
Filing Dt:
|
10/19/2004
|
|
Title:
|
PATTERNING FOR ELONGATED VSS CONTACT FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10973257
|
Filing Dt:
|
10/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
CONTROL CIRCUIT OF DC-DC CONVERTER AND ITS CONTROL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10976816
|
Filing Dt:
|
11/01/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR PROTECTING SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10978045
|
Filing Dt:
|
10/29/2004
|
|
Title:
|
VARIABLE CAPACITANCE CHARGE PUMP SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10979516
|
Filing Dt:
|
11/02/2004
|
|
Title:
|
METHOD OF MAKING A MEMORY CELL
|
|
