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Patent #:
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Issue Dt:
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05/05/1992
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Application #:
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07576182
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Filing Dt:
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08/30/1990
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Title:
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APPARATUS FOR ISOLATION OF FLUX MATERIALS IN "FLIP-CHIP" MANUFACTURING
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Patent #:
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Issue Dt:
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12/01/1992
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Application #:
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07775009
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Filing Dt:
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10/11/1991
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Title:
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METHOD AND APPARATUS FOR ISOLATION OF FLUX MATERIALS IN FLIP-CHIP MANUFACTURING
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Patent #:
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Issue Dt:
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11/16/1993
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Application #:
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07834182
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Filing Dt:
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02/07/1992
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Title:
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PARTIALLY-MOLDED, PCB CHIP CARRIER PACKAGE
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Patent #:
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Issue Dt:
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08/16/1994
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Application #:
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07911846
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Filing Dt:
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07/10/1992
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Title:
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METHOD AND APPARATUS FOR INTERIM, IN-SITU TESTING OF AN ELECTRONIC SYSTEM WITH AN INCHOATE ASIC
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Patent #:
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Issue Dt:
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08/23/1994
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Application #:
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07916328
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Filing Dt:
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07/17/1992
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Title:
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METHOD OF INCREASING THE LAYOUT EFFICIENCY OF DIES ON A WAFER AND INCREASING THE RATIO OF I/O AREA TO ACTIVE AREA PER DIE
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Patent #:
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Issue Dt:
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07/12/1994
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Application #:
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07933430
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Filing Dt:
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08/21/1992
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Title:
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SEMICONDUCTOR PACKAGING TECHNIQUE YIELDING INCREASED INNER LEAD COUNT FOR A GIVEN DIE-RECEIVING AREA
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Patent #:
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Issue Dt:
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04/05/1994
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Application #:
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07935449
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Filing Dt:
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08/25/1992
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Title:
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TECHNIQUE OF INCREASING BOND PAD DENSITY ON A SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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05/13/1997
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Application #:
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07937643
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Filing Dt:
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08/31/1992
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Title:
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METHOD AND APPARATUS FOR INTERIM IN-SITU TESTING OF AN ELECTRONIC SYSTEM WITH AN INCHOATE ASIC
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Patent #:
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Issue Dt:
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09/28/1993
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Application #:
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07947854
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Filing Dt:
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09/18/1992
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Title:
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COMPOSITE BOND PADS FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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03/21/1995
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Application #:
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07975185
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Filing Dt:
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11/12/1992
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Title:
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MULTI-CHIP SEMICONDUCTOR ARRANGEMENTS USING FLIP CHIP DIES
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Patent #:
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Issue Dt:
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08/23/1994
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Application #:
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07978483
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Filing Dt:
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11/18/1992
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Title:
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METHOD OF INCREASING THE LAYOUT EFFICIENCY OF DIES ON A WAFER, AND INCREASING THE RATIO OF I/O AREA TO ACTIVE AREA PER DIE
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Patent #:
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Issue Dt:
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09/09/1997
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Application #:
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07980492
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Filing Dt:
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11/23/1992
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Title:
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FLEXIBLE DESIGN SYSTEM
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Patent #:
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Issue Dt:
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04/05/1994
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Application #:
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07981096
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Filing Dt:
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11/24/1992
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Title:
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METHOD AND APPARATUS FOR ISOLATION OF FLUX MATERIALS IN FLIP-CHIP MANUFACTURING
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Patent #:
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Issue Dt:
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02/08/1994
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Application #:
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07984206
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Filing Dt:
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11/30/1992
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Title:
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SEMICONDUCTOR BOND PADS
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Patent #:
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Issue Dt:
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04/04/1995
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Application #:
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07995644
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Filing Dt:
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12/18/1992
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Title:
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SEMICONDUCTOR DIE HAVING A HIGH DENSITY ARRAY OF COMPOSITE BOND PADS
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Patent #:
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Issue Dt:
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07/18/1995
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Application #:
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08079499
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Filing Dt:
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06/18/1993
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Title:
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PARTIALLY-MOLDED, PCB CHIP CARRIER PACKAGE FOR CERTAIN NON-SQUARE DIE SHAPES
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Patent #:
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Issue Dt:
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04/02/1996
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Application #:
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08105547
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Filing Dt:
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08/12/1993
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Title:
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PROCESS FOR SOLDER BALL INTERCONNECTING A SEMICONDUCTOR DEVICE TO A SUBSTRATE USING A NOBLE METAL FOIL EMBEDDED INTERPOSER SUBSTRATE
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Patent #:
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Issue Dt:
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09/13/1994
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Application #:
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08105838
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Filing Dt:
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08/12/1993
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Title:
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PREFORMED PLANAR STRUCTURES EMPLOYING EMBEDDED CONDUCTORS
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Patent #:
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Issue Dt:
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02/06/1996
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Application #:
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08106157
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Filing Dt:
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08/12/1993
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Title:
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FLEXIBLE PREFORMED PLANAR STRUCTURES FOR INTERPOSING BETWEEN A CHIP AND A SUBSTRATE
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Patent #:
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Issue Dt:
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05/02/1995
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Application #:
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08194241
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Filing Dt:
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02/10/1994
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Title:
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METHOD AND APPARATUS FOR ISOLATION OF FLUX MATERIALS IN "FLIP-CHIP" MANUFACTURING
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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08229616
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Filing Dt:
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04/19/1994
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Title:
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OPTIMIZATION PROCESSING FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM USING OPTIMALLY SWITCHED FITNESS IMPROVEMENT ALGORITHMS
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08229624
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Filing Dt:
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04/19/1994
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Title:
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CONGESTION BASED COST FACTOR COMPUTING APPARATUS FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM
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Patent #:
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Issue Dt:
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09/17/1996
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Application #:
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08229821
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Filing Dt:
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04/19/1994
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Title:
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CELL PLACEMENT ALTERATION APPARATUS FOR INTEGRATED CIRCUIT CHIP PHYSICAL DESIGN AUTOMATION SYSTEM
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Patent #:
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Issue Dt:
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02/27/1996
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Application #:
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08229826
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Filing Dt:
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04/19/1994
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Title:
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INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM UTILIZING OPTIMIZATION PROCESS DECOMPOSITION AND PARALLEL PROCESSING
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Patent #:
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Issue Dt:
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10/28/1997
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Application #:
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08229949
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Filing Dt:
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04/19/1994
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Title:
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OPTIMIZATION PROCESSING FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM USING CHAOTIC FITNESS IMPROVEMENT METHOD
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Patent #:
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Issue Dt:
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09/29/1998
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Application #:
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08229954
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Filing Dt:
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04/19/1994
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Title:
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FAIL-SAFE DISTRIBUTIVE PROCESSING METHOD FOR PRODUCING A HIGHEST FITNESS CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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08230383
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Filing Dt:
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04/19/1994
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Title:
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CELL PLACEMENT REPRESENTATION AND TRANSPOSITION FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM
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Patent #:
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Issue Dt:
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12/24/1996
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Application #:
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08233791
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Filing Dt:
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04/22/1994
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Title:
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APPARATUS AND METHOD FOR LOGIC OPTIMIZATION BY REDUNDANCY ADDITION AND REMOVAL
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Patent #:
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Issue Dt:
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10/17/1995
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Application #:
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08242246
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Filing Dt:
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05/13/1994
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Title:
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GATE ARRAY LAYOUT TO ACCOMMODATE MULTI ANGLE ION IMPLANTATION
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Patent #:
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Issue Dt:
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08/15/1995
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Application #:
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08251058
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Filing Dt:
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05/31/1994
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Title:
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METHOD OF LAYING OUT BOND PADS ON A SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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02/20/1996
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Application #:
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08252231
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Filing Dt:
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06/01/1994
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Title:
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SPECIFICATION AND DESIGN OF COMPLEX DIGITAL SYSTEMS
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Patent #:
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Issue Dt:
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04/30/1996
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Application #:
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08254218
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Filing Dt:
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06/06/1994
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Title:
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METHOD AND APPARATUS FOR DETERMINING THE REACHABLE STATES IN A HYBRID MODEL STATE MACHINE
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Patent #:
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Issue Dt:
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11/21/1995
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Application #:
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08260078
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Filing Dt:
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06/15/1994
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Title:
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PROCESS FOR INTERCONNECTING CONDUCTIVE SUBSTRATES USING AN INTERPOSER HAVING CONDUCTIVE PLASTIC FILLED VIAS
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Patent #:
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Issue Dt:
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04/22/1997
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Application #:
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08267109
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Filing Dt:
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06/27/1994
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Title:
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METHOD AND APPARATUS FOR GENERATING CONFORMANCE TEST DATA SEQUENCES
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Patent #:
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Issue Dt:
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10/22/1996
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Application #:
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08268920
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Filing Dt:
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06/29/1994
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Title:
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MODELING AND ESTIMATING CROSSTALK NOISE AND DETECTING FALSE LOGIC
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Patent #:
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Issue Dt:
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07/16/1996
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Application #:
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08269230
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Filing Dt:
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06/30/1994
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Title:
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APPARATUS AND METHOD FOR ANALYZING CIRCUITS
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Patent #:
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Issue Dt:
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03/25/1997
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Application #:
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08294973
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Filing Dt:
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08/24/1994
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Title:
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HIGH-SPEED INTERNAL INTERCONNECTION TECHNIQUE FOR INTEGRATED CIRCUITS THAT REDUCES THE NUMBER OF SIGNAL LINES THROUGH MULTIPLEXING
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Patent #:
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Issue Dt:
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06/10/1997
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Application #:
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08295094
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Filing Dt:
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08/24/1994
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Title:
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SEPARABLE CELLS HAVING WIRING CHANNELS FOR ROUTING SIGNALS BETWEEN SURROUNDING CELLS
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Patent #:
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Issue Dt:
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12/24/1996
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Application #:
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08301687
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Filing Dt:
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09/07/1994
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Title:
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METHOD FOR ESTIMATING ROUTABILITY AND CONGESTION IN A CELL PLACEMENT FOR INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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10/15/1996
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Application #:
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08306088
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Filing Dt:
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09/14/1994
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Title:
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METHOD FOR IDENTIFYING UNTESTABLE FAULTS IN LOGIC CIRCUITS
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Patent #:
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Issue Dt:
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04/08/1997
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Application #:
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08306182
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Filing Dt:
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09/13/1994
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Title:
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METHOD OF CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP COMPRISING CHAOTIC PLACEMENT AND CELL OVERLAP REMOVAL
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Patent #:
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Issue Dt:
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06/10/1997
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Application #:
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08306189
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Filing Dt:
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09/13/1994
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Title:
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OPTIMAL PAD LOCATION METHOD FOR MICROELECTRONIC CIRCUIT CELL PLACEMENT
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Patent #:
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Issue Dt:
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10/22/1996
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Application #:
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08306385
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Filing Dt:
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09/13/1994
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Title:
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METHOD AND SYSTEM FOR IMPROVING A PLACEMENT OF CELLS USING ENERGETIC PLACEMENT WITH ALTERNATING CONTRACTION AND EXPANSION OPERATIONS
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Patent #:
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Issue Dt:
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09/03/1996
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Application #:
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08307942
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Filing Dt:
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09/16/1994
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Title:
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METHOD FOR DESIGNING LOW PROFILE VARIABLE WIDTH INPUT/OUTPUT CELLS
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Patent #:
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Issue Dt:
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10/28/1997
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Application #:
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08318275
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Filing Dt:
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10/05/1994
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Title:
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CELL PLACEMENT METHOD FOR MICROELECTRONIC INTEGRATED CIRCUIT COMBINING CLUSTERING, CLUSTER PLACEMENT AND DE-CLUSTERING
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Patent #:
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Issue Dt:
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02/25/1997
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Application #:
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08327338
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Filing Dt:
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10/21/1994
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Title:
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DELAY TESTING OF HIGH-PERFORMANCE DIGITAL COMPONENTS BY A SLOW-SPEED TESTER
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Patent #:
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Issue Dt:
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11/26/1996
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Application #:
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08333367
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Filing Dt:
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11/02/1994
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT STRUCTURE AND METHOD USING THREE DIRECTIONAL INTERCONNECT ROUTING BASED ON HEXAGONAL GEOMETRY
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Patent #:
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Issue Dt:
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12/05/1995
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Application #:
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08365264
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Filing Dt:
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12/28/1994
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Title:
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METHOD AND APPARATUS FOR TESTING LARGE EMBEDDED COUNTERS
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Patent #:
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Issue Dt:
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04/30/1996
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Application #:
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08365394
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Filing Dt:
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12/28/1994
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Title:
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METHOD FOR BUILT-IN SELF-TESTING OF RING-ADDRESS FIFOS
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Patent #:
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Issue Dt:
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09/09/1997
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Application #:
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08367556
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Filing Dt:
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01/03/1995
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Title:
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PROGRAMMABLE MICROSYSTEMS IN SILICON
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Patent #:
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Issue Dt:
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07/01/1997
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Application #:
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08377844
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Filing Dt:
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01/25/1995
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Title:
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TIMING SHELL GENERATION THROUGH NETLIST REDUCTION
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Patent #:
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Issue Dt:
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01/02/1996
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Application #:
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08378435
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Filing Dt:
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01/26/1995
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Title:
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METHOD AND APPARATUS FOR TESTING LONG COUNTERS
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Patent #:
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Issue Dt:
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10/15/1996
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Application #:
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08387154
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Filing Dt:
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02/10/1995
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Title:
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SEMICONDUCTOR BOND PAD STRUCTURE AND INCREASED BOND PAD COUNT PER DIE
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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08396541
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Filing Dt:
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03/01/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING HEXAGONAL CMOS "NAND" GATE DEVICE
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Patent #:
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Issue Dt:
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10/28/1997
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Application #:
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08401099
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Filing Dt:
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03/06/1995
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Title:
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SYSTEM AND METHOD FOR PERFORMING OPTICAL PROXIMITY CORRECTION ON MACROCELL LIBRARIES
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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08409191
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Filing Dt:
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03/23/1995
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Title:
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SYNTHESIS SHELL GENRATION AND USE IN ASIC DESIGN
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Patent #:
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Issue Dt:
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08/26/1997
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Application #:
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08409757
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Filing Dt:
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03/24/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND METHOD USING HIERARCHICAL CLUSTERIZATION AND PLACEMENT IMPROVEMENT BASED ON COMPLETE RE-PLACEMENT OF CELL CLUSTERS
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Patent #:
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Issue Dt:
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07/02/1996
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Application #:
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08416457
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Filing Dt:
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04/03/1995
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Title:
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FLOORPLANNING TECHNIQUE USING MULTI-PARTITIONING BASED ON A PARTITION COST FACTOR FOR NON-SQUARE SHAPED PARTITONS
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Patent #:
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Issue Dt:
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10/29/1996
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Application #:
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08428323
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Filing Dt:
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04/25/1995
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Title:
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PREFORMED PLANAR STRUCTURES FOR SEMICONDUCTOR DEVICE ASSEMBLIES
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Patent #:
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Issue Dt:
|
09/17/1996
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Application #:
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08429605
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Filing Dt:
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04/27/1995
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Title:
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OVERMOLDED SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
|
06/03/1997
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Application #:
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08430399
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Filing Dt:
|
04/28/1995
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Title:
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HIGH DENSITY BOND PAD LAYOUT ARRANGEMENTS FIR SEMICONDUCTOR DIES, AND CONNECTING TO THE BOND PADS
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Patent #:
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Issue Dt:
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01/14/1997
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Application #:
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08432535
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Filing Dt:
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05/02/1995
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Title:
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PARTIALLY-MOLDED, PCB CHIP CARRIER PACKAGE FOR CERTAIN NON-SQUARE DIE SHAPES
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Patent #:
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Issue Dt:
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04/08/1997
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Application #:
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08434660
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Filing Dt:
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05/04/1995
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Title:
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SEMICONDUCTOR CELL HAVING A VARIABLE TRANSISTOR WIDTH
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Patent #:
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Issue Dt:
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06/16/1998
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Application #:
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08441539
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Filing Dt:
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05/15/1995
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Title:
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METHOD OF CALCULATING MACROCELL POWER AND DELAY VALUES
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Patent #:
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Issue Dt:
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04/27/1999
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Application #:
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08451177
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Filing Dt:
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05/26/1995
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Title:
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AUTOMATED GENERATION OF MEGACELLS IN AN INTEGRATED CIRCUIT DESIGN SYSTEM
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08470945
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Filing Dt:
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06/05/1995
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Title:
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SEMICONDUCTOR DEVICE ASSEMBLY TECHNIQUES USING PREFORMED PLANAR STRUCTURES
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Patent #:
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Issue Dt:
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08/19/1997
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Application #:
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08473543
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Filing Dt:
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06/07/1995
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Title:
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LAYOUT CONFIGURATION FOR AN INTEGRATED CIRCUIT GATE ARRAY
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Patent #:
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Issue Dt:
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04/28/1998
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Application #:
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08476431
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Filing Dt:
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06/07/1995
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Title:
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NON-SQUARE DIE FOR INTEGRATED CIRCUITS AND SYSTEMS CONTAINING THE SAME
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Patent #:
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Issue Dt:
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12/30/1997
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Application #:
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08477490
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Filing Dt:
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06/07/1995
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Title:
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CONFIGURATION MANAGEMENT AND AUTOMATED TEST SYSTEM FOR ASIC DESIGN SOFTWARE
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Patent #:
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Issue Dt:
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09/02/1997
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Application #:
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08477827
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Filing Dt:
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06/07/1995
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Title:
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OPTICAL CORRECTIVE TECHNIQUES WITH RETICLE FORMATION AND RETICLE STITCHING TO PROVIDE DESIGN FLEXIBILITY
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Patent #:
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Issue Dt:
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11/18/1997
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Application #:
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08489270
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Filing Dt:
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06/09/1995
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Title:
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APPARATUS AND METHOD FOR ANALYZING CIRCUITS USING REDUCED-ORDER MODELING OF LARGE LINEAR SUBSCIRCUITS
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Patent #:
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Issue Dt:
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10/20/1998
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Application #:
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08491433
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Filing Dt:
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06/16/1995
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Title:
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METHOD FOR LOCAL RIP-UP AND REROUTE OF SIGNAL PATHS IN AN IC DESIGN
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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08517142
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Filing Dt:
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08/21/1995
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Title:
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HEXAGONAL ARCHITECTURE
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08517153
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Filing Dt:
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08/21/1995
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Title:
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HEXAGONAL DRAM ARRAY
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08517171
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Filing Dt:
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08/21/1995
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Title:
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CAD FOR HEXAGONAL ARCHITECTURE
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Patent #:
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Issue Dt:
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02/16/1999
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Application #:
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08517189
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Filing Dt:
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08/21/1995
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Title:
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HEXAGONAL SENSE CELL ARCHITECTURE
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Patent #:
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Issue Dt:
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08/04/1998
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Application #:
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08517236
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Filing Dt:
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08/21/1995
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Title:
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HEXAGONAL ARCHITECTURE WITH TRIANGULAR SHAPED CELLS
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Patent #:
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Issue Dt:
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09/01/1998
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Application #:
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08517266
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Filing Dt:
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08/21/1995
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Title:
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HEXAGONAL SRAM ARCHITECTURE
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08517339
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Filing Dt:
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08/21/1995
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Title:
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TRI-DIRECTIONAL INTERCONNECT ARCHITECTURE FOR SRAM
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08517406
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Filing Dt:
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08/21/1995
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Title:
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ARCHITECTURE HAVING DIAMOND SHAPED OR PARALLELOGRAM SHAPED CELLS
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Patent #:
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Issue Dt:
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09/15/1998
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Application #:
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08517441
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Filing Dt:
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08/21/1995
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Title:
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POLYDIRECTIONAL NON-ORTHOGINAL THREE LAYER INTERCONNECT ARCHITECTURE
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Patent #:
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Issue Dt:
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01/26/1999
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Application #:
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08517451
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Filing Dt:
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08/21/1995
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Title:
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TRIANGULAR SEMICONDUCTOR 'NAND' GATE
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Patent #:
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Issue Dt:
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07/07/1998
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Application #:
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08517508
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Filing Dt:
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08/21/1995
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Title:
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HEXAGONAL FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE
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|
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Patent #:
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Issue Dt:
|
08/01/2000
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Application #:
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08517892
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Filing Dt:
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08/21/1995
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Title:
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TRIANGULAR SEMICONDUCTOR OR GATE
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|
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Patent #:
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Issue Dt:
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12/16/1997
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Application #:
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08525839
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Filing Dt:
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09/08/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING MULTIWAY PARTITIONING WITH CONSTRAINTS
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|
|
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Patent #:
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Issue Dt:
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07/21/1998
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Application #:
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08536004
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Filing Dt:
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09/29/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING GENERALIZED ASSIGNMENT
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Patent #:
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Issue Dt:
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09/02/1997
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Application #:
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08545462
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Filing Dt:
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10/19/1995
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Title:
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DEFECT ISOLATION USING SCAN-PATH TESTING AND ELECTRON BEAM PROBING IN MULTI-LEVEL HIGH DENSITY ASICS
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Patent #:
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Issue Dt:
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09/16/1997
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Application #:
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08545879
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Filing Dt:
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10/20/1995
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Title:
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METHOD AND APPARATUS FOR TESTING OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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10/21/1997
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Application #:
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08546055
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Filing Dt:
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10/20/1995
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Title:
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METHOD AND APPARATUS FOR BUILT-IN SELF-TEST WITH MULTIPLE CLOCK CIRCUITS
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Patent #:
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Issue Dt:
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10/14/1997
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Application #:
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08552421
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Filing Dt:
|
11/03/1995
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Title:
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METHOD TO DERIVE THE FUNCTIONALITY OF A DIGITAL CIRCUIT FROM ITS MASK LAYOUT
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Patent #:
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Issue Dt:
|
07/14/1998
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Application #:
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08558165
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Filing Dt:
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11/13/1995
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Title:
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METHOD FOR PRODUCING INTEGRATED CIRCUIT CHIP HAVING OPTIMIZED CELL PLACEMENT
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Patent #:
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Issue Dt:
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06/03/1997
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Application #:
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08559206
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Filing Dt:
|
11/13/1995
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Title:
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COMPUTER IMPLEMENTED METHOD FOR PRODUCING OPTIMIZED CELL PLACEMENT FOR INTEGRATED CIRCUIT CHIP
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|
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Patent #:
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Issue Dt:
|
01/27/1998
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Application #:
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08560588
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Filing Dt:
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11/20/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING FUZZY CELL CLUSTERIZATION
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|
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Patent #:
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Issue Dt:
|
11/10/1998
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Application #:
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08560834
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Filing Dt:
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11/20/1995
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Title:
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COMPUTER IMPLEMENTED METHOD FOR LEVELING INTERCONNECT WIRING DENSITY IN A CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP
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|
|
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Patent #:
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Issue Dt:
|
06/01/1999
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Application #:
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08560848
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Filing Dt:
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11/20/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING HIGHLY PARALLEL SIEVE OPTIMIZATION WITH MULTIPLE "JIGGLES"
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|
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Patent #:
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Issue Dt:
|
08/05/1997
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Application #:
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08567894
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Filing Dt:
|
12/06/1995
|
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR SEMICONDUCTOR "OR" GATE DEVICE
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|
|
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Patent #:
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Issue Dt:
|
06/30/1998
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Application #:
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08577454
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Filing Dt:
|
12/22/1995
|
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Title:
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METHOD AND APPARATUS FOR PSEUDORANDOM BOUNDARY-SCAN TESTING
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|
|
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Patent #:
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Issue Dt:
|
11/23/1999
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Application #:
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08580908
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Filing Dt:
|
12/29/1995
|
|
Title:
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HIGH DENSITY GATE ARRAY CELL ARCHITECTURE WITH METALLIZATION ROUTING TRACKS HAVING A VARIABLE PITCH
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|
|
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Patent #:
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|
Issue Dt:
|
07/28/1998
|
Application #:
|
08586174
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Filing Dt:
|
01/17/1996
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|
Title:
|
LOOP-BACK TEST SYSTEM AND METHOD
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|
|
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Patent #:
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|
Issue Dt:
|
09/24/1996
|
Application #:
|
08599289
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Filing Dt:
|
02/09/1996
|
|
Title:
|
METHOD FOR IDENTIFYING UNTESTABLE & REDUNDANT FAULTS IN SEQUENTIAL LOGIC CIRCUITS.
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