skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:059720/0223   Pages: 247
Recorded: 04/15/2022
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 935
Page 5 of 10
Pages: 1 2 3 4 5 6 7 8 9 10
1
Patent #:
6766499
Issue Dt:
07/20/2004
Application #:
09828553
Filing Dt:
04/05/2001
Title:
BUFFER CELL INSERTION AND ELECTRONIC DESIGN AUTOMATION
2
Patent #:
6453453
Issue Dt:
09/17/2002
Application #:
09833142
Filing Dt:
04/11/2001
Title:
PROCESS FOR SOLVING ASSIGNMENT PROBLEMS IN INTEGRATED CIRCUIT DESIGNS WITH UNIMODAL OBJECT PENALTY FUNCTIONS AND LINEARLY ORDERED SET OF BOXES
3
Patent #:
6598213
Issue Dt:
07/22/2003
Application #:
09836129
Filing Dt:
04/16/2001
Title:
STATIC TIMING ANALYSIS VALIDATION TOOL FOR ASIC CORES
4
Patent #:
6526553
Issue Dt:
02/25/2003
Application #:
09837492
Filing Dt:
04/18/2001
Title:
CHIP CORE SIZE ESTIMATION
5
Patent #:
6637016
Issue Dt:
10/21/2003
Application #:
09841824
Filing Dt:
04/25/2001
Title:
ASSIGNMENT OF CELL COORDINATES
6
Patent #:
6553551
Issue Dt:
04/22/2003
Application #:
09841825
Filing Dt:
04/25/2001
Title:
TIMING RECOMPUTATION
7
Patent #:
6470487
Issue Dt:
10/22/2002
Application #:
09842350
Filing Dt:
04/25/2001
Publication #:
US20020162085
Pub Dt:
10/31/2002
Title:
PARALLELIZATION OF RESYNTHESIS
8
Patent #:
6513148
Issue Dt:
01/28/2003
Application #:
09844361
Filing Dt:
04/27/2001
Title:
DENSITY DRIVEN ASSIGNMENT OF COORDINATES
9
Patent #:
6502230
Issue Dt:
12/31/2002
Application #:
09847460
Filing Dt:
05/02/2001
Title:
CIRCUIT MODELING
10
Patent #:
6530073
Issue Dt:
03/04/2003
Application #:
09847838
Filing Dt:
04/30/2001
Publication #:
US20020162086
Pub Dt:
10/31/2002
Title:
RTL ANNOTATION TOOL FOR LAYOUT INDUCED NETLIST CHANGES
11
Patent #:
6493851
Issue Dt:
12/10/2002
Application #:
09848489
Filing Dt:
05/03/2001
Title:
METHOD AND APPARATUS FOR INDENTIFYING CAUSES OF POOR SILICON-TO-SIMULATION CORRELATION
12
Patent #:
7076406
Issue Dt:
07/11/2006
Application #:
09849691
Filing Dt:
05/04/2001
Title:
MINIMAL BENDS CONNECTION MODELS FOR WIRE DENSITY CALCULATION
13
Patent #:
6487698
Issue Dt:
11/26/2002
Application #:
09849919
Filing Dt:
05/04/2001
Title:
PROCESS, APPARATUS AND PROGRAM FOR TRANSFORMING PROGRAM LANGUAGE DESCRIPTION OF AN IC TO AN RTL DESCRIPTION
14
Patent #:
6507939
Issue Dt:
01/14/2003
Application #:
09858166
Filing Dt:
05/15/2001
Title:
NET DELAY OPTIMIZATION WITH RAMPTIME VIOLATION REMOVAL
15
Patent #:
6587999
Issue Dt:
07/01/2003
Application #:
09859149
Filing Dt:
05/15/2001
Title:
MODELING DELAYS FOR SMALL NETS IN AN INTEGRATED CIRCUIT DESIGN
16
Patent #:
6664801
Issue Dt:
12/16/2003
Application #:
09862045
Filing Dt:
05/21/2001
Title:
IDDQ TEST METHODOLOGY BASED ON THE SENSITIVITY OF FAULT CURRENT TO POWER SUPPLY VARIATIONS
17
Patent #:
6680150
Issue Dt:
01/20/2004
Application #:
09866137
Filing Dt:
05/25/2001
Publication #:
US20020177078
Pub Dt:
11/28/2002
Title:
SUPPRESSION OF SIDE-LOBE PRINTING BY SHAPE ENGINEERING
18
Patent #:
6438730
Issue Dt:
08/20/2002
Application #:
09866661
Filing Dt:
05/30/2001
Title:
RTL CODE OPTIMIZATION FOR RESOURCE SHARING STRUCTURES
19
Patent #:
6463572
Issue Dt:
10/08/2002
Application #:
09871129
Filing Dt:
05/31/2001
Title:
IC TIMING ANALYSIS WITH KNOWN FALSE PATHS
20
Patent #:
6502222
Issue Dt:
12/31/2002
Application #:
09875314
Filing Dt:
06/04/2001
Title:
METHOD OF CLOCK BUFFER PARTITIONING TO MINIMIZE CLOCK SKEW FOR AN INTEGRATED CIRCUIT DESIGN
21
Patent #:
6442737
Issue Dt:
08/27/2002
Application #:
09876736
Filing Dt:
06/06/2001
Title:
METHOD OF GENERATING AN OPTIMAL CLOCK BUFFER SET FOR MINIMIZING CLOCK SKEW IN BALANCED CLOCK TREES
22
Patent #:
6792578
Issue Dt:
09/14/2004
Application #:
09878499
Filing Dt:
06/11/2001
Title:
HARD MACRO HAVING AN ANTENNA RULE VIOLATION FREE INPUT/OUTPUT PORTS
23
Patent #:
6442738
Issue Dt:
08/27/2002
Application #:
09879297
Filing Dt:
06/12/2001
Title:
RTL BACK ANNOTATOR
24
Patent #:
6615397
Issue Dt:
09/02/2003
Application #:
09879380
Filing Dt:
06/12/2001
Title:
OPTIMAL CLOCK TIMING SCHEDULE FOR AN INTEGRATED CIRCUIT
25
Patent #:
6449751
Issue Dt:
09/10/2002
Application #:
09879417
Filing Dt:
06/12/2001
Title:
METHOD OF ANALYZING STATIC CURRENT TEST VECTORS WITH REDUCED FILE SIZES FOR SEMICONDUCTOR INTEGRATED CIRCUITS
26
Patent #:
6694495
Issue Dt:
02/17/2004
Application #:
09879506
Filing Dt:
06/12/2001
Title:
METHOD OF ANALYZING STATIC CURRENT TEST VECTORS FOR SEMICONDUCTOR INTEGRATED CIRCUITS
27
Patent #:
6704915
Issue Dt:
03/09/2004
Application #:
09879643
Filing Dt:
06/12/2001
Title:
PROCESS FOR FAST CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN
28
Patent #:
6934410
Issue Dt:
08/23/2005
Application #:
09879664
Filing Dt:
06/12/2001
Title:
MASK CORRECTION FOR PHOTOLITHOGRAPHIC PROCESSES
29
Patent #:
6868535
Issue Dt:
03/15/2005
Application #:
09879841
Filing Dt:
06/12/2001
Title:
METHOD AND APPARATUS FOR OPTIMIZING THE TIMING OF INTEGRATED CIRCUITS
30
Patent #:
6467067
Issue Dt:
10/15/2002
Application #:
09879845
Filing Dt:
06/12/2001
Title:
EPSILON-DISCREPANT SELF-TEST TECHNIQUE
31
Patent #:
6611953
Issue Dt:
08/26/2003
Application #:
09879846
Filing Dt:
06/12/2001
Title:
MASK CORRECTION OPTIMIZATION
32
Patent #:
6453451
Issue Dt:
09/17/2002
Application #:
09880607
Filing Dt:
06/12/2001
Title:
GENERATING STANDARD DELAY FORMAT FILES WITH CONDITIONAL PATH DELAY FOR DESIGNING INTEGRATED CIRCUITS
33
Patent #:
6928598
Issue Dt:
08/09/2005
Application #:
09880675
Filing Dt:
06/13/2001
Title:
SCAN METHOD FOR BUILT-IN-SELF-REPAIR (BISR)
34
Patent #:
6609238
Issue Dt:
08/19/2003
Application #:
09882114
Filing Dt:
06/15/2001
Title:
METHOD OF CONTROL CELL PLACEMENT TO MINIMIZE CONNECTION LENGTH AND CELL DELAY
35
Patent #:
6581194
Issue Dt:
06/17/2003
Application #:
09882899
Filing Dt:
06/15/2001
Title:
METHOD FOR REDUCING SIMULATION OVERHEAD FOR EXTERNAL MODELS
36
Patent #:
7050582
Issue Dt:
05/23/2006
Application #:
09883733
Filing Dt:
06/18/2001
Title:
PSEUDO-RANDOM ONE-TO-ONE CIRCUIT SYNTHESIS
37
Patent #:
6550044
Issue Dt:
04/15/2003
Application #:
09885589
Filing Dt:
06/19/2001
Title:
METHOD IN INTEGRATING CLOCK TREE SYNTHESIS AND TIMING OPTIMIZATION FOR AN INTEGRATED CIRCUIT DESIGN
38
Patent #:
6507937
Issue Dt:
01/14/2003
Application #:
09885596
Filing Dt:
06/19/2001
Title:
METHOD OF GLOBAL PLACEMENT OF CONTROL CELLS AND HARDMAC PINS IN A DATAPATH MACRO FOR AN INTEGRATED CIRCUIT DESIGN
39
Patent #:
6650139
Issue Dt:
11/18/2003
Application #:
09885896
Filing Dt:
06/20/2001
Title:
MODULAR COLLECTION OF SPARE GATES FOR USE IN HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS
40
Patent #:
6588003
Issue Dt:
07/01/2003
Application #:
09892241
Filing Dt:
06/26/2001
Title:
METHOD OF CONTROL CELL PLACEMENT FOR DATAPATH MACROS IN INTEGRATED CIRCUIT DESIGNS
41
Patent #:
6532577
Issue Dt:
03/11/2003
Application #:
09894618
Filing Dt:
06/27/2001
Title:
TIMING DRIVEN INTERCONNECT ANALYSIS
42
Patent #:
6611951
Issue Dt:
08/26/2003
Application #:
09895668
Filing Dt:
06/29/2001
Title:
METHOD FOR ESTIMATING CELL POROSITY OF HARDMACS
43
Patent #:
6951017
Issue Dt:
09/27/2005
Application #:
09916958
Filing Dt:
07/27/2001
Title:
DESIGN SYSTEM UPGRADE MIGRATION
44
Patent #:
6701511
Issue Dt:
03/02/2004
Application #:
09928471
Filing Dt:
08/13/2001
Title:
OPTICAL AND ETCH PROXIMITY CORRECTION
45
Patent #:
6973421
Issue Dt:
12/06/2005
Application #:
09934051
Filing Dt:
08/21/2001
Title:
BZFLASH SUBCIRCUIT TO DYNAMICALLY SUPPLY BZ CODES FOR CONTROLLED IMPEDANCE BUFFER DEVELOPMENT, VERIFICATION AND SYSTEM LEVEL SIMULATIONS
46
Patent #:
6587991
Issue Dt:
07/01/2003
Application #:
09941359
Filing Dt:
08/28/2001
Title:
OPTIMIZED METAL STACK STRATEGY
47
Patent #:
6629304
Issue Dt:
09/30/2003
Application #:
09955698
Filing Dt:
09/19/2001
Title:
CELL PLACEMENT IN INTEGRATED CIRCUIT CHIPS TO REMOVE CELL OVERLAP, ROW OVERFLOW AND OPTIMAL PLACEMENT OF DUAL HEIGHT CELLS
48
Patent #:
6643832
Issue Dt:
11/04/2003
Application #:
09964011
Filing Dt:
09/26/2001
Title:
VIRTUAL TREE-BASED NETLIST MODEL AND METHOD OF DELAY ESTIMATION FOR AN INTEGRATED CIRCUIT DESIGN
49
Patent #:
7020589
Issue Dt:
03/28/2006
Application #:
09964030
Filing Dt:
09/26/2001
Title:
METHOD AND APPARATUS FOR ADAPTIVE TIMING OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN
50
Patent #:
6907590
Issue Dt:
06/14/2005
Application #:
09968008
Filing Dt:
10/02/2001
Title:
INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
51
Patent #:
6907586
Issue Dt:
06/14/2005
Application #:
09968009
Filing Dt:
10/02/2001
Title:
INTERGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
52
Patent #:
6792579
Issue Dt:
09/14/2004
Application #:
09972100
Filing Dt:
10/05/2001
Publication #:
US20030084410
Pub Dt:
05/01/2003
Title:
SPICE TO VERILOG NETLIST TRANSLATOR AND DESIGN METHODS USING SPICE TO VERILOG AND VERILOG TO SPICE TRANSLATION
53
Patent #:
7051318
Issue Dt:
05/23/2006
Application #:
09973153
Filing Dt:
10/09/2001
Title:
WEB BASED OLA MEMORY GENERATOR
54
Patent #:
6931606
Issue Dt:
08/16/2005
Application #:
09978141
Filing Dt:
10/15/2001
Title:
AUTOMATIC METHOD AND SYSTEM FOR INSTANTIATING BUILT-IN -TEST (BIST) MODULES IN ASIC MEMORY DESIGNS
55
Patent #:
6594805
Issue Dt:
07/15/2003
Application #:
09986912
Filing Dt:
11/13/2001
Title:
INTEGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
56
Patent #:
6550045
Issue Dt:
04/15/2003
Application #:
09991574
Filing Dt:
11/20/2001
Title:
CHANGING CLOCK DELAYS IN AN INTEGRATED CIRCUIT FOR SKEW OPTIMIZATION
57
Patent #:
6788091
Issue Dt:
09/07/2004
Application #:
09993015
Filing Dt:
11/05/2001
Title:
METHOD AND APPARATUS FOR AUTOMATIC MARKING OF INTERGRATED CIRCUITS IN WAFER SCALE TESTING
58
Patent #:
6966020
Issue Dt:
11/15/2005
Application #:
09994299
Filing Dt:
11/26/2001
Title:
IDENTIFYING FAULTY PROGRAMMABLE INTERCONNECT RESOURCES OF FIELD PROGRAMMABLE GATE ARRAYS
59
Patent #:
6745358
Issue Dt:
06/01/2004
Application #:
09997757
Filing Dt:
11/30/2001
Title:
ENHANCED FAULT COVERAGE
60
Patent #:
7006962
Issue Dt:
02/28/2006
Application #:
09997888
Filing Dt:
11/29/2001
Title:
DISTRIBUTED DELAY PREDICTION OF MULTI-MILLION GATE DEEP SUB-MICRON ASIC DESIGNS
61
Patent #:
6668359
Issue Dt:
12/23/2003
Application #:
10003823
Filing Dt:
10/31/2001
Title:
VERILOG TO VITAL TRANSLATOR
62
Patent #:
6769107
Issue Dt:
07/27/2004
Application #:
10005062
Filing Dt:
12/03/2001
Title:
METHOD AND SYSTEM FOR IMPLEMENTING INCREMENTAL CHANGE TO CIRCUIT DESIGN
63
Patent #:
6651239
Issue Dt:
11/18/2003
Application #:
10008089
Filing Dt:
11/13/2001
Title:
DIRECT TRANSFORMATION OF ENGINEERING CHANGE ORDERS TO SYNTHESIZED IC CHIP DESIGNS
64
Patent #:
7065683
Issue Dt:
06/20/2006
Application #:
10011796
Filing Dt:
12/05/2001
Title:
LONG PATH AT-SPEED TESTING
65
Patent #:
6675363
Issue Dt:
01/06/2004
Application #:
10014746
Filing Dt:
10/24/2001
Title:
GRAPHICAL USER INTERFACE TO INTEGRATE THIRD PARTY TOOLS IN POWER INTEGRITY ANALYSIS
66
Patent #:
6999910
Issue Dt:
02/14/2006
Application #:
10015194
Filing Dt:
11/20/2001
Publication #:
US20030097241
Pub Dt:
05/22/2003
Title:
METHOD AND APPARATUS FOR IMPLEMENTING A METAMETHODOLOGY
67
Patent #:
6654946
Issue Dt:
11/25/2003
Application #:
10021414
Filing Dt:
10/30/2001
Title:
INTERSCALABLE INTERCONNECT
68
Patent #:
6792584
Issue Dt:
09/14/2004
Application #:
10021619
Filing Dt:
10/30/2001
Title:
SYSTEM AND METHOD FOR DESIGNING AN INTEGRATED CIRCUIT
69
Patent #:
6751783
Issue Dt:
06/15/2004
Application #:
10021696
Filing Dt:
10/30/2001
Title:
SYSTEM AND METHOD FOR OPTIMIZING AN INTEGRATED CIRCUIT DESIGN
70
Patent #:
6658628
Issue Dt:
12/02/2003
Application #:
10025123
Filing Dt:
12/19/2001
Title:
DEVELOPMENT OF HARDMAC TECHNOLOGY FILES (CLF, TECH AND SYNLIB) FOR RTL AND FULL GATE LEVEL NETLISTS
71
Patent #:
6845495
Issue Dt:
01/18/2005
Application #:
10027642
Filing Dt:
12/20/2001
Publication #:
US20030121017
Pub Dt:
06/26/2003
Title:
MULTIDIRECTIONAL ROUTER
72
Patent #:
6691288
Issue Dt:
02/10/2004
Application #:
10034535
Filing Dt:
12/27/2001
Title:
METHOD TO DEBUG IKOS METHOD
73
Patent #:
6889366
Issue Dt:
05/03/2005
Application #:
10034839
Filing Dt:
12/27/2001
Publication #:
US20030126562
Pub Dt:
07/03/2003
Title:
SYSTEM AND METHOD FOR COEVOLUTIONARY CIRCUIT DESIGN
74
Patent #:
6640333
Issue Dt:
10/28/2003
Application #:
10044781
Filing Dt:
01/10/2002
Publication #:
US20030131335
Pub Dt:
07/10/2003
Title:
ARCHITECTURE FOR A SEA OF PLATFORMS
75
Patent #:
6647538
Issue Dt:
11/11/2003
Application #:
10045473
Filing Dt:
11/08/2001
Title:
APPARATUS AND METHOD FOR SIGNAL SKEW CHARACTERIZATION UTILIZING CLOCK DIVISION
76
Patent #:
6757881
Issue Dt:
06/29/2004
Application #:
10059480
Filing Dt:
01/29/2002
Publication #:
US20030145302
Pub Dt:
07/31/2003
Title:
POWER ROUTING WITH OBSTACLES
77
Patent #:
6701503
Issue Dt:
03/02/2004
Application #:
10072008
Filing Dt:
02/07/2002
Publication #:
US20030149952
Pub Dt:
08/07/2003
Title:
OVERLAP REMOVER MANAGER
78
Patent #:
7043718
Issue Dt:
05/09/2006
Application #:
10077066
Filing Dt:
02/15/2002
Title:
SYSTEM REAL-TIME ANALYSIS TOOL
79
Patent #:
6757877
Issue Dt:
06/29/2004
Application #:
10083411
Filing Dt:
02/27/2002
Publication #:
US20030163797
Pub Dt:
08/28/2003
Title:
SYSTEM AND METHOD FOR IDENTIFYING AND ELIMINATING BOTTLENECKS IN INTEGRATED CIRCUIT DESIGNS
80
Patent #:
6662349
Issue Dt:
12/09/2003
Application #:
10086232
Filing Dt:
02/27/2002
Publication #:
US20030163795
Pub Dt:
08/28/2003
Title:
METHOD OF REPEATER INSERTION FOR HIERARCHICAL INTEGRATED CIRCUIT DESIGN
81
Patent #:
6615401
Issue Dt:
09/02/2003
Application #:
10092195
Filing Dt:
03/06/2002
Title:
BLOCKED NET BUFFER INSERTION
82
Patent #:
6813758
Issue Dt:
11/02/2004
Application #:
10097419
Filing Dt:
03/14/2002
Publication #:
US20030177451
Pub Dt:
09/18/2003
Title:
OPTICAL PROXIMITY CORRECTION DRIVEN HIERARCHY
83
Patent #:
6904586
Issue Dt:
06/07/2005
Application #:
10105579
Filing Dt:
03/25/2002
Title:
INTEGRATED CIRCUIT HAVING INTEGRATED PROGRAMMABLE GATE ARRAY AND FIELD PROGRAMMABLE GATE ARRAY, AND METHOD OF OPERATING THE SAME
84
Patent #:
6934597
Issue Dt:
08/23/2005
Application #:
10106432
Filing Dt:
03/26/2002
Title:
INTEGRATED CIRCUIT HAVING INTEGRATED PROGRAMMABLE GATE ARRAY AND METHOD OF OPERATING THE SAME
85
Patent #:
7017096
Issue Dt:
03/21/2006
Application #:
10106960
Filing Dt:
03/26/2002
Publication #:
US20030188245
Pub Dt:
10/02/2003
Title:
SEQUENTIAL TEST PATTERN GENERATION USING CLOCK-CONTROL DESIGN FOR TESTABILITY STRUCTURES
86
Patent #:
6842750
Issue Dt:
01/11/2005
Application #:
10108286
Filing Dt:
03/27/2002
Publication #:
US20030187815
Pub Dt:
10/02/2003
Title:
SYMBOLIC SIMULATION DRIVEN NETLIST SIMPLIFICATION
87
Patent #:
6701493
Issue Dt:
03/02/2004
Application #:
10109113
Filing Dt:
03/27/2002
Publication #:
US20030188274
Pub Dt:
10/02/2003
Title:
FLOOR PLAN TESTER FOR INTEGRATED CIRCUIT DESIGN
88
Patent #:
7024641
Issue Dt:
04/04/2006
Application #:
10119821
Filing Dt:
04/10/2002
Title:
INTEGRATED CIRCUIT HAVING A PROGRAMMABLE GATE ARRAY AND A FIELD PROGRAMMABLE GATE ARRAY AND METHODS OF DESIGNING AND MANUFACTURING THE SAME USING TESTING IC BEFORE CONFIGURING FPGA
89
Patent #:
7028238
Issue Dt:
04/11/2006
Application #:
10125675
Filing Dt:
04/18/2002
Publication #:
US20030200045
Pub Dt:
10/23/2003
Title:
INPUT/OUTPUT CHARACTERIZATION CHAIN FOR AN INTEGRATED CIRCUIT
90
Patent #:
6948114
Issue Dt:
09/20/2005
Application #:
10132360
Filing Dt:
04/25/2002
Publication #:
US20030204809
Pub Dt:
10/30/2003
Title:
MULTI-RESOLUTION VITERBI DECODING TECHNIQUE
91
Patent #:
NONE
Issue Dt:
Application #:
10135189
Filing Dt:
04/30/2002
Publication #:
US20030204704
Pub Dt:
10/30/2003
Title:
Extended instruction sets in a platform architecture
92
Patent #:
7016748
Issue Dt:
03/21/2006
Application #:
10135869
Filing Dt:
04/30/2002
Publication #:
US20030204369
Pub Dt:
10/30/2003
Title:
COLLABORATIVE INTEGRATION OF HYBRID ELECTRONIC AND MICRO AND SUB-MICRO LEVEL AGGREGATES
93
Patent #:
6683476
Issue Dt:
01/27/2004
Application #:
10140967
Filing Dt:
05/08/2002
Publication #:
US20030210076
Pub Dt:
11/13/2003
Title:
CONTACT RING ARCHITECTURE
94
Patent #:
7539680
Issue Dt:
05/26/2009
Application #:
10143155
Filing Dt:
05/10/2002
Publication #:
US20030212718
Pub Dt:
11/13/2003
Title:
REVISION CONTROL FOR DATABASE OF EVOLVED DESIGN
95
Patent #:
6898767
Issue Dt:
05/24/2005
Application #:
10144101
Filing Dt:
05/09/2002
Publication #:
US20030212967
Pub Dt:
11/13/2003
Title:
METHOD AND APPARATUS FOR CUSTOM DESIGN IN A STANDARD CELL DESIGN ENVIRONMENT
96
Patent #:
6931612
Issue Dt:
08/16/2005
Application #:
10146363
Filing Dt:
05/15/2002
Title:
DESIGN AND OPTIMIZATION METHODS FOR INTEGRATED CIRCUITS
97
Patent #:
6775811
Issue Dt:
08/10/2004
Application #:
10151826
Filing Dt:
05/22/2002
Publication #:
US20030221177
Pub Dt:
11/27/2003
Title:
CHIP DESIGN METHOD FOR DESIGNING INTEGRATED CIRCUIT CHIPS WITH EMBEDDED MEMORIES
98
Patent #:
6665850
Issue Dt:
12/16/2003
Application #:
10153570
Filing Dt:
05/22/2002
Publication #:
US20030221176
Pub Dt:
11/27/2003
Title:
SPANNING TREE METHOD FOR K-DIMENSIONAL SPACE
99
Patent #:
7035446
Issue Dt:
04/25/2006
Application #:
10155620
Filing Dt:
05/22/2002
Publication #:
US20030219154
Pub Dt:
11/27/2003
Title:
QUALITY MEASUREMENT OF AN AERIAL IMAGE
100
Patent #:
6829754
Issue Dt:
12/07/2004
Application #:
10163208
Filing Dt:
06/04/2002
Title:
METHOD AND SYSTEM FOR CHECKING FOR POWER ERRORS IN ASIC DESIGNS
Assignor
1
CORTLAND CAPITAL MARKET SERVICES LLC
Exec Dt:
04/01/2022
Assignees
1
HILCO PATENT ACQUISITION 56, LLC
401 N. MICHIGAN AVE., SUITE 1630
CHICAGO, ILLINOIS 60611
2
BELL SEMICONDUCTOR, LLC
401 N. MICHIGAN AVE., SUITE 1630
CHICAGO, ILLINOIS 60611
3
BELL NORTHERN RESEARCH, LLC
401 N. MICHIGAN AVE., SUITE 1630
CHICAGO, ILLINOIS 60611
Correspondence name and address
JOSHUA GAMMON
401 N. MICHIGAN AVE.
SUITE 1630
CHICAGO, IL 60611

Search Results as of: 05/12/2024 08:05 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT